2 FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.
\r
4 ***************************************************************************
\r
8 * + New to FreeRTOS, *
\r
9 * + Wanting to learn FreeRTOS or multitasking in general quickly *
\r
10 * + Looking for basic training, *
\r
11 * + Wanting to improve your FreeRTOS skills and productivity *
\r
13 * then take a look at the FreeRTOS eBook *
\r
15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
\r
16 * http://www.FreeRTOS.org/Documentation *
\r
18 * A pdf reference manual is also available. Both are usually delivered *
\r
19 * to your inbox within 20 minutes to two hours when purchased between 8am *
\r
20 * and 8pm GMT (although please allow up to 24 hours in case of *
\r
21 * exceptional circumstances). Thank you for your support! *
\r
23 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 ***NOTE*** The exception to the GPL is included to allow you to distribute
\r
31 a combined work that includes FreeRTOS without being obliged to provide the
\r
32 source code for proprietary components outside of the FreeRTOS kernel.
\r
33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
\r
34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
47 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
50 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
51 licensing and training services.
\r
54 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
\r
56 /* Kernel includes. */
\r
57 #include "FreeRTOS.h"
\r
61 /* Hardware specific includes. */
\r
62 #include "EthDev_LPC17xx.h"
\r
64 /* Time to wait between each inspection of the link status. */
\r
65 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
\r
67 /* Short delay used in several places during the initialisation process. */
\r
68 #define emacSHORT_DELAY ( 2 )
\r
70 /* Hardware specific bit definitions. */
\r
71 #define emacLINK_ESTABLISHED ( 0x0020)
\r
72 #define emacFULL_DUPLEX_ENABLED ( 0x0010 )
\r
73 #define emac10BASE_T_MODE ( 0x0004 )
\r
74 #define emacPINSEL2_VALUE ( 0x50150105 )
\r
75 #define emacDIV_44 ( 0x28 )
\r
77 /* If no buffers are available, then wait this long before looking again.... */
\r
78 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
\r
80 /* ...and don't look more than this many times. */
\r
81 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
83 /* Index to the Tx descriptor that is always used first for every Tx. The second
\r
84 descriptor is then used to re-send in order to speed up the uIP Tx process. */
\r
85 #define emacTX_DESC_INDEX ( 0 )
\r
87 /*-----------------------------------------------------------*/
\r
90 * Configure both the Rx and Tx descriptors during the init process.
\r
92 static void prvInitDescriptors( void );
\r
95 * Setup the IO and peripherals required for Ethernet communication.
\r
97 static void prvSetupEMACHardware( void );
\r
100 * Control the auto negotiate process.
\r
102 static void prvConfigurePHY( void );
\r
105 * Wait for a link to be established, then setup the PHY according to the link
\r
108 static long prvSetupLinkStatus( void );
\r
111 * Search the pool of buffers to find one that is free. If a buffer is found
\r
112 * mark it as in use before returning its address.
\r
114 static unsigned char *prvGetNextBuffer( void );
\r
117 * Return an allocated buffer to the pool of free buffers.
\r
119 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
122 * Send lValue to the lPhyReg within the PHY.
\r
124 static long prvWritePHY( long lPhyReg, long lValue );
\r
127 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
\r
128 * pdFALSE if there is an error.
\r
130 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
\r
132 /*-----------------------------------------------------------*/
\r
134 /* The semaphore used to wake the uIP task when data arrives. */
\r
135 extern xSemaphoreHandle xEMACSemaphore;
\r
137 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
\r
138 If the index contains a 1 then the buffer within pool is in use, if it
\r
139 contains a 0 then the buffer is free. */
\r
140 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
\r
142 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
\r
143 allocated within this file. */
\r
144 unsigned char * uip_buf;
\r
146 /* Store the length of the data being sent so the data can be sent twice. The
\r
147 value will be set back to 0 once the data has been sent twice. */
\r
148 static unsigned short usSendLen = 0;
\r
150 /*-----------------------------------------------------------*/
\r
152 long lEMACInit( void )
\r
154 long lReturn = pdPASS;
\r
155 unsigned long ulID1, ulID2;
\r
157 /* Reset peripherals, configure port pins and registers. */
\r
158 prvSetupEMACHardware();
\r
160 /* Check the PHY part number is as expected. */
\r
161 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
\r
162 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
\r
163 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )
\r
165 /* Set the Ethernet MAC Address registers */
\r
166 EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
\r
167 EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
\r
168 EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
\r
170 /* Initialize Tx and Rx DMA Descriptors */
\r
171 prvInitDescriptors();
\r
173 /* Receive broadcast and perfect match packets */
\r
174 EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
\r
176 /* Setup the PHY. */
\r
184 /* Check the link status. */
\r
185 if( lReturn == pdPASS )
\r
187 lReturn = prvSetupLinkStatus();
\r
190 if( lReturn == pdPASS )
\r
192 /* Initialise uip_buf to ensure it points somewhere valid. */
\r
193 uip_buf = prvGetNextBuffer();
\r
195 /* Reset all interrupts */
\r
196 EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
\r
198 /* Enable receive and transmit mode of MAC Ethernet core */
\r
199 EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
\r
200 EMAC->MAC1 |= MAC1_REC_EN;
\r
205 /*-----------------------------------------------------------*/
\r
207 static unsigned char *prvGetNextBuffer( void )
\r
210 unsigned char *pucReturn = NULL;
\r
211 unsigned long ulAttempts = 0;
\r
213 while( pucReturn == NULL )
\r
215 /* Look through the buffers to find one that is not in use by
\r
217 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
\r
219 if( ucBufferInUse[ x ] == pdFALSE )
\r
221 ucBufferInUse[ x ] = pdTRUE;
\r
222 pucReturn = ( unsigned char * ) ETH_BUF( x );
\r
227 /* Was a buffer found? */
\r
228 if( pucReturn == NULL )
\r
232 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
237 /* Wait then look again. */
\r
238 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
244 /*-----------------------------------------------------------*/
\r
246 static void prvInitDescriptors( void )
\r
248 long x, lNextBuffer = 0;
\r
250 for( x = 0; x < NUM_RX_FRAG; x++ )
\r
252 /* Allocate the next Ethernet buffer to this descriptor. */
\r
253 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
\r
254 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
\r
255 RX_STAT_INFO( x ) = 0;
\r
256 RX_STAT_HASHCRC( x ) = 0;
\r
258 /* The Ethernet buffer is now in use. */
\r
259 ucBufferInUse[ lNextBuffer ] = pdTRUE;
\r
263 /* Set EMAC Receive Descriptor Registers. */
\r
264 EMAC->RxDescriptor = RX_DESC_BASE;
\r
265 EMAC->RxStatus = RX_STAT_BASE;
\r
266 EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
\r
268 /* Rx Descriptors Point to 0 */
\r
269 EMAC->RxConsumeIndex = 0;
\r
271 /* A buffer is not allocated to the Tx descriptors until they are actually
\r
273 for( x = 0; x < NUM_TX_FRAG; x++ )
\r
275 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
\r
276 TX_DESC_CTRL( x ) = 0;
\r
277 TX_STAT_INFO( x ) = 0;
\r
280 /* Set EMAC Transmit Descriptor Registers. */
\r
281 EMAC->TxDescriptor = TX_DESC_BASE;
\r
282 EMAC->TxStatus = TX_STAT_BASE;
\r
283 EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
\r
285 /* Tx Descriptors Point to 0 */
\r
286 EMAC->TxProduceIndex = 0;
\r
288 /*-----------------------------------------------------------*/
\r
290 static void prvSetupEMACHardware( void )
\r
295 /* Enable P1 Ethernet Pins. */
\r
296 PINCON->PINSEL2 = emacPINSEL2_VALUE;
\r
297 PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
\r
299 /* Power Up the EMAC controller. */
\r
300 SC->PCONP |= PCONP_PCENET;
\r
301 vTaskDelay( emacSHORT_DELAY );
\r
303 /* Reset all EMAC internal modules. */
\r
304 EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
\r
305 EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
\r
307 /* A short delay after reset. */
\r
308 vTaskDelay( emacSHORT_DELAY );
\r
310 /* Initialize MAC control registers. */
\r
311 EMAC->MAC1 = MAC1_PASS_ALL;
\r
312 EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
\r
313 EMAC->MAXF = ETH_MAX_FLEN;
\r
314 EMAC->CLRT = CLRT_DEF;
\r
315 EMAC->IPGR = IPGR_DEF;
\r
316 EMAC->MCFG = emacDIV_44;
\r
318 /* Enable Reduced MII interface. */
\r
319 EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
\r
321 /* Reset Reduced MII Logic. */
\r
322 EMAC->SUPP = SUPP_RES_RMII;
\r
323 vTaskDelay( emacSHORT_DELAY );
\r
326 /* Put the PHY in reset mode */
\r
327 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
328 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
330 /* Wait for hardware reset to end. */
\r
331 for( x = 0; x < 100; x++ )
\r
333 vTaskDelay( emacSHORT_DELAY * 5 );
\r
334 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
\r
335 if( !( us & MCFG_RES_MII ) )
\r
337 /* Reset complete */
\r
342 /*-----------------------------------------------------------*/
\r
344 static void prvConfigurePHY( void )
\r
349 /* Auto negotiate the configuration. */
\r
350 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
\r
352 vTaskDelay( emacSHORT_DELAY * 5 );
\r
354 for( x = 0; x < 10; x++ )
\r
356 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
\r
358 if( us & PHY_AUTO_NEG_COMPLETE )
\r
363 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
367 /*-----------------------------------------------------------*/
\r
369 static long prvSetupLinkStatus( void )
\r
371 long lReturn = pdFAIL, x;
\r
372 unsigned short usLinkStatus;
\r
374 /* Wait with timeout for the link to be established. */
\r
375 for( x = 0; x < 10; x++ )
\r
377 usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );
\r
378 if( usLinkStatus != 0x00 )
\r
380 /* Link is established. */
\r
385 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
388 if( lReturn == pdPASS )
\r
390 /* Configure Full/Half Duplex mode. */
\r
391 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
\r
393 /* Full duplex is enabled. */
\r
394 EMAC->MAC2 |= MAC2_FULL_DUP;
\r
395 EMAC->Command |= CR_FULL_DUP;
\r
396 EMAC->IPGT = IPGT_FULL_DUP;
\r
400 /* Half duplex mode. */
\r
401 EMAC->IPGT = IPGT_HALF_DUP;
\r
404 /* Configure 100MBit/10MBit mode. */
\r
405 if( usLinkStatus & emac10BASE_T_MODE )
\r
412 /* 100MBit mode. */
\r
413 EMAC->SUPP = SUPP_SPEED;
\r
419 /*-----------------------------------------------------------*/
\r
421 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
425 /* Return a buffer to the pool of free buffers. */
\r
426 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
\r
428 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
\r
430 ucBufferInUse[ ul ] = pdFALSE;
\r
435 /*-----------------------------------------------------------*/
\r
437 unsigned long ulGetEMACRxData( void )
\r
439 unsigned long ulLen = 0;
\r
442 if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
\r
444 /* Mark the current buffer as free as uip_buf is going to be set to
\r
445 the buffer that contains the received data. */
\r
446 prvReturnBuffer( uip_buf );
\r
448 ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
\r
449 uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
\r
451 /* Allocate a new buffer to the descriptor. */
\r
452 RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
\r
454 /* Move the consume index onto the next position, ensuring it wraps to
\r
455 the beginning at the appropriate place. */
\r
456 lIndex = EMAC->RxConsumeIndex;
\r
459 if( lIndex >= NUM_RX_FRAG )
\r
464 EMAC->RxConsumeIndex = lIndex;
\r
469 /*-----------------------------------------------------------*/
\r
471 void vSendEMACTxData( unsigned short usTxDataLen )
\r
473 unsigned long ulAttempts = 0UL;
\r
475 /* Check to see if the Tx descriptor is free, indicated by its buffer being
\r
477 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
\r
479 /* Wait for the Tx descriptor to become available. */
\r
480 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
483 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
\r
485 /* Something has gone wrong as the Tx descriptor is still in use.
\r
486 Clear it down manually, the data it was sending will probably be
\r
488 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
493 /* Setup the Tx descriptor for transmission. Remember the length of the
\r
494 data being sent so the second descriptor can be used to send it again from
\r
496 usSendLen = usTxDataLen;
\r
497 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
\r
498 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
\r
499 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
\r
501 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
\r
502 uip_buf = prvGetNextBuffer();
\r
504 /*-----------------------------------------------------------*/
\r
506 static long prvWritePHY( long lPhyReg, long lValue )
\r
508 const long lMaxTime = 10;
\r
511 EMAC->MADR = KS8721_DEF_ADR | lPhyReg;
\r
512 EMAC->MWTD = lValue;
\r
515 for( x = 0; x < lMaxTime; x++ )
\r
517 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
519 /* Operation has finished. */
\r
523 vTaskDelay( emacSHORT_DELAY );
\r
535 /*-----------------------------------------------------------*/
\r
537 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
\r
540 const long lMaxTime = 10;
\r
542 EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;
\r
543 EMAC->MCMD = MCMD_READ;
\r
545 for( x = 0; x < lMaxTime; x++ )
\r
547 /* Operation has finished. */
\r
548 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
553 vTaskDelay( emacSHORT_DELAY );
\r
558 if( x >= lMaxTime )
\r
560 *plStatus = pdFAIL;
\r
563 return( EMAC->MRDD );
\r
565 /*-----------------------------------------------------------*/
\r
567 void vEMAC_ISR( void )
\r
569 unsigned long ulStatus;
\r
570 long lHigherPriorityTaskWoken = pdFALSE;
\r
572 ulStatus = EMAC->IntStatus;
\r
574 /* Clear the interrupt. */
\r
575 EMAC->IntClear = ulStatus;
\r
577 if( ulStatus & INT_RX_DONE )
\r
579 /* Ensure the uIP task is not blocked as data has arrived. */
\r
580 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
\r
583 if( ulStatus & INT_TX_DONE )
\r
585 if( usSendLen > 0 )
\r
587 /* Send the data again, using the second descriptor. As there are
\r
588 only two descriptors the index is set back to 0. */
\r
589 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
\r
590 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
\r
591 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
\r
593 /* This is the second Tx so set usSendLen to 0 to indicate that the
\r
594 Tx descriptors will be free again. */
\r
599 /* The Tx buffer is no longer required. */
\r
600 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
601 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
\r
605 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
\r