2 ******************************************************************************
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3 * @file system_stm32f0xx.c
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4 * @author MCD Application Team
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6 * @date 27-January-2012
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7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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8 * This file contains the system clock configuration for STM32F0xx devices,
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9 * and is generated by the clock configuration tool
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10 * STM32F0xx_Clock_Configuration_VX.Y.Z.xls
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12 * 1. This file provides two functions and one global variable to be called from
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14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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15 * and Divider factors, AHB/APBx prescalers and Flash settings),
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16 * depending on the configuration made in the clock xls tool.
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17 * This function is called at startup just after reset and
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18 * before branch to main program. This call is made inside
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19 * the "startup_stm32f0xx.s" file.
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21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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22 * by the user application to setup the SysTick
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23 * timer or configure other parameters.
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25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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26 * be called whenever the core clock is changed
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27 * during program execution.
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29 * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
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30 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
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31 * configure the system clock before to branch to main program.
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33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
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34 * function will do nothing and HSI still used as system clock source. User can
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35 * add some code to deal with this issue inside the SetSysClock() function.
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37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
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38 * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
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39 * through PLL, and you are using different crystal you have to adapt the HSE
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40 * value to your own configuration.
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42 * 5. This file configures the system clock as follows:
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43 *=============================================================================
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44 * System Clock Configuration
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45 *=============================================================================
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46 * System Clock source | PLL(HSE)
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47 *-----------------------------------------------------------------------------
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48 * SYSCLK | 48000000 Hz
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49 *-----------------------------------------------------------------------------
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50 * HCLK | 48000000 Hz
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51 *-----------------------------------------------------------------------------
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53 *-----------------------------------------------------------------------------
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54 * APB1 Prescaler | 1
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55 *-----------------------------------------------------------------------------
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56 * APB2 Prescaler | 1
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57 *-----------------------------------------------------------------------------
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58 * HSE Frequency | 8000000 Hz
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59 *-----------------------------------------------------------------------------
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61 *-----------------------------------------------------------------------------
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63 *-----------------------------------------------------------------------------
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64 * Flash Latency | 1 WS
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65 *-----------------------------------------------------------------------------
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66 *=============================================================================
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67 ******************************************************************************
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70 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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71 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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72 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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73 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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74 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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75 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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77 * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
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78 * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
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80 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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81 ******************************************************************************
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84 /** @addtogroup CMSIS
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88 /** @addtogroup stm32f0xx_system
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92 /** @addtogroup STM32F0xx_System_Private_Includes
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96 #include "stm32f0xx.h"
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102 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
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110 /** @addtogroup STM32F0xx_System_Private_Defines
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117 /** @addtogroup STM32F0xx_System_Private_Macros
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125 /** @addtogroup STM32F0xx_System_Private_Variables
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128 uint32_t SystemCoreClock = 48000000;
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129 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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135 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
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139 static void SetSysClock(void);
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145 /** @addtogroup STM32F0xx_System_Private_Functions
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150 * @brief Setup the microcontroller system.
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151 * Initialize the Embedded Flash Interface, the PLL and update the
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152 * SystemCoreClock variable.
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156 void SystemInit (void)
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158 /* Set HSION bit */
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159 RCC->CR |= (uint32_t)0x00000001;
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161 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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162 RCC->CFGR &= (uint32_t)0xF8FFB80C;
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164 /* Reset HSEON, CSSON and PLLON bits */
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165 RCC->CR &= (uint32_t)0xFEF6FFFF;
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167 /* Reset HSEBYP bit */
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168 RCC->CR &= (uint32_t)0xFFFBFFFF;
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170 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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171 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
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173 /* Reset PREDIV1[3:0] bits */
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174 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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176 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
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177 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
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179 /* Reset HSI14 bit */
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180 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
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182 /* Disable all interrupts */
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183 RCC->CIR = 0x00000000;
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185 /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
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190 * @brief Update SystemCoreClock according to Clock Register Values
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191 * @note - The system frequency computed by this function is not the real
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192 * frequency in the chip. It is calculated based on the predefined
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193 * constant and the selected clock source:
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195 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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197 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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199 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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200 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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202 * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
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203 * 8 MHz) but the real value may vary depending on the variations
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204 * in voltage and temperature.
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206 * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
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207 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
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208 * frequency of the crystal used. Otherwise, this function may
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209 * have wrong result.
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211 * - The result of this function could be not correct when using fractional
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212 * value for HSE crystal.
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216 void SystemCoreClockUpdate (void)
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218 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
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220 /* Get SYSCLK source -------------------------------------------------------*/
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221 tmp = RCC->CFGR & RCC_CFGR_SWS;
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225 case 0x00: /* HSI used as system clock */
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226 SystemCoreClock = HSI_VALUE;
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228 case 0x04: /* HSE used as system clock */
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229 SystemCoreClock = HSE_VALUE;
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231 case 0x08: /* PLL used as system clock */
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232 /* Get PLL clock source and multiplication factor ----------------------*/
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233 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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234 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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235 pllmull = ( pllmull >> 18) + 2;
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237 if (pllsource == 0x00)
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239 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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240 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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244 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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245 /* HSE oscillator clock selected as PREDIV1 clock entry */
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246 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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249 default: /* HSI used as system clock */
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250 SystemCoreClock = HSI_VALUE;
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253 /* Compute HCLK clock frequency ----------------*/
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254 /* Get HCLK prescaler */
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255 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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256 /* HCLK clock frequency */
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257 SystemCoreClock >>= tmp;
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261 * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
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263 * @note This function should be called only once the RCC clock configuration
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264 * is reset to the default reset state (done in SystemInit() function).
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268 static void SetSysClock(void)
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270 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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272 /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
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274 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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276 /* Wait till HSE is ready and if Time out is reached exit */
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279 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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281 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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283 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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285 HSEStatus = (uint32_t)0x01;
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289 HSEStatus = (uint32_t)0x00;
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292 if (HSEStatus == (uint32_t)0x01)
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294 /* Enable Prefetch Buffer */
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295 FLASH->ACR |= FLASH_ACR_PRFTBE;
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296 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY;
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298 /* HCLK = SYSCLK */
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299 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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302 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
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304 /* PLL configuration: = HSE * 6 = 48 MHz */
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305 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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306 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
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309 RCC->CR |= RCC_CR_PLLON;
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311 /* Wait till PLL is ready */
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312 while((RCC->CR & RCC_CR_PLLRDY) == 0)
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316 /* Select PLL as system clock source */
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317 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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318 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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320 /* Wait till PLL is used as system clock source */
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321 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
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326 { /* If HSE fails to start-up, the application will have wrong clock
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327 configuration. User can add here some code to deal with this error */
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343 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
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