1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
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5 * @date 19. July 2011
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8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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22 ******************************************************************************/
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23 #if defined ( __ICCARM__ )
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24 #pragma system_include /* treat file as system include file for MISRA check */
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31 #ifndef __CORE_CM0_H_GENERIC
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32 #define __CORE_CM0_H_GENERIC
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35 /** \mainpage CMSIS Cortex-M0
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37 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
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40 - Cortex-M Core Register Definitions
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41 - Cortex-M functions
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42 - Cortex-M instructions
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44 The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
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45 access to the Cortex-M Core
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48 /** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
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49 CMSIS violates following MISRA-C2004 Rules:
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51 - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
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52 Function definitions in header files are used to allow 'inlining'.
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54 - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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55 Unions are used for effective representation of core registers.
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57 - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
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58 Function-like macros are used to allow more efficient code.
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63 /*******************************************************************************
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65 ******************************************************************************/
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66 /** \defgroup CMSIS_core_definitions CMSIS Core Definitions
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67 This file defines all structures and symbols for CMSIS core:
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68 - CMSIS version number
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70 - Cortex-M core Revision Number
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74 /* CMSIS CM0 definitions */
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75 #define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
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76 #define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
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77 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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79 #define __CORTEX_M (0x00) /*!< Cortex core */
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82 #if defined ( __CC_ARM )
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83 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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86 #elif defined ( __ICCARM__ )
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87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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90 #elif defined ( __GNUC__ )
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91 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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92 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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94 #elif defined ( __TASKING__ )
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95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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100 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
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101 #define __FPU_USED 0
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103 #if defined ( __CC_ARM )
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104 #if defined __TARGET_FPU_VFP
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105 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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107 #elif defined ( __ICCARM__ )
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108 #if defined __ARMVFP__
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109 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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112 #elif defined ( __GNUC__ )
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113 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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114 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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117 #elif defined ( __TASKING__ )
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118 /* add preprocessor checks */
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121 #include <stdint.h> /*!< standard types definitions */
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122 #include "core_cmInstr.h" /*!< Core Instruction Access */
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123 #include "core_cmFunc.h" /*!< Core Function Access */
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125 #endif /* __CORE_CM0_H_GENERIC */
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127 #ifndef __CMSIS_GENERIC
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129 #ifndef __CORE_CM0_H_DEPENDANT
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130 #define __CORE_CM0_H_DEPENDANT
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132 /* check device defines and use defaults */
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133 #if defined __CHECK_DEVICE_DEFINES
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135 #define __CM0_REV 0x0000
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136 #warning "__CM0_REV not defined in device header file; using default!"
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139 #ifndef __NVIC_PRIO_BITS
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140 #define __NVIC_PRIO_BITS 2
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141 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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144 #ifndef __Vendor_SysTickConfig
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145 #define __Vendor_SysTickConfig 0
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146 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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150 /* IO definitions (access restrictions to peripheral registers) */
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152 #define __I volatile /*!< defines 'read only' permissions */
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154 #define __I volatile const /*!< defines 'read only' permissions */
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156 #define __O volatile /*!< defines 'write only' permissions */
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157 #define __IO volatile /*!< defines 'read / write' permissions */
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159 /*@} end of group CMSIS_core_definitions */
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163 /*******************************************************************************
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164 * Register Abstraction
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165 ******************************************************************************/
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166 /** \defgroup CMSIS_core_register CMSIS Core Register
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167 Core Register contain:
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169 - Core NVIC Register
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170 - Core SCB Register
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171 - Core SysTick Register
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174 /** \ingroup CMSIS_core_register
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175 \defgroup CMSIS_CORE CMSIS Core
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176 Type definitions for the Cortex-M Core Registers
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180 /** \brief Union type to access the Application Program Status Register (APSR).
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186 #if (__CORTEX_M != 0x04)
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187 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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189 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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190 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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191 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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193 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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194 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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195 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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196 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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197 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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198 } b; /*!< Structure used for bit access */
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199 uint32_t w; /*!< Type used for word access */
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203 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
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209 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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210 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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211 } b; /*!< Structure used for bit access */
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212 uint32_t w; /*!< Type used for word access */
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216 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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223 #if (__CORTEX_M != 0x04)
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224 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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226 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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227 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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228 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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230 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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231 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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232 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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233 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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234 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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235 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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236 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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237 } b; /*!< Structure used for bit access */
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238 uint32_t w; /*!< Type used for word access */
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242 /** \brief Union type to access the Control Registers (CONTROL).
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248 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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249 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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250 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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251 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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252 } b; /*!< Structure used for bit access */
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253 uint32_t w; /*!< Type used for word access */
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256 /*@} end of group CMSIS_CORE */
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259 /** \ingroup CMSIS_core_register
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260 \defgroup CMSIS_NVIC CMSIS NVIC
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261 Type definitions for the Cortex-M NVIC Registers
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265 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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269 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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270 uint32_t RESERVED0[31];
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271 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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272 uint32_t RSERVED1[31];
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273 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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274 uint32_t RESERVED2[31];
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275 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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276 uint32_t RESERVED3[31];
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277 uint32_t RESERVED4[64];
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278 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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281 /*@} end of group CMSIS_NVIC */
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284 /** \ingroup CMSIS_core_register
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285 \defgroup CMSIS_SCB CMSIS SCB
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286 Type definitions for the Cortex-M System Control Block Registers
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290 /** \brief Structure type to access the System Control Block (SCB).
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294 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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295 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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296 uint32_t RESERVED0;
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297 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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298 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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299 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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300 uint32_t RESERVED1;
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301 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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302 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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305 /* SCB CPUID Register Definitions */
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306 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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307 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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309 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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310 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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312 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
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313 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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315 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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316 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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318 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
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319 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
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321 /* SCB Interrupt Control State Register Definitions */
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322 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
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323 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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325 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
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326 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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328 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
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329 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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331 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
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332 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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334 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
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335 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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337 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
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338 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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340 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
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341 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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343 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
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344 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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346 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
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347 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
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349 /* SCB Application Interrupt and Reset Control Register Definitions */
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350 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
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351 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
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353 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
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354 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
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356 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
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357 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
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359 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
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360 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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362 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
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363 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
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365 /* SCB System Control Register Definitions */
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366 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
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367 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
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369 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
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370 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
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372 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
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373 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
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375 /* SCB Configuration Control Register Definitions */
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376 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
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377 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
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379 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
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380 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
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382 /* SCB System Handler Control and State Register Definitions */
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383 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
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384 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
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386 /*@} end of group CMSIS_SCB */
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389 /** \ingroup CMSIS_core_register
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390 \defgroup CMSIS_SysTick CMSIS SysTick
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391 Type definitions for the Cortex-M System Timer Registers
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395 /** \brief Structure type to access the System Timer (SysTick).
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399 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
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400 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
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401 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
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402 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
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405 /* SysTick Control / Status Register Definitions */
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406 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
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407 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
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409 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
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410 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
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412 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
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413 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
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415 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
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416 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
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418 /* SysTick Reload Register Definitions */
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419 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
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420 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
\r
422 /* SysTick Current Register Definitions */
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423 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
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424 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
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426 /* SysTick Calibration Register Definitions */
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427 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
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428 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
430 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
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431 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
433 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
434 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
\r
436 /*@} end of group CMSIS_SysTick */
\r
439 /** \ingroup CMSIS_core_register
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440 \defgroup CMSIS_CoreDebug CMSIS Core Debug
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441 Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
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442 and not via processor. Therefore they are not covered by the Cortex-M0 header file.
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445 /*@} end of group CMSIS_CoreDebug */
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448 /** \ingroup CMSIS_core_register
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452 /* Memory mapping of Cortex-M0 Hardware */
\r
453 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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454 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
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455 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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456 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
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457 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
459 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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460 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
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461 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
468 /*******************************************************************************
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469 * Hardware Abstraction Layer
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470 ******************************************************************************/
\r
471 /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
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472 Core Function Interface contains:
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473 - Core NVIC Functions
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474 - Core SysTick Functions
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475 - Core Register Access Functions
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480 /* ########################## NVIC functions #################################### */
\r
481 /** \ingroup CMSIS_Core_FunctionInterface
\r
482 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
\r
486 /* Interrupt Priorities are WORD accessible only under ARMv6M */
\r
487 /* The following MACROS handle generation of the register offset and byte masks */
\r
488 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
\r
489 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
\r
490 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
\r
493 /** \brief Enable External Interrupt
\r
495 This function enables a device specific interrupt in the NVIC interrupt controller.
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496 The interrupt number cannot be a negative value.
\r
498 \param [in] IRQn Number of the external interrupt to enable
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500 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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502 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
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506 /** \brief Disable External Interrupt
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508 This function disables a device specific interrupt in the NVIC interrupt controller.
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509 The interrupt number cannot be a negative value.
\r
511 \param [in] IRQn Number of the external interrupt to disable
\r
513 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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515 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
\r
519 /** \brief Get Pending Interrupt
\r
521 This function reads the pending register in the NVIC and returns the pending bit
\r
522 for the specified interrupt.
\r
524 \param [in] IRQn Number of the interrupt for get pending
\r
525 \return 0 Interrupt status is not pending
\r
526 \return 1 Interrupt status is pending
\r
528 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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530 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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534 /** \brief Set Pending Interrupt
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536 This function sets the pending bit for the specified interrupt.
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537 The interrupt number cannot be a negative value.
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539 \param [in] IRQn Number of the interrupt for set pending
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541 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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543 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
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547 /** \brief Clear Pending Interrupt
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549 This function clears the pending bit for the specified interrupt.
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550 The interrupt number cannot be a negative value.
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552 \param [in] IRQn Number of the interrupt for clear pending
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554 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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556 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
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560 /** \brief Set Interrupt Priority
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562 This function sets the priority for the specified interrupt. The interrupt
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563 number can be positive to specify an external (device specific)
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564 interrupt, or negative to specify an internal (core) interrupt.
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566 Note: The priority cannot be set for every core interrupt.
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568 \param [in] IRQn Number of the interrupt for set priority
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569 \param [in] priority Priority to set
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571 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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574 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
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575 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
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577 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
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578 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
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582 /** \brief Get Interrupt Priority
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584 This function reads the priority for the specified interrupt. The interrupt
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585 number can be positive to specify an external (device specific)
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586 interrupt, or negative to specify an internal (core) interrupt.
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588 The returned priority value is automatically aligned to the implemented
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589 priority bits of the microcontroller.
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591 \param [in] IRQn Number of the interrupt for get priority
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592 \return Interrupt Priority
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594 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
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598 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
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600 return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
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604 /** \brief System Reset
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606 This function initiate a system reset request to reset the MCU.
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608 static __INLINE void NVIC_SystemReset(void)
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610 __DSB(); /* Ensure all outstanding memory accesses included
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611 buffered write are completed before reset */
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612 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
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613 SCB_AIRCR_SYSRESETREQ_Msk);
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614 __DSB(); /* Ensure completion of memory access */
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615 while(1); /* wait until reset */
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618 /*@} end of CMSIS_Core_NVICFunctions */
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622 /* ################################## SysTick function ############################################ */
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623 /** \ingroup CMSIS_Core_FunctionInterface
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624 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
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628 #if (__Vendor_SysTickConfig == 0)
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630 /** \brief System Tick Configuration
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632 This function initialises the system tick timer and its interrupt and start the system tick timer.
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633 Counter is in free running mode to generate periodical interrupts.
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635 \param [in] ticks Number of ticks between two interrupts
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636 \return 0 Function succeeded
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637 \return 1 Function failed
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639 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
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641 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
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643 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
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644 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
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645 SysTick->VAL = 0; /* Load the SysTick Counter Value */
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646 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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647 SysTick_CTRL_TICKINT_Msk |
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648 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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649 return (0); /* Function successful */
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654 /*@} end of CMSIS_Core_SysTickFunctions */
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659 #endif /* __CORE_CM0_H_DEPENDANT */
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661 #endif /* __CMSIS_GENERIC */
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