2 *****************************************************************************
\r
4 ** File : startup_XMC4500.s
\r
6 ** Abstract : This assembler file contains interrupt vector and
\r
7 ** startup code for Infineon XMC4500.
\r
9 ** Functions : Reset_Handler
\r
12 ** Target : ARM Cortex-M4
\r
14 ** Environment : Atollic TrueSTUDIO(R)
\r
16 ** Distribution: The file is distributed
\93as is,
\94 without any warranty
\r
19 ** (c)Copyright Atollic AB.
\r
20 ** This file may be distributed and used with the FreeRTOS example project
\r
21 ** for Atollic TrueSTUDIO only.
\r
23 *****************************************************************************
\r
27 **===========================================================================
\r
29 **===========================================================================
\r
30 ** Date Modification
\r
31 ** 2011-12-30 First issue.
\r
32 **===========================================================================
\r
36 **===========================================================================
\r
38 **===========================================================================
\r
45 .global g_pfnVectors
\r
46 .global Default_Handler
\r
48 /* Linker script definitions */
\r
49 /* start address for the initialization values of the .data section */
\r
51 /* start address for the .data section */
\r
53 /* end address for the .data section */
\r
55 /* start address for the .bss section */
\r
57 /* end address for the .bss section */
\r
60 .equ PREF_PCON, 0x58004000
\r
61 .equ SCU_GCU_PEEN, 0x5000413C
\r
62 .equ SCU_GCU_PEFLAG, 0x50004150
\r
65 **===========================================================================
\r
66 ** Program - Reset_Handler
\r
67 ** Abstract: This code gets called after a reset event.
\r
68 ** 1. Copy .data section from ROM to RAM
\r
69 ** 2. Clear .bss section (Zero init)
\r
70 ** 3. Call system initialzation routine
\r
71 ** 4. Run static constructors
\r
73 ** 6. Loop forever if returning from main
\r
74 **===========================================================================
\r
76 .section .text.Reset_Handler
\r
78 .type Reset_Handler, %function
\r
81 /* Remap vector table - added by RB. */
\r
82 ldr r0, =g_pfnVectors
\r
83 ldr r1, =0xE000ED08 /* VTOR register */
\r
86 /* Disable Branch prediction */
\r
89 orr r1,r1,#0x00010000
\r
92 /* Clear existing parity errors if any */
\r
93 ldr r0,=SCU_GCU_PEFLAG
\r
97 /* Disable parity */
\r
98 ldr r0,=SCU_GCU_PEEN
\r
102 /* Enable un-aligned memory access - added by RB. */
\r
103 ldr r1, =0xE000ED14
\r
109 ldr sp, =_estack /* set stack pointer */
\r
111 /* 1. copy .data section (Copy from ROM to RAM) */
\r
130 /* 2. Clear .bss section (Zero init) */
\r
140 /* 3. Call system initialzation routine */
\r
143 /* 4. Run static constructors */
\r
144 bl __libc_init_array
\r
146 /* 5. Enter main */
\r
149 /* 6. Loop forever if returning from main */
\r
154 .size Reset_Handler, .-Reset_Handler
\r
157 **===========================================================================
\r
158 ** Program - Default_Handler
\r
159 ** Abstract: This code gets called when the processor receives an
\r
160 ** unexpected interrupt.
\r
161 **===========================================================================
\r
163 .section .text.Default_Handler,"ax",%progbits
\r
167 .size Default_Handler, .-Default_Handler
\r
170 **===========================================================================
\r
171 ** Reset, Exception, and Interrupt vectors
\r
172 **===========================================================================
\r
174 .section .isr_vector,"a",%progbits
\r
175 .type g_pfnVectors, %object
\r
176 .size g_pfnVectors, .-g_pfnVectors
\r
180 /* Processor exception vectors */
\r
182 .word Reset_Handler
\r
184 .word HardFault_Handler
\r
185 .word MemManage_Handler
\r
186 .word BusFault_Handler
\r
187 .word UsageFault_Handler
\r
193 .word DebugMon_Handler
\r
195 .word PendSV_Handler
\r
196 .word SysTick_Handler
\r
198 /* Interrupt Handlers for XMC4500 Peripherals */
\r
199 .word SCU_0_IRQHandler /* Handler name for SR SCU_0 */
\r
200 .word ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
\r
201 .word ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
\r
202 .word ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
\r
203 .word ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
\r
204 .word ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
\r
205 .word ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
\r
206 .word ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
\r
207 .word ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
\r
208 .word 0 /* Not Available */
\r
209 .word 0 /* Not Available */
\r
210 .word 0 /* Not Available */
\r
211 .word PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
\r
212 .word 0 /* Not Available */
\r
213 .word VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
\r
214 .word VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
\r
215 .word VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
\r
216 .word VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
\r
217 .word VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
\r
218 .word VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
\r
219 .word VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
\r
220 .word VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
\r
221 .word VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
\r
222 .word VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
\r
223 .word VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
\r
224 .word VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
\r
225 .word VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */
\r
226 .word VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */
\r
227 .word VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */
\r
228 .word VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */
\r
229 .word VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */
\r
230 .word VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */
\r
231 .word VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */
\r
232 .word VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */
\r
233 .word DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */
\r
234 .word DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */
\r
235 .word DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */
\r
236 .word DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */
\r
237 .word DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */
\r
238 .word DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */
\r
239 .word DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */
\r
240 .word DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */
\r
241 .word DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
\r
242 .word DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */
\r
243 .word CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
\r
244 .word CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
\r
245 .word CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
\r
246 .word CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
\r
247 .word CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
\r
248 .word CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
\r
249 .word CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
\r
250 .word CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
\r
251 .word CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */
\r
252 .word CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */
\r
253 .word CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */
\r
254 .word CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */
\r
255 .word CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */
\r
256 .word CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */
\r
257 .word CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */
\r
258 .word CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */
\r
259 .word CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
\r
260 .word CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
\r
261 .word CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
\r
262 .word CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
\r
263 .word CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */
\r
264 .word CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */
\r
265 .word CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */
\r
266 .word CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */
\r
267 .word POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
\r
268 .word POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
\r
269 .word POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */
\r
270 .word POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */
\r
271 .word 0 /* Not Available */
\r
272 .word 0 /* Not Available */
\r
273 .word 0 /* Not Available */
\r
274 .word 0 /* Not Available */
\r
275 .word CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
\r
276 .word CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
\r
277 .word CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
\r
278 .word CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
\r
279 .word CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
\r
280 .word CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
\r
281 .word CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
\r
282 .word CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
\r
283 .word USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
\r
284 .word USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
\r
285 .word USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
\r
286 .word USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
\r
287 .word USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
\r
288 .word USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
\r
289 .word USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
\r
290 .word USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
\r
291 .word USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
\r
292 .word USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
\r
293 .word USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
\r
294 .word USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
\r
295 .word USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */
\r
296 .word USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */
\r
297 .word USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */
\r
298 .word USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */
\r
299 .word USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */
\r
300 .word USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */
\r
301 .word LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
\r
302 .word 0 /* Not Available */
\r
303 .word FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
\r
304 .word GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
\r
305 .word SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */
\r
306 .word USB0_0_IRQHandler /* Handler name for SR USB0_0 */
\r
307 .word ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */
\r
308 .word 0 /* Not Available */
\r
309 .word GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */
\r
310 .word 0 /* Not Available */
\r
314 **===========================================================================
\r
315 ** Provide weak aliases for each Exception handler to the Default_Handler.
\r
316 **===========================================================================
\r
319 .thumb_set NMI_Handler,Default_Handler
\r
321 .weak HardFault_Handler
\r
322 .thumb_set HardFault_Handler,Default_Handler
\r
324 .weak MemManage_Handler
\r
325 .thumb_set MemManage_Handler,Default_Handler
\r
327 .weak BusFault_Handler
\r
328 .thumb_set BusFault_Handler,Default_Handler
\r
330 .weak UsageFault_Handler
\r
331 .thumb_set UsageFault_Handler,Default_Handler
\r
334 .thumb_set SVC_Handler,Default_Handler
\r
336 .weak DebugMon_Handler
\r
337 .thumb_set DebugMon_Handler,Default_Handler
\r
339 .weak PendSV_Handler
\r
340 .thumb_set PendSV_Handler,Default_Handler
\r
342 .weak SysTick_Handler
\r
343 .thumb_set SysTick_Handler,Default_Handler
\r
345 .weak SCU_0_IRQHandler
\r
346 .thumb_set SCU_0_IRQHandler,Default_Handler
\r
348 .weak ERU0_0_IRQHandler
\r
349 .thumb_set ERU0_0_IRQHandler,Default_Handler
\r
351 .weak ERU0_1_IRQHandler
\r
352 .thumb_set ERU0_1_IRQHandler,Default_Handler
\r
354 .weak ERU0_2_IRQHandler
\r
355 .thumb_set ERU0_2_IRQHandler,Default_Handler
\r
357 .weak ERU0_3_IRQHandler
\r
358 .thumb_set ERU0_3_IRQHandler,Default_Handler
\r
360 .weak ERU1_0_IRQHandler
\r
361 .thumb_set ERU1_0_IRQHandler,Default_Handler
\r
363 .weak ERU1_1_IRQHandler
\r
364 .thumb_set ERU1_1_IRQHandler,Default_Handler
\r
366 .weak ERU1_2_IRQHandler
\r
367 .thumb_set ERU1_2_IRQHandler,Default_Handler
\r
369 .weak ERU1_3_IRQHandler
\r
370 .thumb_set ERU1_3_IRQHandler,Default_Handler
\r
372 .weak PMU0_0_IRQHandler
\r
373 .thumb_set PMU0_0_IRQHandler,Default_Handler
\r
375 .weak VADC0_C0_0_IRQHandler
\r
376 .thumb_set VADC0_C0_0_IRQHandler,Default_Handler
\r
378 .weak VADC0_C0_1_IRQHandler
\r
379 .thumb_set VADC0_C0_1_IRQHandler,Default_Handler
\r
381 .weak VADC0_C0_2_IRQHandler
\r
382 .thumb_set VADC0_C0_2_IRQHandler,Default_Handler
\r
384 .weak VADC0_C0_3_IRQHandler
\r
385 .thumb_set VADC0_C0_3_IRQHandler,Default_Handler
\r
387 .weak VADC0_G0_0_IRQHandler
\r
388 .thumb_set VADC0_G0_0_IRQHandler,Default_Handler
\r
390 .weak VADC0_G0_1_IRQHandler
\r
391 .thumb_set VADC0_G0_1_IRQHandler,Default_Handler
\r
393 .weak VADC0_G0_2_IRQHandler
\r
394 .thumb_set VADC0_G0_2_IRQHandler,Default_Handler
\r
396 .weak VADC0_G0_3_IRQHandler
\r
397 .thumb_set VADC0_G0_3_IRQHandler,Default_Handler
\r
399 .weak VADC0_G1_0_IRQHandler
\r
400 .thumb_set VADC0_G1_0_IRQHandler,Default_Handler
\r
402 .weak VADC0_G1_1_IRQHandler
\r
403 .thumb_set VADC0_G1_1_IRQHandler,Default_Handler
\r
405 .weak VADC0_G1_2_IRQHandler
\r
406 .thumb_set VADC0_G1_2_IRQHandler,Default_Handler
\r
408 .weak VADC0_G1_3_IRQHandler
\r
409 .thumb_set VADC0_G1_3_IRQHandler,Default_Handler
\r
411 .weak VADC0_G2_0_IRQHandler
\r
412 .thumb_set VADC0_G2_0_IRQHandler,Default_Handler
\r
414 .weak VADC0_G2_1_IRQHandler
\r
415 .thumb_set VADC0_G2_1_IRQHandler,Default_Handler
\r
417 .weak VADC0_G2_2_IRQHandler
\r
418 .thumb_set VADC0_G2_2_IRQHandler,Default_Handler
\r
420 .weak VADC0_G2_3_IRQHandler
\r
421 .thumb_set VADC0_G2_3_IRQHandler,Default_Handler
\r
423 .weak VADC0_G3_0_IRQHandler
\r
424 .thumb_set VADC0_G3_0_IRQHandler,Default_Handler
\r
426 .weak VADC0_G3_1_IRQHandler
\r
427 .thumb_set VADC0_G3_1_IRQHandler,Default_Handler
\r
429 .weak VADC0_G3_2_IRQHandler
\r
430 .thumb_set VADC0_G3_2_IRQHandler,Default_Handler
\r
432 .weak VADC0_G3_3_IRQHandler
\r
433 .thumb_set VADC0_G3_3_IRQHandler,Default_Handler
\r
435 .weak DSD0_0_IRQHandler
\r
436 .thumb_set DSD0_0_IRQHandler,Default_Handler
\r
438 .weak DSD0_1_IRQHandler
\r
439 .thumb_set DSD0_1_IRQHandler,Default_Handler
\r
441 .weak DSD0_2_IRQHandler
\r
442 .thumb_set DSD0_2_IRQHandler,Default_Handler
\r
444 .weak DSD0_3_IRQHandler
\r
445 .thumb_set DSD0_3_IRQHandler,Default_Handler
\r
447 .weak DSD0_4_IRQHandler
\r
448 .thumb_set DSD0_4_IRQHandler,Default_Handler
\r
450 .weak DSD0_5_IRQHandler
\r
451 .thumb_set DSD0_5_IRQHandler,Default_Handler
\r
453 .weak DSD0_6_IRQHandler
\r
454 .thumb_set DSD0_6_IRQHandler,Default_Handler
\r
456 .weak DSD0_7_IRQHandler
\r
457 .thumb_set DSD0_7_IRQHandler,Default_Handler
\r
459 .weak DAC0_0_IRQHandler
\r
460 .thumb_set DAC0_0_IRQHandler,Default_Handler
\r
462 .weak DAC0_1_IRQHandler
\r
463 .thumb_set DAC0_1_IRQHandler,Default_Handler
\r
465 .weak CCU40_0_IRQHandler
\r
466 .thumb_set CCU40_0_IRQHandler,Default_Handler
\r
468 .weak CCU40_1_IRQHandler
\r
469 .thumb_set CCU40_1_IRQHandler,Default_Handler
\r
471 .weak CCU40_2_IRQHandler
\r
472 .thumb_set CCU40_2_IRQHandler,Default_Handler
\r
474 .weak CCU40_3_IRQHandler
\r
475 .thumb_set CCU40_3_IRQHandler,Default_Handler
\r
477 .weak CCU41_0_IRQHandler
\r
478 .thumb_set CCU41_0_IRQHandler,Default_Handler
\r
480 .weak CCU41_1_IRQHandler
\r
481 .thumb_set CCU41_1_IRQHandler,Default_Handler
\r
483 .weak CCU41_2_IRQHandler
\r
484 .thumb_set CCU41_2_IRQHandler,Default_Handler
\r
486 .weak CCU41_3_IRQHandler
\r
487 .thumb_set CCU41_3_IRQHandler,Default_Handler
\r
489 .weak CCU42_0_IRQHandler
\r
490 .thumb_set CCU42_0_IRQHandler,Default_Handler
\r
492 .weak CCU42_1_IRQHandler
\r
493 .thumb_set CCU42_1_IRQHandler,Default_Handler
\r
495 .weak CCU42_2_IRQHandler
\r
496 .thumb_set CCU42_2_IRQHandler,Default_Handler
\r
498 .weak CCU42_3_IRQHandler
\r
499 .thumb_set CCU42_3_IRQHandler,Default_Handler
\r
501 .weak CCU43_0_IRQHandler
\r
502 .thumb_set CCU43_0_IRQHandler,Default_Handler
\r
504 .weak CCU43_1_IRQHandler
\r
505 .thumb_set CCU43_1_IRQHandler,Default_Handler
\r
507 .weak CCU43_2_IRQHandler
\r
508 .thumb_set CCU43_2_IRQHandler,Default_Handler
\r
510 .weak CCU43_3_IRQHandler
\r
511 .thumb_set CCU43_3_IRQHandler,Default_Handler
\r
513 .weak CCU80_0_IRQHandler
\r
514 .thumb_set CCU80_0_IRQHandler,Default_Handler
\r
516 .weak CCU80_1_IRQHandler
\r
517 .thumb_set CCU80_1_IRQHandler,Default_Handler
\r
519 .weak CCU80_2_IRQHandler
\r
520 .thumb_set CCU80_2_IRQHandler,Default_Handler
\r
522 .weak CCU80_3_IRQHandler
\r
523 .thumb_set CCU80_3_IRQHandler,Default_Handler
\r
525 .weak CCU81_0_IRQHandler
\r
526 .thumb_set CCU81_0_IRQHandler,Default_Handler
\r
528 .weak CCU81_1_IRQHandler
\r
529 .thumb_set CCU81_1_IRQHandler,Default_Handler
\r
531 .weak CCU81_2_IRQHandler
\r
532 .thumb_set CCU81_2_IRQHandler,Default_Handler
\r
534 .weak CCU81_3_IRQHandler
\r
535 .thumb_set CCU81_3_IRQHandler,Default_Handler
\r
537 .weak POSIF0_0_IRQHandler
\r
538 .thumb_set POSIF0_0_IRQHandler,Default_Handler
\r
540 .weak POSIF0_1_IRQHandler
\r
541 .thumb_set POSIF0_1_IRQHandler,Default_Handler
\r
543 .weak POSIF1_0_IRQHandler
\r
544 .thumb_set POSIF1_0_IRQHandler,Default_Handler
\r
546 .weak POSIF1_1_IRQHandler
\r
547 .thumb_set POSIF1_1_IRQHandler,Default_Handler
\r
549 .weak CAN0_0_IRQHandler
\r
550 .thumb_set CAN0_0_IRQHandler,Default_Handler
\r
552 .weak CAN0_1_IRQHandler
\r
553 .thumb_set CAN0_1_IRQHandler,Default_Handler
\r
555 .weak CAN0_2_IRQHandler
\r
556 .thumb_set CAN0_2_IRQHandler,Default_Handler
\r
558 .weak CAN0_3_IRQHandler
\r
559 .thumb_set CAN0_3_IRQHandler,Default_Handler
\r
561 .weak CAN0_4_IRQHandler
\r
562 .thumb_set CAN0_4_IRQHandler,Default_Handler
\r
564 .weak CAN0_5_IRQHandler
\r
565 .thumb_set CAN0_5_IRQHandler,Default_Handler
\r
567 .weak CAN0_6_IRQHandler
\r
568 .thumb_set CAN0_6_IRQHandler,Default_Handler
\r
570 .weak CAN0_7_IRQHandler
\r
571 .thumb_set CAN0_7_IRQHandler,Default_Handler
\r
573 .weak USIC0_0_IRQHandler
\r
574 .thumb_set USIC0_0_IRQHandler,Default_Handler
\r
576 .weak USIC0_1_IRQHandler
\r
577 .thumb_set USIC0_1_IRQHandler,Default_Handler
\r
579 .weak USIC0_2_IRQHandler
\r
580 .thumb_set USIC0_2_IRQHandler,Default_Handler
\r
582 .weak USIC0_3_IRQHandler
\r
583 .thumb_set USIC0_3_IRQHandler,Default_Handler
\r
585 .weak USIC0_4_IRQHandler
\r
586 .thumb_set USIC0_4_IRQHandler,Default_Handler
\r
588 .weak USIC0_5_IRQHandler
\r
589 .thumb_set USIC0_5_IRQHandler,Default_Handler
\r
591 .weak USIC1_0_IRQHandler
\r
592 .thumb_set USIC1_0_IRQHandler,Default_Handler
\r
594 .weak USIC1_1_IRQHandler
\r
595 .thumb_set USIC1_1_IRQHandler,Default_Handler
\r
597 .weak USIC1_2_IRQHandler
\r
598 .thumb_set USIC1_2_IRQHandler,Default_Handler
\r
600 .weak USIC1_3_IRQHandler
\r
601 .thumb_set USIC1_3_IRQHandler,Default_Handler
\r
603 .weak USIC1_4_IRQHandler
\r
604 .thumb_set USIC1_4_IRQHandler,Default_Handler
\r
606 .weak USIC1_5_IRQHandler
\r
607 .thumb_set USIC1_5_IRQHandler,Default_Handler
\r
609 .weak USIC2_0_IRQHandler
\r
610 .thumb_set USIC2_0_IRQHandler,Default_Handler
\r
612 .weak USIC2_1_IRQHandler
\r
613 .thumb_set USIC2_1_IRQHandler,Default_Handler
\r
615 .weak USIC2_2_IRQHandler
\r
616 .thumb_set USIC2_2_IRQHandler,Default_Handler
\r
618 .weak USIC2_3_IRQHandler
\r
619 .thumb_set USIC2_3_IRQHandler,Default_Handler
\r
621 .weak USIC2_4_IRQHandler
\r
622 .thumb_set USIC2_4_IRQHandler,Default_Handler
\r
624 .weak USIC2_5_IRQHandler
\r
625 .thumb_set USIC2_5_IRQHandler,Default_Handler
\r
627 .weak LEDTS0_0_IRQHandler
\r
628 .thumb_set LEDTS0_0_IRQHandler,Default_Handler
\r
630 .weak FCE0_0_IRQHandler
\r
631 .thumb_set FCE0_0_IRQHandler,Default_Handler
\r
633 .weak GPDMA0_0_IRQHandler
\r
634 .thumb_set GPDMA0_0_IRQHandler,Default_Handler
\r
636 .weak SDMMC0_0_IRQHandler
\r
637 .thumb_set SDMMC0_0_IRQHandler,Default_Handler
\r
639 .weak USB0_0_IRQHandler
\r
640 .thumb_set USB0_0_IRQHandler,Default_Handler
\r
642 .weak ETH0_0_IRQHandler
\r
643 .thumb_set ETH0_0_IRQHandler,Default_Handler
\r
645 .weak GPDMA1_0_IRQHandler
\r
646 .thumb_set GPDMA1_0_IRQHandler,Default_Handler
\r