git.sur5r.net Git - freertos/blob - Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_PeripheralLibraryFiles/lpc43xx_cgu.h

   1 /**********************************************************************\r
   2 * $Id$          lpc43xx_cgu.h                   2011-06-02\r
   3 *//**\r
   4 * @file         llpc43xx_cgu.h\r
   5 * @brief        Contains all macro definitions and function prototypes\r
   6 *                       support for Clock Generation and Clock Control firmware\r
   7 *                       library on lpc43xx\r
   8 * @version      1.0\r
   9 * @date         02. June. 2011\r
  10 * @author       NXP MCU SW Application Team\r
  11 *\r
  12 * Copyright(C) 2011, NXP Semiconductor\r
  13 * All rights reserved.\r
  14 *\r
  15 ***********************************************************************\r
  16 * Software that is described herein is for illustrative purposes only\r
  17 * which provides customers with programming information regarding the\r
  18 * products. This software is supplied "AS IS" without any warranties.\r
  19 * NXP Semiconductors assumes no responsibility or liability for the\r
  20 * use of the software, conveys no license or title under any patent,\r
  21 * copyright, or mask work right to the product. NXP Semiconductors\r
  22 * reserves the right to make changes in the software without\r
  23 * notification. NXP Semiconductors also make no representation or\r
  24 * warranty that such application will be suitable for the specified\r
  25 * use without further testing or modification.\r
  26 **********************************************************************/\r
  27 \r
  28 /* Peripheral group ----------------------------------------------------------- */\r
  29 /** @defgroup CGU CGU (Clock Generation Unit)\r
  30  * @ingroup LPC4300CMSIS_FwLib_Drivers\r
  31  * @{\r
  32  */\r
  33 \r
  34 #ifndef lpc43xx_CGU_H_\r
  35 #define lpc43xx_CGU_H_\r
  36 \r
  37 /* Includes ------------------------------------------------------------------- */\r
  38 #include "lpc43xx.h"\r
  39 #include "lpc_types.h"\r
  40 \r
  41 #ifdef __cplusplus\r
  42 extern "C"\r
  43 {\r
  44 #endif\r
  45 \r
  46 /* Private Macros -------------------------------------------------------------- */\r
  47 /** @defgroup CGU_Private_Macros CGU Private Macros\r
  48  * @{\r
  49  */\r
  50 \r
  51 /** Branch clocks from CGU_BASE_SAFE */\r
  52 #define CGU_ENTITY_NONE                         CGU_ENTITY_NUM\r
  53 \r
  54 /** Check bit at specific position is clear or not */\r
  55 #define ISBITCLR(x,bit)                         ((x&(1<<bit))^(1<<bit))\r
  56 /** Check bit at specific position is set or not */\r
  57 #define ISBITSET(x,bit)                         (x&(1<<bit))\r
  58 /** Set mask */\r
  59 #define ISMASKSET(x,mask)                       (x&mask)\r
  60 \r
  61 /** CGU number of clock source */\r
  62 #define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)\r
  63 \r
  64 /*********************************************************************//**\r
  65  * Macro defines for CGU control mask bit definitions\r
  66  **********************************************************************/\r
  67 /** CGU control enable mask bit */\r
  68 #define CGU_CTRL_EN_MASK                        1\r
  69 /** CGU control clock-source mask bit */\r
  70 #define CGU_CTRL_SRC_MASK                       (0xF<<24)\r
  71 /** CGU control auto block mask bit */\r
  72 #define CGU_CTRL_AUTOBLOCK_MASK         (1<<11)\r
  73 \r
  74 /*********************************************************************//**\r
  75  * Macro defines for CGU PLL1 mask bit definitions\r
  76  **********************************************************************/\r
  77 /** CGU PLL1 feedback select mask bit */\r
  78 #define CGU_PLL1_FBSEL_MASK                     (1<<6)\r
  79 /** CGU PLL1 Input clock bypass control mask bit */\r
  80 #define CGU_PLL1_BYPASS_MASK            (1<<1)\r
  81 /** CGU PLL1 direct CCO output mask bit */\r
  82 #define CGU_PLL1_DIRECT_MASK            (1<<7)\r
  83 \r
  84 /**\r
  85  * @}\r
  86  */\r
  87 \r
  88 /* Public Types --------------------------------------------------------------- */\r
  89 /** @defgroup CGU_Public_Types CGU Public Types\r
  90  * @{\r
  91  */\r
  92 \r
  93 /*********************************************************************//**\r
  94  * @brief CGU enumeration\r
  95  **********************************************************************/\r
  96 /*\r
  97  * @brief       CGU clock source enumerate definition
  98  */\r
  99 typedef enum {\r
 100         /* Clock Source */\r
 101         CGU_CLKSRC_32KHZ_OSC = 0,                                       /**< 32KHz oscillator clock source      */\r
 102         CGU_CLKSRC_IRC,                                                         /**< IRC 12 Mhz clock source            */\r
 103         CGU_CLKSRC_ENET_RX_CLK,                                         /**< Ethernet receive clock source      */\r
 104         CGU_CLKSRC_ENET_TX_CLK,                                         /**< Ethernet transmit clock source */\r
 105         CGU_CLKSRC_GP_CLKIN,                                            /**< General purpose clock source       */\r
 106         CGU_CLKSRC_TCK,                                                         /**< TCK clock source                           */\r
 107         CGU_CLKSRC_XTAL_OSC,                                            /**< Crystal oscillator clock source*/\r
 108         CGU_CLKSRC_PLL0,                                                        /**< PLL0 (USB0) clock source           */\r
 109         CGU_CLKSRC_PLL0_AUDIO,\r
 110         CGU_CLKSRC_PLL1,                                                        /**< PLL1 clock source                          */\r
 111         CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,         /**< IDIVA clock source                         */\r
 112         CGU_CLKSRC_IDIVB,                                                       /**< IDIVB clock source                         */\r
 113         CGU_CLKSRC_IDIVC,                                                       /**< IDIVC clock source                         */\r
 114         CGU_CLKSRC_IDIVD,                                                       /**< IDIVD clock source                         */\r
 115         CGU_CLKSRC_IDIVE,                                                       /**< IDIVE clock source                         */\r
 116 \r
 117         /* Base */\r
 118         CGU_BASE_SAFE,                                                          /**< Base save clock (always on) for WDT */\r
 119         CGU_BASE_USB0,                                                          /**< USB0 base clock                            */\r
 120         CGU_BASE_USB1 = CGU_BASE_USB0 + 2,                      /**< USB1 base clock                            */\r
 121         CGU_BASE_M3,                                                            /**< ARM Cortex-M3 Core base clock      */\r
 122         CGU_BASE_SPIFI,                                                         /**< SPIFI base clock                           */\r
 123         //CGU_BASE_SPI,\r
 124         CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2,           /**< Ethernet PHY Rx base clock         */\r
 125         CGU_BASE_PHY_TX,                                                        /**< Ethernet PHY Tx base clock         */\r
 126         CGU_BASE_APB1,                                                          /**< APB peripheral block #1 base clock */\r
 127         CGU_BASE_APB3,                                                          /**< APB peripheral block #3 base clock */\r
 128         CGU_BASE_LCD,                                                           /**< LCD base clock                                     */\r
 129         CGU_BASE_ENET_CSR,\r
 130         CGU_BASE_SDIO,                                                          /**< SDIO base clock                            */\r
 131         CGU_BASE_SSP0,                                                          /**< SSP0 base clock                            */\r
 132         CGU_BASE_SSP1,                                                          /**< SSP1 base clock                            */\r
 133         CGU_BASE_UART0,                                                         /**< UART0 base clock                           */\r
 134         CGU_BASE_UART1,                                                         /**< UART1 base clock                           */\r
 135         CGU_BASE_UART2,                                                         /**< UART2 base clock                           */\r
 136         CGU_BASE_UART3,                                                         /**< UART3 base clock                           */\r
 137         CGU_BASE_CLKOUT,                                                        /**< CLKOUT base clock                          */\r
 138         CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,\r
 139         CGU_BASE_OUT0,\r
 140         CGU_BASE_OUT1,\r
 141         CGU_ENTITY_NUM                                                          /**< Number or clock source entity      */\r
 142 } CGU_ENTITY_T;\r
 143 \r
 144 /*\r
 145  * @brief       CGU PPL0 mode enumerate definition\r
 146  */\r
 147 typedef enum {\r
 148         CGU_PLL0_MODE_1d = 0,\r
 149         CGU_PLL0_MODE_1c,\r
 150         CGU_PLL0_MODE_1b,\r
 151         CGU_PLL0_MODE_1a\r
 152 }CGU_PLL0_MODE;\r
 153 \r
 154 /*\r
 155  * @brief       CGU peripheral enumerate definition\r
 156  */\r
 157 typedef enum {\r
 158         CGU_PERIPHERAL_ADC0 = 0,                                        /**< ADC0               */\r
 159         CGU_PERIPHERAL_ADC1,                                            /**< ADC1               */\r
 160         CGU_PERIPHERAL_AES,                                                     /**< AES                */\r
 161 //      CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
 162         CGU_PERIPHERAL_APB1_BUS,                                        /**< APB1 bus                   */\r
 163         CGU_PERIPHERAL_APB3_BUS,                                        /**< APB3 bus                   */\r
 164         CGU_PERIPHERAL_CAN,                                                     /**< CAN                                */\r
 165         CGU_PERIPHERAL_CREG,                                            /**< CREG                               */\r
 166         CGU_PERIPHERAL_DAC,                                                     /**< DAC                                */\r
 167         CGU_PERIPHERAL_DMA,                                                     /**< DMA                                */\r
 168         CGU_PERIPHERAL_EMC,                                                     /**< EMC                                */\r
 169         CGU_PERIPHERAL_ETHERNET,                                        /**< Ethernet                   */\r
 170         CGU_PERIPHERAL_ETHERNET_TX, //HIDE                      /**< Ethernet transmit  */\r
 171         CGU_PERIPHERAL_GPIO,                                            /**< GPIO                               */\r
 172         CGU_PERIPHERAL_I2C0,                                            /**< I2C0                               */\r
 173         CGU_PERIPHERAL_I2C1,                                            /**< I2C1                               */\r
 174         CGU_PERIPHERAL_I2S,                                                     /**< I2S                                */\r
 175         CGU_PERIPHERAL_LCD,                                                     /**< LCD                                */\r
 176         CGU_PERIPHERAL_M3CORE,                                          /**< ARM Cortex-M3 Core */\r
 177         CGU_PERIPHERAL_M3_BUS,                                          /**< ARM Cortex-M3 Bus  */\r
 178         CGU_PERIPHERAL_MOTOCON,                                         /**< Motor Control              */\r
 179         CGU_PERIPHERAL_QEI,                                                     /**< QEI                                */\r
 180         CGU_PERIPHERAL_RITIMER,                                         /**< RIT Timer                  */\r
 181         CGU_PERIPHERAL_SCT,                                                     /**< SCT                                */\r
 182         CGU_PERIPHERAL_SCU,                                                     /**< SCU                                */\r
 183         CGU_PERIPHERAL_SDIO,                                            /**< SDIO                               */\r
 184         CGU_PERIPHERAL_SPIFI,                                           /**< SPIFI                              */\r
 185         CGU_PERIPHERAL_SSP0,                                            /**< SSP0                               */\r
 186         CGU_PERIPHERAL_SSP1,                                            /**< SSP1                               */\r
 187         CGU_PERIPHERAL_TIMER0,                                          /**< TIMER 0                    */\r
 188         CGU_PERIPHERAL_TIMER1,                                          /**< TIMER 1                    */\r
 189         CGU_PERIPHERAL_TIMER2,                                          /**< TIMER 2                    */\r
 190         CGU_PERIPHERAL_TIMER3,                                          /**< TIMER 3                    */\r
 191         CGU_PERIPHERAL_UART0,                                           /**< UART0                              */\r
 192         CGU_PERIPHERAL_UART1,                                           /**< UART1                              */\r
 193         CGU_PERIPHERAL_UART2,                                           /**< UART2                              */\r
 194         CGU_PERIPHERAL_UART3,                                           /**< UART3                              */\r
 195         CGU_PERIPHERAL_USB0,                                            /**< USB0                               */\r
 196         CGU_PERIPHERAL_USB1,                                            /**< USB1                               */\r
 197         CGU_PERIPHERAL_WWDT,                                            /**< WWDT                               */\r
 198         CGU_PERIPHERAL_NUM\r
 199 } CGU_PERIPHERAL_T;\r
 200 \r
 201 /**\r
 202  *  @brief      CGU error status enumerate definition\r
 203  */\r
 204 typedef enum {\r
 205         CGU_ERROR_SUCCESS = 0,\r
 206         CGU_ERROR_CONNECT_TOGETHER,\r
 207         CGU_ERROR_INVALID_ENTITY,\r
 208         CGU_ERROR_INVALID_CLOCK_SOURCE,\r
 209         CGU_ERROR_INVALID_PARAM,\r
 210         CGU_ERROR_FREQ_OUTOF_RANGE\r
 211 } CGU_ERROR;\r
 212 \r
 213 /********************************************************************//**\r
 214 * @brief CGU structure definitions\r
 215 **********************************************************************/\r
 216 /*\r
 217  * @brief       CGU peripheral clock structure
 218  */\r
 219 typedef struct {\r
 220         uint8_t RegBaseEntity;                                          /**< Base register address              */\r
 221         uint16_t RegBranchOffset;                                       /**< Branch register offset             */\r
 222         uint8_t PerBaseEntity;                                          /**< Base peripheral address    */\r
 223         uint16_t PerBranchOffset;                                       /**< Base peripheral offset             */\r
 224         uint8_t next;                                                           /**< Pointer to next structure  */\r
 225 } CGU_PERIPHERAL_S;\r
 226 \r
 227 /**\r
 228  * @}\r
 229  */\r
 230 \r
 231 \r
 232 /* Public Functions ----------------------------------------------------------- */\r
 233 /** @defgroup CGU_Public_Functions CGU Public Functions\r
 234  * @{\r
 235  */\r
 236 \r
 237 /** Clock generate initialize/de-initialize */\r
 238 uint32_t        CGU_Init(void);\r
 239 uint32_t        CGU_DeInit(void);\r
 240 \r
 241 /** Clock Generator and Clock Control */\r
 242 uint32_t        CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);\r
 243 uint32_t        CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);\r
 244 \r
 245 /** Clock Source and Base Clock operation */\r
 246 uint32_t        CGU_SetXTALOSC(uint32_t ClockFrequency);\r
 247 uint32_t        CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);\r
 248 uint32_t        CGU_SetPLL0(void);\r
 249 uint32_t        CGU_SetPLL1(uint32_t mult);\r
 250 uint32_t        CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);\r
 251 uint32_t        CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);\r
 252 uint32_t        CGU_GetBaseStatus(CGU_ENTITY_T Base);\r
 253 void            CGU_UpdateClock(void);\r
 254 uint32_t        CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);\r
 255 \r
 256 /**\r
 257  * @}\r
 258  */\r
 259 \r
 260 \r
 261 #ifdef __cplusplus\r
 262 }\r
 263 #endif\r
 264 \r
 265 #endif /* lpc43xx_CGU_H_ */\r
 266 \r
 267 /**\r
 268  * @}\r
 269  */\r
 270 \r
 271 /* --------------------------------- End Of File ------------------------------ */\r