1 /**********************************************************************
2 * $Id: Hitex_Fast_Startup.c 8763 2011-12-08 00:45:50Z nxp21346 $ lpc43xx_emc.c 2011-12-07
5 * @brief Contains all functions support for Clock Generation and Control
6 * firmware library on lpc43xx
8 * @date 07. December. 2011
9 * @author NXP MCU SW Application Team
11 * Copyright(C) 2011, NXP Semiconductor
12 * All rights reserved.
14 ***********************************************************************
15 * Software that is described herein is for illustrative purposes only
16 * which provides customers with programming information regarding the
17 * products. This software is supplied "AS IS" without any warranties.
18 * NXP Semiconductors assumes no responsibility or liability for the
19 * use of the software, conveys no license or title under any patent,
20 * copyright, or mask work right to the product. NXP Semiconductors
21 * reserves the right to make changes in the software without
22 * notification. NXP Semiconductors also make no representation or
23 * warranty that such application will be suitable for the specified
24 * use without further testing or modification.
25 **********************************************************************/
28 #include "lpc43xx_cgu.h"
29 #include "lpc43xx_emc.h"
31 void WaitMinUS( volatile uint32_t us, uint32_t SystemClock )
33 us *= (SystemClock / 1000000UL) / 3;
37 void WaitMinMS( uint32_t ms, uint32_t SystemClock )
39 WaitMinUS( ( ms * 1000 ), SystemClock );
42 /* hardware-control routine used by spifi_rom_api.c */
43 void pullMISO(int high) {
44 /* undocumented bit 7 included as 1, Aug 2 2011 */
45 LPC_SCU->SFSP3_6 = high == 0 ? 0xDB /* pull down */
46 : high == 1 ? 0xC3 /* pull up */
50 void Hitex_CGU_Init(void)
54 MemoryPinInit(); // Make sure EMC is in high-speed pin mode
56 /* Set the XTAL oscillator frequency to 12MHz*/
57 CGU_SetXTALOSC(__CRYSTAL);
58 CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
59 CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
61 /* Set PL160M 12*1 = 12 MHz */
62 CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
64 CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
66 /* Run SPIFI from PL160M, /2 */
67 CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
68 CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
69 CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
70 CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
73 LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
74 LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
75 LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
77 /* Set PL160M @ 12*9=108 MHz */
80 /* Run base M3 clock from PL160M, no division */
81 CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
83 WaitMinMS(10, 108000000UL);
85 /* Change the clock to 204 MHz */
86 /* Set PL160M @ 12*15=180 MHz */
89 WaitMinMS(10, 180000000UL);
95 vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
96 LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
98 LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
99 LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */