1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
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5 * @date 06. December 2010
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8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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22 ******************************************************************************/
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23 #if defined ( __ICCARM__ )
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24 #pragma system_include /* treat file as system include file for MISRA check */
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31 #ifndef __CORE_CM4_H_GENERIC
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32 #define __CORE_CM4_H_GENERIC
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35 /** \mainpage CMSIS Cortex-M4
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37 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
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40 - Cortex-M Core Register Definitions
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41 - Cortex-M functions
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42 - Cortex-M instructions
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43 - Cortex-M SIMD instructions
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45 The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
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46 access to the Cortex-M Core
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49 /** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
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50 List of Lint messages which will be suppressed and not shown:
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53 Note: To re-enable a Message, insert a space before 'lint' *
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58 /*******************************************************************************
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60 ******************************************************************************/
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61 /** \defgroup CMSIS_core_definitions CMSIS Core Definitions
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62 This file defines all structures and symbols for CMSIS core:
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63 - CMSIS version number
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65 - Cortex-M core Revision Number
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69 /* CMSIS CM4 definitions */
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70 #define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
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71 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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72 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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74 #define __CORTEX_M (0x04) /*!< Cortex core */
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76 #ifndef __NVIC_PRIO_BITS
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77 #define __NVIC_PRIO_BITS 3 /*!< standard definition for NVIC Priority Bits */
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80 #if defined ( __CC_ARM )
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81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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84 #elif defined ( __ICCARM__ )
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85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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88 #elif defined ( __GNUC__ )
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89 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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90 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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92 #elif defined ( __TASKING__ )
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93 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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94 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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98 #include <stdint.h> /*!< standard types definitions */
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99 #include "core_cmInstr.h" /*!< Core Instruction Access */
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100 #include "core_cmFunc.h" /*!< Core Function Access */
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101 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
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103 #endif /* __CORE_CM4_H_GENERIC */
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106 #ifndef __CMSIS_GENERIC
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108 #ifndef __CORE_CM4_H_DEPENDANT
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109 #define __CORE_CM4_H_DEPENDANT
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111 /* IO definitions (access restrictions to peripheral registers) */
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113 #define __I volatile /*!< defines 'read only' permissions */
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115 #define __I volatile const /*!< defines 'read only' permissions */
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117 #define __O volatile /*!< defines 'write only' permissions */
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118 #define __IO volatile /*!< defines 'read / write' permissions */
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120 /*@} end of group CMSIS_core_definitions */
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124 /*******************************************************************************
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125 * Register Abstraction
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126 ******************************************************************************/
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127 /** \defgroup CMSIS_core_register CMSIS Core Register
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128 Core Register contain:
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130 - Core NVIC Register
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131 - Core SCB Register
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132 - Core SysTick Register
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133 - Core Debug Register
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134 - Core MPU Register
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135 - Core FPU Register
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138 /** \ingroup CMSIS_core_register
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139 \defgroup CMSIS_CORE CMSIS Core
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140 Type definitions for the Cortex-M Core Registers
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144 /** \brief Union type to access the Application Program Status Register (APSR).
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150 #if (__CORTEX_M != 0x04)
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151 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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153 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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154 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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155 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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157 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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158 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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159 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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160 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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161 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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162 } b; /*!< Structure used for bit access */
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163 uint32_t w; /*!< Type used for word access */
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167 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
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173 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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174 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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175 } b; /*!< Structure used for bit access */
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176 uint32_t w; /*!< Type used for word access */
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180 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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186 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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187 #if (__CORTEX_M != 0x04)
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188 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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190 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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191 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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192 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
\r
194 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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195 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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196 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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197 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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198 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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199 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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200 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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201 } b; /*!< Structure used for bit access */
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202 uint32_t w; /*!< Type used for word access */
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206 /** \brief Union type to access the Control Registers (CONTROL).
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212 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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213 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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214 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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215 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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216 } b; /*!< Structure used for bit access */
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217 uint32_t w; /*!< Type used for word access */
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220 /*@} end of group CMSIS_CORE */
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223 /** \ingroup CMSIS_core_register
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224 \defgroup CMSIS_NVIC CMSIS NVIC
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225 Type definitions for the Cortex-M NVIC Registers
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229 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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233 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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234 uint32_t RESERVED0[24];
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235 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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236 uint32_t RSERVED1[24];
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237 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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238 uint32_t RESERVED2[24];
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239 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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240 uint32_t RESERVED3[24];
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241 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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242 uint32_t RESERVED4[56];
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243 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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244 uint32_t RESERVED5[644];
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245 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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248 /*@} end of group CMSIS_NVIC */
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251 /** \ingroup CMSIS_core_register
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252 \defgroup CMSIS_SCB CMSIS SCB
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253 Type definitions for the Cortex-M System Control Block Registers
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257 /** \brief Structure type to access the System Control Block (SCB).
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261 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
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262 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
\r
263 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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264 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
\r
265 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
\r
266 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
\r
267 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
\r
268 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
\r
269 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
\r
270 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */
\r
271 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
\r
272 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */
\r
273 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */
\r
274 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
\r
275 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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276 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
\r
277 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
\r
278 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
\r
279 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
\r
280 uint32_t RESERVED0[5];
\r
281 __IO uint32_t CPACR; /*!< Offset: 0x880 (R/W) Coprocessor access register */
\r
284 /* SCB CPUID Register Definitions */
\r
285 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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286 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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288 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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289 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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291 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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292 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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294 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
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295 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
\r
297 /* SCB Interrupt Control State Register Definitions */
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298 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
\r
299 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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301 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
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302 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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304 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
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305 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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307 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
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308 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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310 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
\r
311 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
\r
313 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
\r
314 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
\r
316 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
\r
317 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
\r
319 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
\r
320 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
\r
322 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
\r
323 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
\r
325 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
\r
326 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
\r
328 /* SCB Interrupt Control State Register Definitions */
\r
329 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
\r
330 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
\r
332 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
\r
333 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
\r
335 /* SCB Application Interrupt and Reset Control Register Definitions */
\r
336 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
\r
337 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
\r
339 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
\r
340 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
\r
342 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
\r
343 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
345 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
\r
346 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
\r
348 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
\r
349 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
351 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
352 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
354 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
\r
355 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
\r
357 /* SCB System Control Register Definitions */
\r
358 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
\r
359 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
361 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
\r
362 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
364 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
\r
365 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
367 /* SCB Configuration Control Register Definitions */
\r
368 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
\r
369 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
371 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
\r
372 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
\r
374 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
\r
375 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
\r
377 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
\r
378 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
380 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
\r
381 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
\r
383 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
\r
384 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
\r
386 /* SCB System Handler Control and State Register Definitions */
\r
387 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
\r
388 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
\r
390 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
\r
391 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
\r
393 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
\r
394 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
\r
396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
\r
397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
399 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
\r
400 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
\r
402 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
\r
403 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
\r
405 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
\r
406 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
\r
408 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
\r
409 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
411 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
\r
412 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
414 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
\r
415 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
\r
417 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
\r
418 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
420 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
\r
421 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
\r
423 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
\r
424 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
\r
426 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
\r
427 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
\r
429 /* SCB Configurable Fault Status Registers Definitions */
\r
430 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
\r
431 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
\r
433 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
\r
434 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
\r
436 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
\r
437 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
\r
439 /* SCB Hard Fault Status Registers Definitions */
\r
440 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
\r
441 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
\r
443 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
\r
444 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
\r
446 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
\r
447 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
\r
449 /* SCB Debug Fault Status Register Definitions */
\r
450 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
\r
451 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
\r
453 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
\r
454 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
\r
456 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
\r
457 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
\r
459 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
\r
460 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
\r
462 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
\r
463 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
\r
465 /*@} end of group CMSIS_SCB */
\r
468 /** \ingroup CMSIS_core_register
\r
469 \defgroup CMSIS_SysTick CMSIS SysTick
\r
470 Type definitions for the Cortex-M System Timer Registers
\r
474 /** \brief Structure type to access the System Timer (SysTick).
\r
478 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
479 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
480 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
481 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
484 /* SysTick Control / Status Register Definitions */
\r
485 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
\r
486 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
488 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
\r
489 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
491 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
\r
492 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
494 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
\r
495 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
\r
497 /* SysTick Reload Register Definitions */
\r
498 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
\r
499 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
\r
501 /* SysTick Current Register Definitions */
\r
502 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
\r
503 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
\r
505 /* SysTick Calibration Register Definitions */
\r
506 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
\r
507 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
509 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
\r
510 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
512 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
513 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
\r
515 /*@} end of group CMSIS_SysTick */
\r
518 /** \ingroup CMSIS_core_register
\r
519 \defgroup CMSIS_ITM CMSIS ITM
\r
520 Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
\r
524 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
\r
530 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
\r
531 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
\r
532 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
\r
533 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
\r
534 uint32_t RESERVED0[864];
\r
535 __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */
\r
536 uint32_t RESERVED1[15];
\r
537 __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */
\r
538 uint32_t RESERVED2[15];
\r
539 __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */
\r
540 uint32_t RESERVED3[29];
\r
541 __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */
\r
542 __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */
\r
543 __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */
\r
544 uint32_t RESERVED4[43];
\r
545 __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */
\r
546 __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */
\r
547 uint32_t RESERVED5[6];
\r
548 __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */
\r
549 __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */
\r
550 __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */
\r
551 __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */
\r
552 __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */
\r
553 __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */
\r
554 __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */
\r
555 __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */
\r
556 __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */
\r
557 __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */
\r
558 __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */
\r
559 __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */
\r
562 /* ITM Trace Privilege Register Definitions */
\r
563 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
\r
564 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
\r
566 /* ITM Trace Control Register Definitions */
\r
567 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
\r
568 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
\r
570 #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
\r
571 #define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
\r
573 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
\r
574 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
\r
576 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
\r
577 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
\r
579 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
\r
580 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
\r
582 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
\r
583 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
\r
585 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
\r
586 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
\r
588 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
\r
589 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
\r
591 /* ITM Integration Write Register Definitions */
\r
592 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
\r
593 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
\r
595 /* ITM Integration Read Register Definitions */
\r
596 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
\r
597 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
\r
599 /* ITM Integration Mode Control Register Definitions */
\r
600 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
\r
601 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
\r
603 /* ITM Lock Status Register Definitions */
\r
604 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
\r
605 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
\r
607 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
\r
608 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
\r
610 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
\r
611 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
\r
613 /*@}*/ /* end of group CMSIS_ITM */
\r
616 /** \ingroup CMSIS_core_register
\r
617 \defgroup CMSIS_InterruptType CMSIS Interrupt Type
\r
618 Type definitions for the Cortex-M Interrupt Type Register
\r
622 /** \brief Structure type to access the Interrupt Type Register.
\r
626 uint32_t RESERVED0;
\r
627 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */
\r
628 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
\r
629 } InterruptType_Type;
\r
631 /* Interrupt Controller Type Register Definitions */
\r
632 #define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
\r
633 #define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
\r
635 /* Auxiliary Control Register Definitions */
\r
636 #define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
\r
637 #define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
\r
639 #define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
\r
640 #define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
\r
642 #define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
\r
643 #define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
\r
645 /*@}*/ /* end of group CMSIS_InterruptType */
\r
648 #if (__MPU_PRESENT == 1)
\r
649 /** \ingroup CMSIS_core_register
\r
650 \defgroup CMSIS_MPU CMSIS MPU
\r
651 Type definitions for the Cortex-M Memory Protection Unit (MPU)
\r
655 /** \brief Structure type to access the Memory Protection Unit (MPU).
\r
659 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
660 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
661 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
\r
662 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
663 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
\r
664 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
\r
665 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
\r
666 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
\r
667 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
\r
668 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
\r
669 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
\r
672 /* MPU Type Register */
\r
673 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
\r
674 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
676 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
\r
677 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
679 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
\r
680 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
\r
682 /* MPU Control Register */
\r
683 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
\r
684 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
686 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
\r
687 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
689 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
\r
690 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
\r
692 /* MPU Region Number Register */
\r
693 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
\r
694 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
\r
696 /* MPU Region Base Address Register */
\r
697 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
\r
698 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
\r
700 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
\r
701 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
\r
703 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
\r
704 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
\r
706 /* MPU Region Attribute and Size Register */
\r
707 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
\r
708 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
\r
710 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
\r
711 #define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
\r
713 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
\r
714 #define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
\r
716 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
\r
717 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
\r
719 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
\r
720 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
\r
722 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
\r
723 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
\r
725 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
\r
726 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
\r
728 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
\r
729 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
\r
731 #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
\r
732 #define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
\r
734 /*@} end of group CMSIS_MPU */
\r
738 #if (__FPU_PRESENT == 1)
\r
739 /** \ingroup CMSIS_core_register
\r
740 \defgroup CMSIS_FPU CMSIS FPU
\r
741 Type definitions for the Cortex-M Floating Point Unit (FPU)
\r
745 /** \brief Structure type to access the Floating Point Unit (FPU).
\r
749 uint32_t RESERVED0[1];
\r
750 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating point context control register */
\r
751 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating point context address register */
\r
752 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating point default status control register */
\r
753 __IO uint32_t MVFR0; /*!< Offset: 0x010 (R/W) Media and VFP feature register 0 */
\r
754 __IO uint32_t MVFR1; /*!< Offset: 0x014 (R/W) Media and VFP feature register 1 */
\r
757 /*@} end of group CMSIS_FPU */
\r
761 /** \ingroup CMSIS_core_register
\r
762 \defgroup CMSIS_CoreDebug CMSIS Core Debug
\r
763 Type definitions for the Cortex-M Core Debug Registers
\r
767 /** \brief Structure type to access the Core Debug Register (CoreDebug).
\r
771 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
772 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
773 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
774 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
777 /* Debug Halting Control and Status Register */
\r
778 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
\r
779 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
781 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
782 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
784 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
785 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
787 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
788 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
790 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
791 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
793 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
\r
794 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
796 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
797 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
799 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
\r
800 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
\r
802 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
803 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
805 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
\r
806 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
808 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
\r
809 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
811 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
812 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
814 /* Debug Core Register Selector Register */
\r
815 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
\r
816 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
818 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
\r
819 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
821 /* Debug Exception and Monitor Control Register */
\r
822 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
\r
823 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
\r
825 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
\r
826 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
\r
828 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
\r
829 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
\r
831 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
\r
832 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
\r
834 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
\r
835 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
\r
837 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
838 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
840 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
\r
841 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
\r
843 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
\r
844 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
\r
846 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
\r
847 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
\r
849 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
\r
850 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
\r
852 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
\r
853 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
\r
855 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
\r
856 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
\r
858 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
859 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
861 /*@} end of group CMSIS_CoreDebug */
\r
864 /** \ingroup CMSIS_core_register
\r
868 /* Memory mapping of Cortex-M4 Hardware */
\r
869 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
870 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
\r
871 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
872 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
873 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
874 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
876 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
\r
877 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
\r
878 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
\r
879 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
\r
880 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
\r
881 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
\r
883 #if (__MPU_PRESENT == 1)
\r
884 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
885 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
\r
888 #if (__FPU_PRESENT == 1)
\r
889 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
\r
890 #define FPU ((FPU_Type*) FPU_BASE) /*!< Floating Point Unit */
\r
897 /*******************************************************************************
\r
898 * Hardware Abstraction Layer
\r
899 ******************************************************************************/
\r
900 /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
\r
901 Core Function Interface contains:
\r
902 - Core NVIC Functions
\r
903 - Core SysTick Functions
\r
904 - Core Debug Functions
\r
905 - Core Register Access Functions
\r
910 /* ########################## NVIC functions #################################### */
\r
911 /** \ingroup CMSIS_Core_FunctionInterface
\r
912 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
\r
916 /** \brief Set Priority Grouping
\r
918 This function sets the priority grouping field using the required unlock sequence.
\r
919 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
\r
920 Only values from 0..7 are used.
\r
921 In case of a conflict between priority grouping and available
\r
922 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
924 \param [in] PriorityGroup Priority grouping field
\r
926 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\r
928 uint32_t reg_value;
\r
929 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
931 reg_value = SCB->AIRCR; /* read old register configuration */
\r
932 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
\r
933 reg_value = (reg_value |
\r
934 (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
\r
935 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
\r
936 SCB->AIRCR = reg_value;
\r
940 /** \brief Get Priority Grouping
\r
942 This function gets the priority grouping from NVIC Interrupt Controller.
\r
943 Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
\r
945 \return Priority grouping field
\r
947 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
\r
949 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
\r
953 /** \brief Enable External Interrupt
\r
955 This function enables a device specific interupt in the NVIC interrupt controller.
\r
956 The interrupt number cannot be a negative value.
\r
958 \param [in] IRQn Number of the external interrupt to enable
\r
960 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\r
962 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
\r
966 /** \brief Disable External Interrupt
\r
968 This function disables a device specific interupt in the NVIC interrupt controller.
\r
969 The interrupt number cannot be a negative value.
\r
971 \param [in] IRQn Number of the external interrupt to disable
\r
973 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\r
975 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
\r
979 /** \brief Get Pending Interrupt
\r
981 This function reads the pending register in the NVIC and returns the pending bit
\r
982 for the specified interrupt.
\r
984 \param [in] IRQn Number of the interrupt for get pending
\r
985 \return 0 Interrupt status is not pending
\r
986 \return 1 Interrupt status is pending
\r
988 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
990 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
\r
994 /** \brief Set Pending Interrupt
\r
996 This function sets the pending bit for the specified interrupt.
\r
997 The interrupt number cannot be a negative value.
\r
999 \param [in] IRQn Number of the interrupt for set pending
\r
1001 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1003 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
\r
1007 /** \brief Clear Pending Interrupt
\r
1009 This function clears the pending bit for the specified interrupt.
\r
1010 The interrupt number cannot be a negative value.
\r
1012 \param [in] IRQn Number of the interrupt for clear pending
\r
1014 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1016 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
\r
1020 /** \brief Get Active Interrupt
\r
1022 This function reads the active register in NVIC and returns the active bit.
\r
1023 \param [in] IRQn Number of the interrupt for get active
\r
1024 \return 0 Interrupt status is not active
\r
1025 \return 1 Interrupt status is active
\r
1027 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\r
1029 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
\r
1033 /** \brief Set Interrupt Priority
\r
1035 This function sets the priority for the specified interrupt. The interrupt
\r
1036 number can be positive to specify an external (device specific)
\r
1037 interrupt, or negative to specify an internal (core) interrupt.
\r
1039 Note: The priority cannot be set for every core interrupt.
\r
1041 \param [in] IRQn Number of the interrupt for set priority
\r
1042 \param [in] priority Priority to set
\r
1044 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1047 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
\r
1049 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
\r
1053 /** \brief Get Interrupt Priority
\r
1055 This function reads the priority for the specified interrupt. The interrupt
\r
1056 number can be positive to specify an external (device specific)
\r
1057 interrupt, or negative to specify an internal (core) interrupt.
\r
1059 The returned priority value is automatically aligned to the implemented
\r
1060 priority bits of the microcontroller.
\r
1062 \param [in] IRQn Number of the interrupt for get priority
\r
1063 \return Interrupt Priority
\r
1065 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\r
1069 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
\r
1071 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
\r
1075 /** \brief Encode Priority
\r
1077 This function encodes the priority for an interrupt with the given priority group,
\r
1078 preemptive priority value and sub priority value.
\r
1079 In case of a conflict between priority grouping and available
\r
1080 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
\r
1082 The returned priority value can be used for NVIC_SetPriority(...) function
\r
1084 \param [in] PriorityGroup Used priority group
\r
1085 \param [in] PreemptPriority Preemptive priority value (starting from 0)
\r
1086 \param [in] SubPriority Sub priority value (starting from 0)
\r
1087 \return Encoded priority for the interrupt
\r
1089 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
1091 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1092 uint32_t PreemptPriorityBits;
\r
1093 uint32_t SubPriorityBits;
\r
1095 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
\r
1096 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
\r
1099 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
\r
1100 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
\r
1105 /** \brief Decode Priority
\r
1107 This function decodes an interrupt priority value with the given priority group to
\r
1108 preemptive priority value and sub priority value.
\r
1109 In case of a conflict between priority grouping and available
\r
1110 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
\r
1112 The priority value can be retrieved with NVIC_GetPriority(...) function
\r
1114 \param [in] Priority Priority value
\r
1115 \param [in] PriorityGroup Used priority group
\r
1116 \param [out] pPreemptPriority Preemptive priority value (starting from 0)
\r
1117 \param [out] pSubPriority Sub priority value (starting from 0)
\r
1119 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
\r
1121 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1122 uint32_t PreemptPriorityBits;
\r
1123 uint32_t SubPriorityBits;
\r
1125 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
\r
1126 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
\r
1128 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
\r
1129 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
\r
1133 /** \brief System Reset
\r
1135 This function initiate a system reset request to reset the MCU.
\r
1137 static __INLINE void NVIC_SystemReset(void)
\r
1139 __DSB(); /* Ensure all outstanding memory accesses included
\r
1140 buffered write are completed before reset */
\r
1141 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
\r
1142 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
\r
1143 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
\r
1144 __DSB(); /* Ensure completion of memory access */
\r
1145 while(1); /* wait until reset */
\r
1148 /*@} end of CMSIS_Core_NVICFunctions */
\r
1152 /* ################################## SysTick function ############################################ */
\r
1153 /** \ingroup CMSIS_Core_FunctionInterface
\r
1154 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
\r
1158 #if (__Vendor_SysTickConfig == 0)
\r
1160 /** \brief System Tick Configuration
\r
1162 This function initialises the system tick timer and its interrupt and start the system tick timer.
\r
1163 Counter is in free running mode to generate periodical interrupts.
\r
1165 \param [in] ticks Number of ticks between two interrupts
\r
1166 \return 0 Function succeeded
\r
1167 \return 1 Function failed
\r
1169 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
1171 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
\r
1173 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
\r
1174 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
\r
1175 SysTick->VAL = 0; /* Load the SysTick Counter Value */
\r
1176 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
1177 SysTick_CTRL_TICKINT_Msk |
\r
1178 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
1179 return (0); /* Function successful */
\r
1184 /*@} end of CMSIS_Core_SysTickFunctions */
\r
1188 /* ##################################### Debug In/Output function ########################################### */
\r
1189 /** \ingroup CMSIS_Core_FunctionInterface
\r
1190 \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
\r
1194 extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
\r
1195 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
\r
1198 /** \brief ITM Send Character
\r
1200 This function transmits a character via the ITM channel 0.
\r
1201 It just returns when no debugger is connected that has booked the output.
\r
1202 It is blocking when a debugger is connected, but the previous character send is not transmitted.
\r
1204 \param [in] ch Character to transmit
\r
1205 \return Character to transmit
\r
1207 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
\r
1209 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
\r
1210 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
\r
1211 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
\r
1213 while (ITM->PORT[0].u32 == 0);
\r
1214 ITM->PORT[0].u8 = (uint8_t) ch;
\r
1220 /** \brief ITM Receive Character
\r
1222 This function inputs a character via external variable ITM_RxBuffer.
\r
1223 It just returns when no debugger is connected that has booked the output.
\r
1224 It is blocking when a debugger is connected, but the previous character send is not transmitted.
\r
1226 \return Received character
\r
1227 \return -1 No character received
\r
1229 static __INLINE int32_t ITM_ReceiveChar (void) {
\r
1230 int32_t ch = -1; /* no character available */
\r
1232 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
\r
1233 ch = ITM_RxBuffer;
\r
1234 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
\r
1241 /** \brief ITM Check Character
\r
1243 This function checks external variable ITM_RxBuffer whether a character is available or not.
\r
1244 It returns '1' if a character is available and '0' if no character is available.
\r
1246 \return 0 No character available
\r
1247 \return 1 Character available
\r
1249 static __INLINE int32_t ITM_CheckChar (void) {
\r
1251 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
\r
1252 return (0); /* no character available */
\r
1254 return (1); /* character available */
\r
1258 /*@} end of CMSIS_core_DebugFunctions */
\r
1260 #endif /* __CORE_CM4_H_DEPENDANT */
\r
1262 #endif /* __CMSIS_GENERIC */
\r
1264 #ifdef __cplusplus
\r
1268 /*lint -restore */
\r