1 /**************************************************************************//**
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2 * @file core_cmFunc.h
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3 * @brief CMSIS Cortex-M Core Function Access Header File
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5 * @date 06. December 2010
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8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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22 ******************************************************************************/
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24 #ifndef __CORE_CMFUNC_H__
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25 #define __CORE_CMFUNC_H__
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27 /* ########################### Core Function Access ########################### */
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28 /** \ingroup CMSIS_Core_FunctionInterface
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29 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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33 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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34 /* ARM armcc specific functions */
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36 /* intrinsic void __enable_irq(); */
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37 /* intrinsic void __disable_irq(); */
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39 /** \brief Get Control Register
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41 This function returns the content of the Control Register.
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43 \return Control Register value
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45 #if (__ARMCC_VERSION < 400000)
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46 extern uint32_t __get_CONTROL(void);
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47 #else /* (__ARMCC_VERSION >= 400000) */
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48 static __INLINE uint32_t __get_CONTROL(void)
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50 register uint32_t __regControl __ASM("control");
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51 return(__regControl);
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53 #endif /* __ARMCC_VERSION */
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56 /** \brief Set Control Register
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58 This function writes the given value to the Control Register.
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60 \param [in] control Control Register value to set
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62 #if (__ARMCC_VERSION < 400000)
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63 extern void __set_CONTROL(uint32_t control);
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64 #else /* (__ARMCC_VERSION >= 400000) */
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65 static __INLINE void __set_CONTROL(uint32_t control)
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67 register uint32_t __regControl __ASM("control");
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68 __regControl = control;
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70 #endif /* __ARMCC_VERSION */
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73 /** \brief Get ISPR Register
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75 This function returns the content of the ISPR Register.
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77 \return ISPR Register value
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79 #if (__ARMCC_VERSION < 400000)
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80 extern uint32_t __get_IPSR(void);
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81 #else /* (__ARMCC_VERSION >= 400000) */
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82 static __INLINE uint32_t __get_IPSR(void)
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84 register uint32_t __regIPSR __ASM("ipsr");
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87 #endif /* __ARMCC_VERSION */
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90 /** \brief Get APSR Register
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92 This function returns the content of the APSR Register.
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94 \return APSR Register value
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96 #if (__ARMCC_VERSION < 400000)
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97 extern uint32_t __get_APSR(void);
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98 #else /* (__ARMCC_VERSION >= 400000) */
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99 static __INLINE uint32_t __get_APSR(void)
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101 register uint32_t __regAPSR __ASM("apsr");
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104 #endif /* __ARMCC_VERSION */
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107 /** \brief Get xPSR Register
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109 This function returns the content of the xPSR Register.
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111 \return xPSR Register value
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113 #if (__ARMCC_VERSION < 400000)
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114 extern uint32_t __get_xPSR(void);
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115 #else /* (__ARMCC_VERSION >= 400000) */
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116 static __INLINE uint32_t __get_xPSR(void)
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118 register uint32_t __regXPSR __ASM("xpsr");
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121 #endif /* __ARMCC_VERSION */
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124 /** \brief Get Process Stack Pointer
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126 This function returns the current value of the Process Stack Pointer (PSP).
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128 \return PSP Register value
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130 #if (__ARMCC_VERSION < 400000)
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131 extern uint32_t __get_PSP(void);
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132 #else /* (__ARMCC_VERSION >= 400000) */
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133 static __INLINE uint32_t __get_PSP(void)
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135 register uint32_t __regProcessStackPointer __ASM("psp");
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136 return(__regProcessStackPointer);
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138 #endif /* __ARMCC_VERSION */
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141 /** \brief Set Process Stack Pointer
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143 This function assigns the given value to the Process Stack Pointer (PSP).
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145 \param [in] topOfProcStack Process Stack Pointer value to set
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147 #if (__ARMCC_VERSION < 400000)
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148 extern void __set_PSP(uint32_t topOfProcStack);
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149 #else /* (__ARMCC_VERSION >= 400000) */
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150 static __INLINE void __set_PSP(uint32_t topOfProcStack)
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152 register uint32_t __regProcessStackPointer __ASM("psp");
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153 __regProcessStackPointer = topOfProcStack;
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155 #endif /* __ARMCC_VERSION */
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158 /** \brief Get Main Stack Pointer
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160 This function returns the current value of the Main Stack Pointer (MSP).
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162 \return MSP Register value
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164 #if (__ARMCC_VERSION < 400000)
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165 extern uint32_t __get_MSP(void);
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166 #else /* (__ARMCC_VERSION >= 400000) */
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167 static __INLINE uint32_t __get_MSP(void)
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169 register uint32_t __regMainStackPointer __ASM("msp");
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170 return(__regMainStackPointer);
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172 #endif /* __ARMCC_VERSION */
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175 /** \brief Set Main Stack Pointer
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177 This function assigns the given value to the Main Stack Pointer (MSP).
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179 \param [in] topOfMainStack Main Stack Pointer value to set
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181 #if (__ARMCC_VERSION < 400000)
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182 extern void __set_MSP(uint32_t topOfMainStack);
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183 #else /* (__ARMCC_VERSION >= 400000) */
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184 static __INLINE void __set_MSP(uint32_t topOfMainStack)
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186 register uint32_t __regMainStackPointer __ASM("msp");
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187 __regMainStackPointer = topOfMainStack;
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189 #endif /* __ARMCC_VERSION */
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192 /** \brief Get Priority Mask
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194 This function returns the current state of the priority mask bit from the Priority Mask Register.
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196 \return Priority Mask value
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198 #if (__ARMCC_VERSION < 400000)
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199 extern uint32_t __get_PRIMASK(void);
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200 #else /* (__ARMCC_VERSION >= 400000) */
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201 static __INLINE uint32_t __get_PRIMASK(void)
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203 register uint32_t __regPriMask __ASM("primask");
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204 return(__regPriMask);
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206 #endif /* __ARMCC_VERSION */
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209 /** \brief Set Priority Mask
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211 This function assigns the given value to the Priority Mask Register.
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213 \param [in] priMask Priority Mask
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215 #if (__ARMCC_VERSION < 400000)
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216 extern void __set_PRIMASK(uint32_t priMask);
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217 #else /* (__ARMCC_VERSION >= 400000) */
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218 static __INLINE void __set_PRIMASK(uint32_t priMask)
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220 register uint32_t __regPriMask __ASM("primask");
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221 __regPriMask = (priMask);
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223 #endif /* __ARMCC_VERSION */
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226 #if (__CORTEX_M >= 0x03)
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228 /** \brief Enable FIQ
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230 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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231 Can only be executed in Privileged modes.
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233 #define __enable_fault_irq __enable_fiq
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236 /** \brief Disable FIQ
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238 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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239 Can only be executed in Privileged modes.
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241 #define __disable_fault_irq __disable_fiq
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244 /** \brief Get Base Priority
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246 This function returns the current value of the Base Priority register.
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248 \return Base Priority register value
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250 #if (__ARMCC_VERSION < 400000)
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251 extern uint32_t __get_BASEPRI(void);
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252 #else /* (__ARMCC_VERSION >= 400000) */
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253 static __INLINE uint32_t __get_BASEPRI(void)
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255 register uint32_t __regBasePri __ASM("basepri");
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256 return(__regBasePri);
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258 #endif /* __ARMCC_VERSION */
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261 /** \brief Set Base Priority
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263 This function assigns the given value to the Base Priority register.
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265 \param [in] basePri Base Priority value to set
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267 #if (__ARMCC_VERSION < 400000)
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268 extern void __set_BASEPRI(uint32_t basePri);
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269 #else /* (__ARMCC_VERSION >= 400000) */
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270 static __INLINE void __set_BASEPRI(uint32_t basePri)
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272 register uint32_t __regBasePri __ASM("basepri");
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273 __regBasePri = (basePri & 0xff);
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275 #endif /* __ARMCC_VERSION */
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278 /** \brief Get Fault Mask
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280 This function returns the current value of the Fault Mask register.
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282 \return Fault Mask register value
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284 #if (__ARMCC_VERSION < 400000)
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285 extern uint32_t __get_FAULTMASK(void);
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286 #else /* (__ARMCC_VERSION >= 400000) */
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287 static __INLINE uint32_t __get_FAULTMASK(void)
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289 register uint32_t __regFaultMask __ASM("faultmask");
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290 return(__regFaultMask);
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292 #endif /* __ARMCC_VERSION */
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295 /** \brief Set Fault Mask
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297 This function assigns the given value to the Fault Mask register.
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299 \param [in] faultMask Fault Mask value to set
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301 #if (__ARMCC_VERSION < 400000)
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302 extern void __set_FAULTMASK(uint32_t faultMask);
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303 #else /* (__ARMCC_VERSION >= 400000) */
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304 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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306 register uint32_t __regFaultMask __ASM("faultmask");
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307 __regFaultMask = (faultMask & 1);
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309 #endif /* __ARMCC_VERSION */
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311 #endif /* (__CORTEX_M >= 0x03) */
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314 #if (__CORTEX_M == 0x04)
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316 /** \brief Get FPSCR
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318 This function returns the current value of the Floating Point Status/Control register.
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320 \return Floating Point Status/Control register value
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322 static __INLINE uint32_t __get_FPSCR(void)
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324 #if (__FPU_PRESENT == 1)
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325 register uint32_t __regfpscr __ASM("fpscr");
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326 return(__regfpscr);
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333 /** \brief Set FPSCR
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335 This function assigns the given value to the Floating Point Status/Control register.
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337 \param [in] fpscr Floating Point Status/Control value to set
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339 static __INLINE void __set_FPSCR(uint32_t fpscr)
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341 #if (__FPU_PRESENT == 1)
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342 register uint32_t __regfpscr __ASM("fpscr");
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343 __regfpscr = (fpscr);
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347 #endif /* (__CORTEX_M == 0x04) */
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350 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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351 /* IAR iccarm specific functions */
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353 #if defined (__ICCARM__)
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354 #include <intrinsics.h> /* IAR Intrinsics */
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357 #pragma diag_suppress=Pe940
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359 /** \brief Enable IRQ Interrupts
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361 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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362 Can only be executed in Privileged modes.
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364 #define __enable_irq __enable_interrupt
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367 /** \brief Disable IRQ Interrupts
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369 This function disables IRQ interrupts by setting the I-bit in the CPSR.
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370 Can only be executed in Privileged modes.
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372 #define __disable_irq __disable_interrupt
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375 /* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
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376 /* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
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379 /** \brief Get ISPR Register
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381 This function returns the content of the ISPR Register.
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383 \return ISPR Register value
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385 static uint32_t __get_IPSR(void)
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387 __ASM("mrs r0, ipsr");
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391 /** \brief Get APSR Register
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393 This function returns the content of the APSR Register.
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395 \return APSR Register value
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397 static uint32_t __get_APSR(void)
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399 __ASM("mrs r0, apsr");
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403 /** \brief Get xPSR Register
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405 This function returns the content of the xPSR Register.
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407 \return xPSR Register value
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409 static uint32_t __get_xPSR(void)
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411 __ASM("mrs r0, psr"); // assembler does not know "xpsr"
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415 /** \brief Get Process Stack Pointer
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417 This function returns the current value of the Process Stack Pointer (PSP).
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419 \return PSP Register value
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421 static uint32_t __get_PSP(void)
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423 __ASM("mrs r0, psp");
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427 /** \brief Set Process Stack Pointer
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429 This function assigns the given value to the Process Stack Pointer (PSP).
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431 \param [in] topOfProcStack Process Stack Pointer value to set
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433 static void __set_PSP(uint32_t topOfProcStack)
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435 __ASM("msr psp, r0");
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439 /** \brief Get Main Stack Pointer
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441 This function returns the current value of the Main Stack Pointer (MSP).
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443 \return MSP Register value
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445 static uint32_t __get_MSP(void)
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447 __ASM("mrs r0, msp");
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451 /** \brief Set Main Stack Pointer
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453 This function assigns the given value to the Main Stack Pointer (MSP).
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455 \param [in] topOfMainStack Main Stack Pointer value to set
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457 static void __set_MSP(uint32_t topOfMainStack)
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459 __ASM("msr msp, r0");
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463 /* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
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464 /* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
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467 #if (__CORTEX_M >= 0x03)
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469 /** \brief Enable FIQ
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471 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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472 Can only be executed in Privileged modes.
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474 static __INLINE void __enable_fault_irq(void)
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480 /** \brief Disable FIQ
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482 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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483 Can only be executed in Privileged modes.
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485 static __INLINE void __disable_fault_irq(void)
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491 /* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
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492 /* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
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493 /* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
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494 /* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
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496 #endif /* (__CORTEX_M >= 0x03) */
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499 #if (__CORTEX_M == 0x04)
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501 /** \brief Get FPSCR
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503 This function returns the current value of the Floating Point Status/Control register.
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505 \return Floating Point Status/Control register value
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507 static uint32_t __get_FPSCR(void)
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509 #if (__FPU_PRESENT == 1)
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510 __ASM("vmrs r0, fpscr");
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517 /** \brief Set FPSCR
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519 This function assigns the given value to the Floating Point Status/Control register.
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521 \param [in] fpscr Floating Point Status/Control value to set
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523 static void __set_FPSCR(uint32_t fpscr)
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525 #if (__FPU_PRESENT == 1)
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526 __ASM("vmsr fpscr, r0");
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530 #endif /* (__CORTEX_M == 0x04) */
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532 #pragma diag_default=Pe940
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535 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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536 /* GNU gcc specific functions */
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538 /** \brief Enable IRQ Interrupts
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540 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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541 Can only be executed in Privileged modes.
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543 __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
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545 __ASM volatile ("cpsie i");
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549 /** \brief Disable IRQ Interrupts
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551 This function disables IRQ interrupts by setting the I-bit in the CPSR.
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552 Can only be executed in Privileged modes.
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554 __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
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556 __ASM volatile ("cpsid i");
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560 /** \brief Get Control Register
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562 This function returns the content of the Control Register.
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564 \return Control Register value
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566 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
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570 __ASM volatile ("MRS %0, control" : "=r" (result) );
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575 /** \brief Set Control Register
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577 This function writes the given value to the Control Register.
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579 \param [in] control Control Register value to set
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581 __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
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583 __ASM volatile ("MSR control, %0" : : "r" (control) );
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587 /** \brief Get ISPR Register
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589 This function returns the content of the ISPR Register.
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591 \return ISPR Register value
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593 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
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597 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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602 /** \brief Get APSR Register
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604 This function returns the content of the APSR Register.
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606 \return APSR Register value
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608 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
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612 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
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617 /** \brief Get xPSR Register
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619 This function returns the content of the xPSR Register.
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621 \return xPSR Register value
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623 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
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627 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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632 /** \brief Get Process Stack Pointer
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634 This function returns the current value of the Process Stack Pointer (PSP).
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636 \return PSP Register value
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638 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
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640 register uint32_t result;
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642 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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647 /** \brief Set Process Stack Pointer
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649 This function assigns the given value to the Process Stack Pointer (PSP).
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651 \param [in] topOfProcStack Process Stack Pointer value to set
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653 __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
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655 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
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659 /** \brief Get Main Stack Pointer
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661 This function returns the current value of the Main Stack Pointer (MSP).
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663 \return MSP Register value
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665 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
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667 register uint32_t result;
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669 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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674 /** \brief Set Main Stack Pointer
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676 This function assigns the given value to the Main Stack Pointer (MSP).
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678 \param [in] topOfMainStack Main Stack Pointer value to set
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680 __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
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682 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
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686 /** \brief Get Priority Mask
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688 This function returns the current state of the priority mask bit from the Priority Mask Register.
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690 \return Priority Mask value
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692 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
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696 __ASM volatile ("MRS %0, primask" : "=r" (result) );
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701 /** \brief Set Priority Mask
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703 This function assigns the given value to the Priority Mask Register.
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705 \param [in] priMask Priority Mask
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707 __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
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709 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
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713 #if (__CORTEX_M >= 0x03)
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715 /** \brief Enable FIQ
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717 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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718 Can only be executed in Privileged modes.
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720 __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
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722 __ASM volatile ("cpsie f");
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726 /** \brief Disable FIQ
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728 This function disables FIQ interrupts by setting the F-bit in the CPSR.
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729 Can only be executed in Privileged modes.
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731 __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
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733 __ASM volatile ("cpsid f");
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737 /** \brief Get Base Priority
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739 This function returns the current value of the Base Priority register.
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741 \return Base Priority register value
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743 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
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747 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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752 /** \brief Set Base Priority
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754 This function assigns the given value to the Base Priority register.
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756 \param [in] basePri Base Priority value to set
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758 __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
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760 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
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764 /** \brief Get Fault Mask
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766 This function returns the current value of the Fault Mask register.
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768 \return Fault Mask register value
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770 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
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774 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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779 /** \brief Set Fault Mask
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781 This function assigns the given value to the Fault Mask register.
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783 \param [in] faultMask Fault Mask value to set
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785 __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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787 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
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790 #endif /* (__CORTEX_M >= 0x03) */
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793 #if (__CORTEX_M == 0x04)
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795 /** \brief Get FPSCR
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797 This function returns the current value of the Floating Point Status/Control register.
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799 \return Floating Point Status/Control register value
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801 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
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803 #if (__FPU_PRESENT == 1)
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806 __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
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814 /** \brief Set FPSCR
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816 This function assigns the given value to the Floating Point Status/Control register.
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818 \param [in] fpscr Floating Point Status/Control value to set
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820 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
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822 #if (__FPU_PRESENT == 1)
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823 __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
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827 #endif /* (__CORTEX_M == 0x04) */
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830 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
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831 /* TASKING carm specific functions */
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834 * The CMSIS functions have been implemented as intrinsics in the compiler.
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835 * Please use "carm -?i" to get an up to date list of all instrinsics,
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836 * Including the CMSIS ones.
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841 /*@} end of CMSIS_Core_RegAccFunctions */
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844 #endif /* __CORE_CMFUNC_H__ */
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