1 /**************************************************************************//**
\r
2 * @file core_cmInstr.h
\r
3 * @brief CMSIS Cortex-M Core Instruction Access Header File
\r
5 * @date 06. December 2010
\r
8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
\r
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
\r
12 * processor based microcontrollers. This file can be freely distributed
\r
13 * within development tools that are supporting such ARM based processors.
\r
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
22 ******************************************************************************/
\r
24 #ifndef __CORE_CMINSTR_H__
\r
25 #define __CORE_CMINSTR_H__
\r
28 /* ########################## Core Instruction Access ######################### */
\r
29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
\r
30 Access to dedicated instructions
\r
34 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
\r
35 /* ARM armcc specific functions */
\r
37 /** \brief No Operation
\r
39 No Operation does nothing. This instruction can be used for code alignment purposes.
\r
44 /** \brief Wait For Interrupt
\r
46 Wait For Interrupt is a hint instruction that suspends execution
\r
47 until one of a number of events occurs.
\r
52 /** \brief Wait For Event
\r
54 Wait For Event is a hint instruction that permits the processor to enter
\r
55 a low-power state until one of a number of events occurs.
\r
60 /** \brief Send Event
\r
62 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
\r
67 /** \brief Instruction Synchronization Barrier
\r
69 Instruction Synchronization Barrier flushes the pipeline in the processor,
\r
70 so that all instructions following the ISB are fetched from cache or
\r
71 memory, after the instruction has been completed.
\r
73 #define __ISB() __isb(0xF)
\r
76 /** \brief Data Synchronization Barrier
\r
78 This function acts as a special kind of Data Memory Barrier.
\r
79 It completes when all explicit memory accesses before this instruction complete.
\r
81 #define __DSB() __dsb(0xF)
\r
84 /** \brief Data Memory Barrier
\r
86 This function ensures the apparent order of the explicit memory operations before
\r
87 and after the instruction, without ensuring their completion.
\r
89 #define __DMB() __dmb(0xF)
\r
92 /** \brief Reverse byte order (32 bit)
\r
94 This function reverses the byte order in integer value.
\r
96 \param [in] value Value to reverse
\r
97 \return Reversed value
\r
102 /** \brief Reverse byte order (16 bit)
\r
104 This function reverses the byte order in two unsigned short values.
\r
106 \param [in] value Value to reverse
\r
107 \return Reversed value
\r
109 #if (__ARMCC_VERSION < 400677)
\r
110 extern uint32_t __REV16(uint32_t value);
\r
111 #else /* (__ARMCC_VERSION >= 400677) */
\r
112 static __INLINE __ASM uint32_t __REV16(uint32_t value)
\r
117 #endif /* __ARMCC_VERSION */
\r
120 /** \brief Reverse byte order in signed short value
\r
122 This function reverses the byte order in a signed short value with sign extension to integer.
\r
124 \param [in] value Value to reverse
\r
125 \return Reversed value
\r
127 #if (__ARMCC_VERSION < 400677)
\r
128 extern int32_t __REVSH(int32_t value);
\r
129 #else /* (__ARMCC_VERSION >= 400677) */
\r
130 static __INLINE __ASM int32_t __REVSH(int32_t value)
\r
135 #endif /* __ARMCC_VERSION */
\r
138 #if (__CORTEX_M >= 0x03)
\r
140 /** \brief Reverse bit order of value
\r
142 This function reverses the bit order of the given value.
\r
144 \param [in] value Value to reverse
\r
145 \return Reversed value
\r
147 #define __RBIT __rbit
\r
150 /** \brief LDR Exclusive (8 bit)
\r
152 This function performs a exclusive LDR command for 8 bit value.
\r
154 \param [in] ptr Pointer to data
\r
155 \return value of type uint8_t at (*ptr)
\r
157 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
\r
160 /** \brief LDR Exclusive (16 bit)
\r
162 This function performs a exclusive LDR command for 16 bit values.
\r
164 \param [in] ptr Pointer to data
\r
165 \return value of type uint16_t at (*ptr)
\r
167 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
\r
170 /** \brief LDR Exclusive (32 bit)
\r
172 This function performs a exclusive LDR command for 32 bit values.
\r
174 \param [in] ptr Pointer to data
\r
175 \return value of type uint32_t at (*ptr)
\r
177 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
\r
180 /** \brief STR Exclusive (8 bit)
\r
182 This function performs a exclusive STR command for 8 bit values.
\r
184 \param [in] value Value to store
\r
185 \param [in] ptr Pointer to location
\r
186 \return 0 Function succeeded
\r
187 \return 1 Function failed
\r
189 #define __STREXB(value, ptr) __strex(value, ptr)
\r
192 /** \brief STR Exclusive (16 bit)
\r
194 This function performs a exclusive STR command for 16 bit values.
\r
196 \param [in] value Value to store
\r
197 \param [in] ptr Pointer to location
\r
198 \return 0 Function succeeded
\r
199 \return 1 Function failed
\r
201 #define __STREXH(value, ptr) __strex(value, ptr)
\r
204 /** \brief STR Exclusive (32 bit)
\r
206 This function performs a exclusive STR command for 32 bit values.
\r
208 \param [in] value Value to store
\r
209 \param [in] ptr Pointer to location
\r
210 \return 0 Function succeeded
\r
211 \return 1 Function failed
\r
213 #define __STREXW(value, ptr) __strex(value, ptr)
\r
216 /** \brief Remove the exclusive lock
\r
218 This function removes the exclusive lock which is created by LDREX.
\r
221 #if (__ARMCC_VERSION < 400000)
\r
222 extern void __CLREX(void);
\r
223 #else /* (__ARMCC_VERSION >= 400000) */
\r
224 #define __CLREX __clrex
\r
225 #endif /* __ARMCC_VERSION */
\r
228 /** \brief Signed Saturate
\r
230 This function saturates a signed value.
\r
232 \param [in] value Value to be saturated
\r
233 \param [in] sat Bit position to saturate to (1..32)
\r
234 \return Saturated value
\r
236 #define __SSAT __ssat
\r
239 /** \brief Unsigned Saturate
\r
241 This function saturates an unsigned value.
\r
243 \param [in] value Value to be saturated
\r
244 \param [in] sat Bit position to saturate to (0..31)
\r
245 \return Saturated value
\r
247 #define __USAT __usat
\r
250 /** \brief Count leading zeros
\r
252 This function counts the number of leading zeros of a data value.
\r
254 \param [in] value Value to count the leading zeros
\r
255 \return number of leading zeros in value
\r
257 #define __CLZ __clz
\r
259 #endif /* (__CORTEX_M >= 0x03) */
\r
263 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
\r
264 /* IAR iccarm specific functions */
\r
266 #include <intrinsics.h> /* IAR Intrinsics */
\r
268 #pragma diag_suppress=Pe940
\r
270 /** \brief No Operation
\r
272 No Operation does nothing. This instruction can be used for code alignment purposes.
\r
274 #define __NOP __no_operation
\r
277 /** \brief Wait For Interrupt
\r
279 Wait For Interrupt is a hint instruction that suspends execution
\r
280 until one of a number of events occurs.
\r
282 static __INLINE void __WFI(void)
\r
288 /** \brief Wait For Event
\r
290 Wait For Event is a hint instruction that permits the processor to enter
\r
291 a low-power state until one of a number of events occurs.
\r
293 static __INLINE void __WFE(void)
\r
299 /** \brief Send Event
\r
301 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
\r
303 static __INLINE void __SEV(void)
\r
309 /* intrinsic void __ISB(void) (see intrinsics.h) */
\r
310 /* intrinsic void __DSB(void) (see intrinsics.h) */
\r
311 /* intrinsic void __DMB(void) (see intrinsics.h) */
\r
312 /* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
\r
313 /* intrinsic __SSAT (see intrinsics.h) */
\r
314 /* intrinsic __USAT (see intrinsics.h) */
\r
317 /** \brief Reverse byte order (16 bit)
\r
319 This function reverses the byte order in two unsigned short values.
\r
321 \param [in] value Value to reverse
\r
322 \return Reversed value
\r
324 static uint32_t __REV16(uint32_t value)
\r
326 __ASM("rev16 r0, r0");
\r
330 /* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
\r
333 #if (__CORTEX_M >= 0x03)
\r
335 /** \brief Reverse bit order of value
\r
337 This function reverses the bit order of the given value.
\r
339 \param [in] value Value to reverse
\r
340 \return Reversed value
\r
342 static uint32_t __RBIT(uint32_t value)
\r
344 __ASM("rbit r0, r0");
\r
348 /** \brief LDR Exclusive (8 bit)
\r
350 This function performs a exclusive LDR command for 8 bit value.
\r
352 \param [in] ptr Pointer to data
\r
353 \return value of type uint8_t at (*ptr)
\r
355 static uint8_t __LDREXB(volatile uint8_t *addr)
\r
357 __ASM("ldrexb r0, [r0]");
\r
361 /** \brief LDR Exclusive (16 bit)
\r
363 This function performs a exclusive LDR command for 16 bit values.
\r
365 \param [in] ptr Pointer to data
\r
366 \return value of type uint16_t at (*ptr)
\r
368 static uint16_t __LDREXH(volatile uint16_t *addr)
\r
370 __ASM("ldrexh r0, [r0]");
\r
374 /** \brief LDR Exclusive (32 bit)
\r
376 This function performs a exclusive LDR command for 32 bit values.
\r
378 \param [in] ptr Pointer to data
\r
379 \return value of type uint32_t at (*ptr)
\r
381 /* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
\r
382 static uint32_t __LDREXW(volatile uint32_t *addr)
\r
384 __ASM("ldrex r0, [r0]");
\r
388 /** \brief STR Exclusive (8 bit)
\r
390 This function performs a exclusive STR command for 8 bit values.
\r
392 \param [in] value Value to store
\r
393 \param [in] ptr Pointer to location
\r
394 \return 0 Function succeeded
\r
395 \return 1 Function failed
\r
397 static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
\r
399 __ASM("strexb r0, r0, [r1]");
\r
403 /** \brief STR Exclusive (16 bit)
\r
405 This function performs a exclusive STR command for 16 bit values.
\r
407 \param [in] value Value to store
\r
408 \param [in] ptr Pointer to location
\r
409 \return 0 Function succeeded
\r
410 \return 1 Function failed
\r
412 static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
\r
414 __ASM("strexh r0, r0, [r1]");
\r
418 /** \brief STR Exclusive (32 bit)
\r
420 This function performs a exclusive STR command for 32 bit values.
\r
422 \param [in] value Value to store
\r
423 \param [in] ptr Pointer to location
\r
424 \return 0 Function succeeded
\r
425 \return 1 Function failed
\r
427 /* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
\r
428 static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
\r
430 __ASM("strex r0, r0, [r1]");
\r
434 /** \brief Remove the exclusive lock
\r
436 This function removes the exclusive lock which is created by LDREX.
\r
439 static __INLINE void __CLREX(void)
\r
444 /* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
\r
446 #endif /* (__CORTEX_M >= 0x03) */
\r
448 #pragma diag_default=Pe940
\r
452 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
\r
453 /* GNU gcc specific functions */
\r
455 /** \brief No Operation
\r
457 No Operation does nothing. This instruction can be used for code alignment purposes.
\r
459 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
\r
461 __ASM volatile ("nop");
\r
465 /** \brief Wait For Interrupt
\r
467 Wait For Interrupt is a hint instruction that suspends execution
\r
468 until one of a number of events occurs.
\r
470 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
\r
472 __ASM volatile ("wfi");
\r
476 /** \brief Wait For Event
\r
478 Wait For Event is a hint instruction that permits the processor to enter
\r
479 a low-power state until one of a number of events occurs.
\r
481 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
\r
483 __ASM volatile ("wfe");
\r
487 /** \brief Send Event
\r
489 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
\r
491 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
\r
493 __ASM volatile ("sev");
\r
497 /** \brief Instruction Synchronization Barrier
\r
499 Instruction Synchronization Barrier flushes the pipeline in the processor,
\r
500 so that all instructions following the ISB are fetched from cache or
\r
501 memory, after the instruction has been completed.
\r
503 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
\r
505 __ASM volatile ("isb");
\r
509 /** \brief Data Synchronization Barrier
\r
511 This function acts as a special kind of Data Memory Barrier.
\r
512 It completes when all explicit memory accesses before this instruction complete.
\r
514 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
\r
516 __ASM volatile ("dsb");
\r
520 /** \brief Data Memory Barrier
\r
522 This function ensures the apparent order of the explicit memory operations before
\r
523 and after the instruction, without ensuring their completion.
\r
525 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
\r
527 __ASM volatile ("dmb");
\r
531 /** \brief Reverse byte order (32 bit)
\r
533 This function reverses the byte order in integer value.
\r
535 \param [in] value Value to reverse
\r
536 \return Reversed value
\r
538 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
\r
542 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
\r
547 /** \brief Reverse byte order (16 bit)
\r
549 This function reverses the byte order in two unsigned short values.
\r
551 \param [in] value Value to reverse
\r
552 \return Reversed value
\r
554 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
\r
558 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
\r
563 /** \brief Reverse byte order in signed short value
\r
565 This function reverses the byte order in a signed short value with sign extension to integer.
\r
567 \param [in] value Value to reverse
\r
568 \return Reversed value
\r
570 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
\r
574 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
\r
579 #if (__CORTEX_M >= 0x03)
\r
581 /** \brief Reverse bit order of value
\r
583 This function reverses the bit order of the given value.
\r
585 \param [in] value Value to reverse
\r
586 \return Reversed value
\r
588 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
\r
592 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
\r
597 /** \brief LDR Exclusive (8 bit)
\r
599 This function performs a exclusive LDR command for 8 bit value.
\r
601 \param [in] ptr Pointer to data
\r
602 \return value of type uint8_t at (*ptr)
\r
604 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
\r
608 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
\r
613 /** \brief LDR Exclusive (16 bit)
\r
615 This function performs a exclusive LDR command for 16 bit values.
\r
617 \param [in] ptr Pointer to data
\r
618 \return value of type uint16_t at (*ptr)
\r
620 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
\r
624 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
\r
629 /** \brief LDR Exclusive (32 bit)
\r
631 This function performs a exclusive LDR command for 32 bit values.
\r
633 \param [in] ptr Pointer to data
\r
634 \return value of type uint32_t at (*ptr)
\r
636 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
\r
640 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
\r
645 /** \brief STR Exclusive (8 bit)
\r
647 This function performs a exclusive STR command for 8 bit values.
\r
649 \param [in] value Value to store
\r
650 \param [in] ptr Pointer to location
\r
651 \return 0 Function succeeded
\r
652 \return 1 Function failed
\r
654 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
\r
658 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
\r
663 /** \brief STR Exclusive (16 bit)
\r
665 This function performs a exclusive STR command for 16 bit values.
\r
667 \param [in] value Value to store
\r
668 \param [in] ptr Pointer to location
\r
669 \return 0 Function succeeded
\r
670 \return 1 Function failed
\r
672 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
\r
676 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
\r
681 /** \brief STR Exclusive (32 bit)
\r
683 This function performs a exclusive STR command for 32 bit values.
\r
685 \param [in] value Value to store
\r
686 \param [in] ptr Pointer to location
\r
687 \return 0 Function succeeded
\r
688 \return 1 Function failed
\r
690 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
\r
694 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
\r
699 /** \brief Remove the exclusive lock
\r
701 This function removes the exclusive lock which is created by LDREX.
\r
704 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
\r
706 __ASM volatile ("clrex");
\r
710 /** \brief Signed Saturate
\r
712 This function saturates a signed value.
\r
714 \param [in] value Value to be saturated
\r
715 \param [in] sat Bit position to saturate to (1..32)
\r
716 \return Saturated value
\r
718 #define __SSAT(ARG1,ARG2) \
\r
720 uint32_t __RES, __ARG1 = (ARG1); \
\r
721 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
\r
726 /** \brief Unsigned Saturate
\r
728 This function saturates an unsigned value.
\r
730 \param [in] value Value to be saturated
\r
731 \param [in] sat Bit position to saturate to (0..31)
\r
732 \return Saturated value
\r
734 #define __USAT(ARG1,ARG2) \
\r
736 uint32_t __RES, __ARG1 = (ARG1); \
\r
737 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
\r
742 /** \brief Count leading zeros
\r
744 This function counts the number of leading zeros of a data value.
\r
746 \param [in] value Value to count the leading zeros
\r
747 \return number of leading zeros in value
\r
749 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
\r
753 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
\r
757 #endif /* (__CORTEX_M >= 0x03) */
\r
762 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
\r
763 /* TASKING carm specific functions */
\r
766 * The CMSIS functions have been implemented as intrinsics in the compiler.
\r
767 * Please use "carm -?i" to get an up to date list of all instrinsics,
\r
768 * Including the CMSIS ones.
\r
773 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
\r
775 #endif /* __CORE_CMINSTR_H__ */
\r