1 ;/***********************************************************************
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2 ; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $
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4 ; * Project: LPC43xx CMSIS Package
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6 ; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx
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9 ; * Copyright(C) 2011, NXP Semiconductor
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10 ; * All rights reserved.
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12 ; ***********************************************************************
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13 ; * Software that is described herein is for illustrative purposes only
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14 ; * which provides customers with programming information regarding the
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15 ; * products. This software is supplied "AS IS" without any warranties.
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16 ; * NXP Semiconductors assumes no responsibility or liability for the
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17 ; * use of the software, conveys no license or title under any patent,
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18 ; * copyright, or mask work right to the product. NXP Semiconductors
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19 ; * reserves the right to make changes in the software without
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20 ; * notification. NXP Semiconductors also make no representation or
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21 ; * warranty that such application will be suitable for the specified
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22 ; * use without further testing or modification.
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23 ; **********************************************************************/
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25 ; <h> Stack Configuration
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26 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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29 Stack_Size EQU 0x00000400
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31 AREA STACK, NOINIT, READWRITE, ALIGN=3
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32 Stack_Mem SPACE Stack_Size
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35 ; <h> Heap Configuration
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36 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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39 Heap_Size EQU 0x00000000
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41 AREA HEAP, NOINIT, READWRITE, ALIGN=3
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43 Heap_Mem SPACE Heap_Size
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49 ; Vector Table Mapped to Address 0 at Reset
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51 AREA RESET, DATA, READONLY
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55 Sign_Value EQU 0x5A5A5A5A
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59 ;Signature_Size EQU 0x10
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64 ; SPACE Signature_Size
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66 ; DCD Reset_Handler ; 1 Reset Handler
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71 __Vectors DCD __initial_sp ; 0 Top of Stack
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72 DCD Reset_Handler ; 1 Reset Handler
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73 DCD NMI_Handler ; 2 NMI Handler
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74 DCD HardFault_Handler ; 3 Hard Fault Handler
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75 DCD MemManage_Handler ; 4 MPU Fault Handler
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76 DCD BusFault_Handler ; 5 Bus Fault Handler
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77 DCD UsageFault_Handler ; 6 Usage Fault Handler
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78 DCD Sign_Value ; 7 Reserved
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82 DCD SVC_Handler ; 11 SVCall Handler
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83 DCD DebugMon_Handler ; 12 Debug Monitor Handler
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85 DCD PendSV_Handler ; 14 PendSV Handler
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86 DCD SysTick_Handler ; 15 SysTick Handler
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88 ; External Interrupts
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89 DCD DAC_IRQHandler ; 16 D/A Converter
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90 DCD M0_IRQHandler ; 17 M0
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91 DCD DMA_IRQHandler ; 18 General Purpose DMA
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93 DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
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94 DCD ETH_IRQHandler ; 21 Ethernet
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95 DCD SDIO_IRQHandler ; 22 SD/MMC
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96 DCD LCD_IRQHandler ; 23 LCD
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97 DCD USB0_IRQHandler ; 24 USB0
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98 DCD USB1_IRQHandler ; 25 USB1
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99 DCD SCT_IRQHandler ; 26 State Configurable Timer
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100 DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
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101 DCD TIMER0_IRQHandler ; 28 Timer0
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102 DCD TIMER1_IRQHandler ; 29 Timer1
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103 DCD TIMER2_IRQHandler ; 30 Timer2
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104 DCD TIMER3_IRQHandler ; 31 Timer3
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105 DCD MCPWM_IRQHandler ; 32 Motor Control PWM
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106 DCD ADC0_IRQHandler ; 33 A/D Converter 0
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107 DCD I2C0_IRQHandler ; 34 I2C0
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108 DCD I2C1_IRQHandler ; 35 I2C1
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109 DCD SPI_IRQHandler ; 36 SPI
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110 DCD ADC1_IRQHandler ; 37 A/D Converter 1
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111 DCD SSP0_IRQHandler ; 38 SSP0
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112 DCD SSP1_IRQHandler ; 39 SSP1
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113 DCD UART0_IRQHandler ; 40 UART0
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114 DCD UART1_IRQHandler ; 41 UART1
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115 DCD UART2_IRQHandler ; 42 UART2
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116 DCD UART3_IRQHandler ; 43 UART3
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117 DCD I2S0_IRQHandler ; 44 I2S0
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118 DCD I2S1_IRQHandler ; 45 I2S1
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119 DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
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120 DCD SGPIO_IRQHandler ; 47 SGPIO
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121 DCD GPIO0_IRQHandler ; 48 GPIO0
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122 DCD GPIO1_IRQHandler ; 49 GPIO1
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123 DCD GPIO2_IRQHandler ; 50 GPIO2
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124 DCD GPIO3_IRQHandler ; 51 GPIO3
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125 DCD GPIO4_IRQHandler ; 52 GPIO4
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126 DCD GPIO5_IRQHandler ; 53 GPIO5
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127 DCD GPIO6_IRQHandler ; 54 GPIO6
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128 DCD GPIO7_IRQHandler ; 55 GPIO7
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129 DCD GINT0_IRQHandler ; 56 GINT0
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130 DCD GINT1_IRQHandler ; 57 GINT1
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131 DCD EVRT_IRQHandler ; 58 Event Router
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132 DCD CAN1_IRQHandler ; 59 C_CAN1
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133 DCD 0 ; 60 Reserved
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134 DCD VADC_IRQHandler ; 61 VADC
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135 DCD ATIMER_IRQHandler ; 62 ATIMER
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136 DCD RTC_IRQHandler ; 63 RTC
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137 DCD 0 ; 64 Reserved
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138 DCD WDT_IRQHandler ; 65 WDT
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139 DCD 0 ; 66 Reserved
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140 DCD CAN0_IRQHandler ; 67 C_CAN0
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141 DCD QEI_IRQHandler ; 68 QEI
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145 IF :LNOT::DEF:NO_CRP
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146 AREA |.ARM.__at_0x02FC|, CODE, READONLY
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147 CRP_Key DCD 0xFFFFFFFF
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150 AREA |.text|, CODE, READONLY
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155 EXPORT Reset_Handler [WEAK]
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160 ; Extend the address bus, as the bootloader configured only [A13:0]
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161 ; *(uint32_t*)(0x40086320) = 0x000000F1;
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162 ; P6_8: A14 (function 1)
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163 LDR R0, =0x40086320
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164 LDR R1, =0x000000F1
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166 ; *(uint32_t*)(0x4008631C) = 0x000000F1;
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167 ; P6_7: A15 (function 1)
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168 LDR R0, =0x4008631C
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169 LDR R1, =0x000000F1
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171 ; *(uint32_t*)(0x400866C0) = 0x000000F2;
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172 ; PD_16: A16 (function 2)
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173 LDR R0, =0x400866C0
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174 LDR R1, =0x000000F2
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176 ; *(uint32_t*)(0x400866BC) = 0x000000F2;
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177 ; PD_15: A17 (function 2)
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178 LDR R0, =0x400866BC
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179 LDR R1, =0x000000F2
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181 ; *(uint32_t*)(0x40086700) = 0x000000F3;
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182 ; PE_0: A18 (function 3)
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183 LDR R0, =0x40086700
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184 LDR R1, =0x000000F3
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186 ; *(uint32_t*)(0x40086704) = 0x000000F3;
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187 ; PE_1: A19 (function 3)
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188 LDR R0, =0x40086704
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189 LDR R1, =0x000000F3
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191 ; *(uint32_t*)(0x40086708) = 0x000000F3;
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192 ; PE_2: A20 (function 3)
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193 LDR R0, =0x40086708
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194 LDR R1, =0x000000F3
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196 ; *(uint32_t*)(0x4008670C) = 0x000000F3;
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197 ; PE_3: A21 (function 3)
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198 LDR R0, =0x4008670C
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199 LDR R1, =0x000000F3
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201 ; *(uint32_t*)(0x40086710) = 0x000000F3;
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202 ; PE_4: A22 (function 3)
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203 LDR R0, =0x40086710
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204 LDR R1, =0x000000F3
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207 ; IMPORT _startup_configureFlash
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208 ; LDR R0, =_startup_configureFlash
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220 ; Dummy Exception Handlers (infinite loops which can be modified)
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223 EXPORT NMI_Handler [WEAK]
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228 EXPORT HardFault_Handler [WEAK]
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233 EXPORT MemManage_Handler [WEAK]
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238 EXPORT BusFault_Handler [WEAK]
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241 UsageFault_Handler\
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243 EXPORT UsageFault_Handler [WEAK]
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249 EXPORT vPortSVCHandler [WEAK]
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254 EXPORT SVC_Handler [WEAK]
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259 EXPORT DebugMon_Handler [WEAK]
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264 xPortPendSVHandler\
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266 EXPORT xPortPendSVHandler [WEAK]
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270 PendSV_Handler PROC
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271 EXPORT PendSV_Handler [WEAK]
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276 xPortSysTickHandler\
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278 EXPORT xPortSysTickHandler [WEAK]
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282 SysTick_Handler PROC
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283 EXPORT SysTick_Handler [WEAK]
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287 Default_Handler PROC
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289 EXPORT DAC_IRQHandler [WEAK]
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290 EXPORT M0_IRQHandler [WEAK]
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291 EXPORT DMA_IRQHandler [WEAK]
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292 EXPORT FLASH_EEPROM_IRQHandler [WEAK]
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293 EXPORT ETH_IRQHandler [WEAK]
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294 EXPORT SDIO_IRQHandler [WEAK]
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295 EXPORT LCD_IRQHandler [WEAK]
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296 EXPORT USB0_IRQHandler [WEAK]
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297 EXPORT USB1_IRQHandler [WEAK]
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298 EXPORT SCT_IRQHandler [WEAK]
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299 EXPORT RIT_IRQHandler [WEAK]
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300 EXPORT TIMER0_IRQHandler [WEAK]
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301 EXPORT TIMER1_IRQHandler [WEAK]
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302 EXPORT TIMER2_IRQHandler [WEAK]
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303 EXPORT TIMER3_IRQHandler [WEAK]
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304 EXPORT MCPWM_IRQHandler [WEAK]
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305 EXPORT ADC0_IRQHandler [WEAK]
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306 EXPORT I2C0_IRQHandler [WEAK]
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307 EXPORT I2C1_IRQHandler [WEAK]
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308 EXPORT SPI_IRQHandler [WEAK]
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309 EXPORT ADC1_IRQHandler [WEAK]
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310 EXPORT SSP0_IRQHandler [WEAK]
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311 EXPORT SSP1_IRQHandler [WEAK]
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312 EXPORT UART0_IRQHandler [WEAK]
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313 EXPORT UART1_IRQHandler [WEAK]
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314 EXPORT UART2_IRQHandler [WEAK]
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315 EXPORT UART3_IRQHandler [WEAK]
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316 EXPORT I2S0_IRQHandler [WEAK]
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317 EXPORT I2S1_IRQHandler [WEAK]
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318 EXPORT SPIFI_IRQHandler [WEAK]
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319 EXPORT SGPIO_IRQHandler [WEAK]
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320 EXPORT GPIO0_IRQHandler [WEAK]
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321 EXPORT GPIO1_IRQHandler [WEAK]
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322 EXPORT GPIO2_IRQHandler [WEAK]
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323 EXPORT GPIO3_IRQHandler [WEAK]
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324 EXPORT GPIO4_IRQHandler [WEAK]
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325 EXPORT GPIO5_IRQHandler [WEAK]
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326 EXPORT GPIO6_IRQHandler [WEAK]
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327 EXPORT GPIO7_IRQHandler [WEAK]
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328 EXPORT GINT0_IRQHandler [WEAK]
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329 EXPORT GINT1_IRQHandler [WEAK]
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330 EXPORT EVRT_IRQHandler [WEAK]
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331 EXPORT CAN1_IRQHandler [WEAK]
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332 EXPORT VADC_IRQHandler [WEAK]
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333 EXPORT ATIMER_IRQHandler [WEAK]
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334 EXPORT RTC_IRQHandler [WEAK]
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335 EXPORT WDT_IRQHandler [WEAK]
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336 EXPORT CAN0_IRQHandler [WEAK]
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337 EXPORT QEI_IRQHandler [WEAK]
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345 FLASH_EEPROM_IRQHandler
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398 ; User Initial Stack & Heap
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402 EXPORT __initial_sp
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404 EXPORT __heap_limit
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408 IMPORT __use_two_region_memory
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409 EXPORT __user_initial_stackheap
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410 __user_initial_stackheap
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413 LDR R1, =(Stack_Mem + Stack_Size)
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414 LDR R2, = (Heap_Mem + Heap_Size)
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415 LDR R3, = Stack_Mem
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