git.sur5r.net Git - freertos/blob - Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/startup_LPC43xx.s

   1 ;/***********************************************************************\r
   2 ; * $Id: startup_LPC43xx.s 8389 2011-10-19 13:53:14Z nxp28536 $\r
   3 ; *\r
   4 ; * Project: LPC43xx CMSIS Package\r
   5 ; *\r
   6 ; * Description: Cortex-M4 Core Device Startup File for the NXP LPC18xx \r
   7 ; *              Device Series.\r
   8 ; *\r
   9 ; * Copyright(C) 2011, NXP Semiconductor\r
  10 ; * All rights reserved.\r
  11 ; *\r
  12 ; ***********************************************************************\r
  13 ; * Software that is described herein is for illustrative purposes only\r
  14 ; * which provides customers with programming information regarding the\r
  15 ; * products. This software is supplied "AS IS" without any warranties.\r
  16 ; * NXP Semiconductors assumes no responsibility or liability for the\r
  17 ; * use of the software, conveys no license or title under any patent,\r
  18 ; * copyright, or mask work right to the product. NXP Semiconductors\r
  19 ; * reserves the right to make changes in the software without\r
  20 ; * notification. NXP Semiconductors also make no representation or\r
  21 ; * warranty that such application will be suitable for the specified\r
  22 ; * use without further testing or modification.\r
  23 ; **********************************************************************/\r
  24 \r
  25 ; <h> Stack Configuration\r
  26 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  27 ; </h>\r
  28 \r
  29 Stack_Size      EQU     0x00000400\r
  30 \r
  31                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  32 Stack_Mem       SPACE   Stack_Size\r
  33 __initial_sp\r
  34 \r
  35 ; <h> Heap Configuration\r
  36 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  37 ; </h>\r
  38 \r
  39 Heap_Size       EQU     0x00000000\r
  40 \r
  41                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  42 __heap_base\r
  43 Heap_Mem        SPACE   Heap_Size\r
  44 __heap_limit\r
  45 \r
  46                 PRESERVE8\r
  47                 THUMB\r
  48 \r
  49 ; Vector Table Mapped to Address 0 at Reset\r
  50 \r
  51                 AREA    RESET, DATA, READONLY\r
  52                 EXPORT  __Vectors\r
  53                 EXPORT  __endVectors\r
  54 \r
  55 Sign_Value              EQU             0x5A5A5A5A\r
  56 \r
  57 ;                IF :DEF:EXT_FLASH\r
  58 ;\r
  59 ;Signature_Size  EQU     0x10\r
  60 ;                                DCD     0x000200DA\r
  61 ;                DCD     0x00000000\r
  62 ;                DCD     0x00000000\r
  63 ;                DCD     0x00000000\r
  64 ;                               SPACE  Signature_Size \r
  65 ;                DCD     __initial_sp\r
  66 ;                DCD     Reset_Handler             ; 1 Reset Handler\r
  67 ;                FILL    256 - 8 - 16\r
  68 ;                ENDIF\r
  69 \r
  70 \r
  71 __Vectors       DCD     __initial_sp                    ; 0 Top of Stack\r
  72                 DCD     Reset_Handler                   ; 1 Reset Handler\r
  73                 DCD     NMI_Handler                     ; 2 NMI Handler\r
  74                 DCD     HardFault_Handler               ; 3 Hard Fault Handler\r
  75                 DCD     MemManage_Handler               ; 4 MPU Fault Handler\r
  76                 DCD     BusFault_Handler                ; 5 Bus Fault Handler\r
  77                 DCD     UsageFault_Handler              ; 6 Usage Fault Handler\r
  78                 DCD     Sign_Value                      ; 7 Reserved\r
  79                 DCD     0                               ; 8 Reserved\r
  80                 DCD     0                               ; 9 Reserved\r
  81                 DCD     0                               ; 10 Reserved\r
  82                 DCD     SVC_Handler                     ; 11 SVCall Handler \r
  83                 DCD     DebugMon_Handler                ; 12 Debug Monitor Handler\r
  84                 DCD     0                               ; 13 Reserved\r
  85                 DCD     PendSV_Handler                  ; 14 PendSV Handler     \r
  86                 DCD     SysTick_Handler                 ; 15 SysTick Handler \r
  87 \r
  88                 ; External Interrupts                           \r
  89                                 DCD             DAC_IRQHandler                          ; 16 D/A Converter\r
  90                                 DCD             M0_IRQHandler                           ; 17 M0 \r
  91                                 DCD             DMA_IRQHandler                          ; 18 General Purpose DMA\r
  92                                 DCD             0                                                       ; 19 Reserved\r
  93                                 DCD             FLASH_EEPROM_IRQHandler         ; 20 Reserved for Typhoon\r
  94                                 DCD             ETH_IRQHandler                          ; 21 Ethernet\r
  95                                 DCD             SDIO_IRQHandler                         ; 22 SD/MMC\r
  96                                 DCD             LCD_IRQHandler                          ; 23 LCD\r
  97                                 DCD             USB0_IRQHandler                         ; 24 USB0\r
  98                                 DCD             USB1_IRQHandler                         ; 25 USB1\r
  99                                 DCD             SCT_IRQHandler                          ; 26 State Configurable Timer\r
 100                                 DCD             RIT_IRQHandler                          ; 27 Repetitive Interrupt Timer\r
 101                                 DCD             TIMER0_IRQHandler                       ; 28 Timer0\r
 102                                 DCD             TIMER1_IRQHandler                       ; 29 Timer1\r
 103                                 DCD             TIMER2_IRQHandler                       ; 30 Timer2\r
 104                                 DCD             TIMER3_IRQHandler                       ; 31 Timer3\r
 105                                 DCD             MCPWM_IRQHandler                        ; 32 Motor Control PWM\r
 106                                 DCD             ADC0_IRQHandler                         ; 33 A/D Converter 0\r
 107                                 DCD             I2C0_IRQHandler                         ; 34 I2C0\r
 108                                 DCD             I2C1_IRQHandler                         ; 35 I2C1\r
 109                                 DCD             SPI_IRQHandler                          ; 36 SPI\r
 110                                 DCD             ADC1_IRQHandler                         ; 37 A/D Converter 1\r
 111                                 DCD             SSP0_IRQHandler                         ; 38 SSP0\r
 112                                 DCD             SSP1_IRQHandler                         ; 39 SSP1\r
 113                                 DCD             UART0_IRQHandler                        ; 40 UART0\r
 114                                 DCD             UART1_IRQHandler                        ; 41 UART1\r
 115                                 DCD             UART2_IRQHandler                        ; 42 UART2\r
 116                                 DCD             UART3_IRQHandler                        ; 43 UART3\r
 117                                 DCD             I2S0_IRQHandler                         ; 44 I2S0\r
 118                                 DCD             I2S1_IRQHandler                         ; 45 I2S1\r
 119                                 DCD             SPIFI_IRQHandler                        ; 46 SPI Flash Interface\r
 120                                 DCD             SGPIO_IRQHandler                        ; 47 SGPIO\r
 121                                 DCD             GPIO0_IRQHandler                        ; 48 GPIO0\r
 122                                 DCD             GPIO1_IRQHandler                        ; 49 GPIO1\r
 123                                 DCD             GPIO2_IRQHandler                        ; 50 GPIO2\r
 124                                 DCD             GPIO3_IRQHandler                        ; 51 GPIO3\r
 125                                 DCD             GPIO4_IRQHandler                        ; 52 GPIO4\r
 126                                 DCD             GPIO5_IRQHandler                        ; 53 GPIO5\r
 127                                 DCD             GPIO6_IRQHandler                        ; 54 GPIO6\r
 128                                 DCD             GPIO7_IRQHandler                        ; 55 GPIO7\r
 129                                 DCD             GINT0_IRQHandler                        ; 56 GINT0\r
 130                                 DCD             GINT1_IRQHandler                        ; 57 GINT1\r
 131                                 DCD             EVRT_IRQHandler                         ; 58 Event Router\r
 132                                 DCD             CAN1_IRQHandler                         ; 59 C_CAN1\r
 133                                 DCD             0                                                       ; 60 Reserved\r
 134                                 DCD             VADC_IRQHandler                         ; 61 VADC\r
 135                                 DCD             ATIMER_IRQHandler                       ; 62 ATIMER\r
 136                                 DCD             RTC_IRQHandler                          ; 63 RTC\r
 137                                 DCD             0                                                       ; 64 Reserved\r
 138                                 DCD             WDT_IRQHandler                          ; 65 WDT\r
 139                                 DCD             0                                                       ; 66 Reserved\r
 140                                 DCD             CAN0_IRQHandler                         ; 67 C_CAN0\r
 141                                 DCD     QEI_IRQHandler                          ; 68 QEI\r
 142 \r
 143 __endVectors\r
 144                                                                                                 \r
 145                 IF      :LNOT::DEF:NO_CRP\r
 146                 AREA    |.ARM.__at_0x02FC|, CODE, READONLY\r
 147 CRP_Key         DCD     0xFFFFFFFF\r
 148                 ENDIF\r
 149 \r
 150                 AREA    |.text|, CODE, READONLY\r
 151 \r
 152 ; Reset Handler\r
 153 \r
 154 Reset_Handler   PROC\r
 155                 EXPORT  Reset_Handler             [WEAK]\r
 156                 IMPORT  __main\r
 157 \r
 158                 IF      :DEF:EXT_FLASH\r
 159 \r
 160                                 ; Extend the address bus, as the bootloader configured only [A13:0]\r
 161                         ; *(uint32_t*)(0x40086320) = 0x000000F1;  \r
 162                                 ; P6_8: A14 (function 1) \r
 163                                 LDR     R0, =0x40086320\r
 164                                 LDR     R1, =0x000000F1\r
 165                                 STR     R1, [R0,#0]\r
 166                                 ; *(uint32_t*)(0x4008631C) = 0x000000F1;  \r
 167                                 ; P6_7: A15 (function 1) \r
 168                         LDR     R0, =0x4008631C\r
 169                         LDR     R1, =0x000000F1\r
 170                             STR     R1, [R0,#0]                 \r
 171                                 ; *(uint32_t*)(0x400866C0) = 0x000000F2;  \r
 172                                 ; PD_16: A16 (function 2) \r
 173                                 LDR     R0, =0x400866C0\r
 174                                 LDR     R1, =0x000000F2\r
 175                                 STR     R1, [R0,#0]                     \r
 176                             ; *(uint32_t*)(0x400866BC) = 0x000000F2;  \r
 177                                 ; PD_15: A17 (function 2) \r
 178                                 LDR     R0, =0x400866BC\r
 179                                 LDR     R1, =0x000000F2\r
 180                                 STR     R1, [R0,#0]                     \r
 181                             ; *(uint32_t*)(0x40086700) = 0x000000F3;  \r
 182                                 ; PE_0: A18 (function 3) \r
 183                                 LDR     R0, =0x40086700\r
 184                                 LDR     R1, =0x000000F3\r
 185                                 STR     R1, [R0,#0]                     \r
 186                             ; *(uint32_t*)(0x40086704) = 0x000000F3;  \r
 187                                 ; PE_1: A19 (function 3) \r
 188                                 LDR     R0, =0x40086704\r
 189                                 LDR     R1, =0x000000F3\r
 190                                 STR     R1, [R0,#0]                     \r
 191                             ; *(uint32_t*)(0x40086708) = 0x000000F3;  \r
 192                                 ; PE_2: A20 (function 3) \r
 193                                 LDR     R0, =0x40086708\r
 194                                 LDR     R1, =0x000000F3\r
 195                                 STR     R1, [R0,#0]                     \r
 196                             ; *(uint32_t*)(0x4008670C) = 0x000000F3;  \r
 197                                 ; PE_3: A21 (function 3) \r
 198                                 LDR     R0, =0x4008670C\r
 199                                 LDR     R1, =0x000000F3\r
 200                                 STR     R1, [R0,#0]                     \r
 201                             ; *(uint32_t*)(0x40086710) = 0x000000F3;  \r
 202                                 ; PE_4: A22 (function 3) \r
 203                                 LDR     R0, =0x40086710\r
 204                                 LDR     R1, =0x000000F3\r
 205                                 STR     R1, [R0,#0]\r
 206 \r
 207 ;                               IMPORT  _startup_configureFlash\r
 208 ;                LDR     R0, =_startup_configureFlash\r
 209 ;                NOP\r
 210 ;                               NOP\r
 211 ;                               NOP\r
 212 ;                               BLX     R0\r
 213 \r
 214                                 ENDIF\r
 215 \r
 216                 LDR     R0, =__main\r
 217                 BX      R0\r
 218                 ENDP\r
 219 \r
 220 ; Dummy Exception Handlers (infinite loops which can be modified)                \r
 221 \r
 222 NMI_Handler     PROC\r
 223                 EXPORT  NMI_Handler               [WEAK]\r
 224                 B       .\r
 225                 ENDP\r
 226 HardFault_Handler\\r
 227                 PROC\r
 228                 EXPORT  HardFault_Handler         [WEAK]\r
 229                 B       .\r
 230                 ENDP\r
 231 MemManage_Handler\\r
 232                 PROC\r
 233                 EXPORT  MemManage_Handler         [WEAK]\r
 234                 B       .\r
 235                 ENDP\r
 236 BusFault_Handler\\r
 237                 PROC\r
 238                 EXPORT  BusFault_Handler          [WEAK]\r
 239                 B       .\r
 240                 ENDP\r
 241 UsageFault_Handler\\r
 242                 PROC\r
 243                 EXPORT  UsageFault_Handler        [WEAK]\r
 244                 B       .\r
 245                 ENDP\r
 246 ; FreeRTOS handler\r
 247 vPortSVCHandler\\r
 248                         PROC\r
 249                                 EXPORT  vPortSVCHandler         [WEAK]\r
 250                 B       .\r
 251                 ENDP\r
 252 \r
 253 SVC_Handler     PROC\r
 254                 EXPORT  SVC_Handler               [WEAK]\r
 255                 B       .\r
 256                 ENDP\r
 257 DebugMon_Handler\\r
 258                 PROC\r
 259                 EXPORT  DebugMon_Handler          [WEAK]\r
 260                 B       .\r
 261                 ENDP\r
 262 \r
 263 ; FreeRTOS handler\r
 264 xPortPendSVHandler\\r
 265                                 PROC\r
 266                 EXPORT  xPortPendSVHandler      [WEAK]\r
 267                 B       .\r
 268                 ENDP\r
 269 \r
 270 PendSV_Handler  PROC\r
 271                 EXPORT  PendSV_Handler      [WEAK]\r
 272                 B       .\r
 273                 ENDP\r
 274 \r
 275 ; FreeRTOS handler\r
 276 xPortSysTickHandler\\r
 277                                 PROC\r
 278                 EXPORT  xPortSysTickHandler             [WEAK]\r
 279                 B       .\r
 280                 ENDP\r
 281 \r
 282 SysTick_Handler PROC\r
 283                 EXPORT  SysTick_Handler           [WEAK]\r
 284                 B       .\r
 285                 ENDP\r
 286 \r
 287 Default_Handler PROC\r
 288 \r
 289                                 EXPORT  DAC_IRQHandler          [WEAK]\r
 290                                 EXPORT  M0_IRQHandler           [WEAK]\r
 291                                 EXPORT  DMA_IRQHandler          [WEAK]\r
 292                                 EXPORT  FLASH_EEPROM_IRQHandler [WEAK]\r
 293                                 EXPORT  ETH_IRQHandler          [WEAK]\r
 294                                 EXPORT  SDIO_IRQHandler         [WEAK]\r
 295                                 EXPORT  LCD_IRQHandler          [WEAK]\r
 296                                 EXPORT  USB0_IRQHandler         [WEAK]\r
 297                                 EXPORT  USB1_IRQHandler         [WEAK]\r
 298                                 EXPORT  SCT_IRQHandler          [WEAK]\r
 299                                 EXPORT  RIT_IRQHandler          [WEAK]\r
 300                                 EXPORT  TIMER0_IRQHandler       [WEAK]\r
 301                                 EXPORT  TIMER1_IRQHandler       [WEAK]\r
 302                                 EXPORT  TIMER2_IRQHandler       [WEAK]\r
 303                                 EXPORT  TIMER3_IRQHandler       [WEAK]\r
 304                                 EXPORT  MCPWM_IRQHandler        [WEAK]\r
 305                                 EXPORT  ADC0_IRQHandler         [WEAK]\r
 306                                 EXPORT  I2C0_IRQHandler         [WEAK]\r
 307                                 EXPORT  I2C1_IRQHandler         [WEAK]\r
 308                                 EXPORT  SPI_IRQHandler          [WEAK]\r
 309                                 EXPORT  ADC1_IRQHandler         [WEAK]\r
 310                                 EXPORT  SSP0_IRQHandler         [WEAK]\r
 311                                 EXPORT  SSP1_IRQHandler         [WEAK]\r
 312                                 EXPORT  UART0_IRQHandler        [WEAK]\r
 313                                 EXPORT  UART1_IRQHandler        [WEAK]\r
 314                                 EXPORT  UART2_IRQHandler        [WEAK]\r
 315                                 EXPORT  UART3_IRQHandler        [WEAK]\r
 316                                 EXPORT  I2S0_IRQHandler         [WEAK]\r
 317                                 EXPORT  I2S1_IRQHandler         [WEAK]\r
 318                                 EXPORT  SPIFI_IRQHandler        [WEAK]\r
 319                                 EXPORT  SGPIO_IRQHandler        [WEAK]\r
 320                                 EXPORT  GPIO0_IRQHandler        [WEAK]\r
 321                                 EXPORT  GPIO1_IRQHandler        [WEAK]\r
 322                                 EXPORT  GPIO2_IRQHandler        [WEAK]\r
 323                                 EXPORT  GPIO3_IRQHandler        [WEAK]\r
 324                                 EXPORT  GPIO4_IRQHandler        [WEAK]\r
 325                                 EXPORT  GPIO5_IRQHandler        [WEAK]\r
 326                                 EXPORT  GPIO6_IRQHandler        [WEAK]\r
 327                                 EXPORT  GPIO7_IRQHandler        [WEAK]\r
 328                                 EXPORT  GINT0_IRQHandler        [WEAK]\r
 329                                 EXPORT  GINT1_IRQHandler        [WEAK]\r
 330                                 EXPORT  EVRT_IRQHandler         [WEAK]\r
 331                                 EXPORT  CAN1_IRQHandler         [WEAK]\r
 332                                 EXPORT  VADC_IRQHandler         [WEAK]\r
 333                                 EXPORT  ATIMER_IRQHandler       [WEAK]\r
 334                                 EXPORT  RTC_IRQHandler          [WEAK]\r
 335                                 EXPORT  WDT_IRQHandler          [WEAK]\r
 336                                 EXPORT  CAN0_IRQHandler         [WEAK]\r
 337                                 EXPORT  QEI_IRQHandler          [WEAK]\r
 338 \r
 339 \r
 340 \r
 341 \r
 342 DAC_IRQHandler\r
 343 M0_IRQHandler\r
 344 DMA_IRQHandler\r
 345 FLASH_EEPROM_IRQHandler\r
 346 ETH_IRQHandler\r
 347 SDIO_IRQHandler\r
 348 LCD_IRQHandler\r
 349 USB0_IRQHandler\r
 350 USB1_IRQHandler\r
 351 SCT_IRQHandler\r
 352 RIT_IRQHandler\r
 353 TIMER0_IRQHandler\r
 354 TIMER1_IRQHandler\r
 355 TIMER2_IRQHandler\r
 356 TIMER3_IRQHandler\r
 357 MCPWM_IRQHandler\r
 358 ADC0_IRQHandler\r
 359 I2C0_IRQHandler\r
 360 I2C1_IRQHandler\r
 361 SPI_IRQHandler\r
 362 ADC1_IRQHandler\r
 363 SSP0_IRQHandler\r
 364 SSP1_IRQHandler\r
 365 UART0_IRQHandler\r
 366 UART1_IRQHandler\r
 367 UART2_IRQHandler\r
 368 UART3_IRQHandler\r
 369 I2S0_IRQHandler\r
 370 I2S1_IRQHandler\r
 371 SPIFI_IRQHandler\r
 372 SGPIO_IRQHandler\r
 373 GPIO0_IRQHandler\r
 374 GPIO1_IRQHandler\r
 375 GPIO2_IRQHandler\r
 376 GPIO3_IRQHandler\r
 377 GPIO4_IRQHandler\r
 378 GPIO5_IRQHandler\r
 379 GPIO6_IRQHandler\r
 380 GPIO7_IRQHandler\r
 381 GINT0_IRQHandler\r
 382 GINT1_IRQHandler\r
 383 EVRT_IRQHandler\r
 384 CAN1_IRQHandler\r
 385 VADC_IRQHandler\r
 386 ATIMER_IRQHandler\r
 387 RTC_IRQHandler\r
 388 WDT_IRQHandler\r
 389 CAN0_IRQHandler\r
 390 QEI_IRQHandler\r
 391 \r
 392                 B       .\r
 393 \r
 394                 ENDP\r
 395 \r
 396                 ALIGN\r
 397 \r
 398 ; User Initial Stack & Heap\r
 399 \r
 400                 IF      :DEF:__MICROLIB\r
 401                 \r
 402                 EXPORT  __initial_sp\r
 403                 EXPORT  __heap_base\r
 404                 EXPORT  __heap_limit\r
 405                 \r
 406                 ELSE\r
 407                 \r
 408                 IMPORT  __use_two_region_memory\r
 409                 EXPORT  __user_initial_stackheap\r
 410 __user_initial_stackheap\r
 411 \r
 412                 LDR     R0, =  Heap_Mem\r
 413                 LDR     R1, =(Stack_Mem + Stack_Size)\r
 414                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
 415                 LDR     R3, = Stack_Mem\r
 416                 BX      LR\r
 417 \r
 418                 ALIGN\r
 419 \r
 420                 ENDIF\r
 421 \r
 422                 END\r