1 /***********************************************************************
\r
2 * $Id: system_LPC43xx.h 8242 2011-10-11 15:15:25Z nxp28536 $
\r
4 * Project: LPC43xx Common
\r
7 * CMSIS Cortex-M4 Device Peripheral Access Layer Header File
\r
8 * for the NXP LPC43xx Device Series
\r
10 ***********************************************************************
\r
11 * Software that is described herein is for illustrative purposes only
\r
12 * which provides customers with programming information regarding the
\r
13 * products. This software is supplied "AS IS" without any warranties.
\r
14 * NXP Semiconductors assumes no responsibility or liability for the
\r
15 * use of the software, conveys no license or title under any patent,
\r
16 * copyright, or mask work right to the product. NXP Semiconductors
\r
17 * reserves the right to make changes in the software without
\r
18 * notification. NXP Semiconductors also make no representation or
\r
19 * warranty that such application will be suitable for the specified
\r
20 * use without further testing or modification.
\r
21 **********************************************************************/
\r
24 #ifndef __SYSTEM_LPC18xx_H
\r
25 #define __SYSTEM_LPC18xx_H
\r
34 #define BUTTON0 !((LPC_GPIO3->PIN>>6)&1) // P6.10
\r
35 #define BUTTON1 !((LPC_GPIO2->PIN>>0)&1) // P4.0
\r
37 /*----------------------------------------------------------------------------
\r
38 Clock Variable definitions
\r
39 DO NOT SET MANUALLY, SET WITH SetClock AND SetPL160M
\r
40 *----------------------------------------------------------------------------*/
\r
41 extern uint32_t XtalFrequency;
\r
42 extern uint32_t PL160M_0Frequency;
\r
43 extern uint32_t PL160M_1Frequency;
\r
44 extern uint32_t PL160M_2Frequency;
\r
45 extern uint32_t PL550Frequency;
\r
46 extern uint32_t PL550FracFrequency; //New in Falcon
\r
47 extern uint32_t IDIVAFrequency;
\r
48 extern uint32_t IDIVBFrequency;
\r
49 extern uint32_t IDIVCFrequency;
\r
50 extern uint32_t IDIVDFrequency;
\r
51 extern uint32_t IDIVEFrequency;
\r
52 extern uint32_t M0Frequency;
\r
53 extern uint32_t USB1Frequency;
\r
54 extern uint32_t M4Frequency;
\r
55 extern uint32_t SPIFIFrequency;
\r
56 extern uint32_t SPIFrequency;
\r
57 extern uint32_t EnetRxFrequency;
\r
58 extern uint32_t EnetTxFrequency;
\r
59 extern uint32_t EXTFrequency;
\r
60 extern uint32_t VPB1Frequency;
\r
61 extern uint32_t VPB3Frequency;
\r
62 extern uint32_t LCDFrequency;
\r
63 extern uint32_t SCIFrequency;
\r
64 extern uint32_t SDIOFrequency;
\r
65 extern uint32_t SSP0Frequency;
\r
66 extern uint32_t SSP1Frequency;
\r
67 extern uint32_t UART0Frequency;
\r
68 extern uint32_t UART1Frequency;
\r
69 extern uint32_t UART2Frequency;
\r
70 extern uint32_t UART3Frequency;
\r
71 extern uint32_t OUTFrequency;
\r
72 extern uint32_t AOTESTFrequency;
\r
73 extern uint32_t ISOFrequency;
\r
74 extern uint32_t BSRFrequency;
\r
75 extern uint32_t CLK_TESTFrequency;
\r
76 extern uint32_t APLLFrequency;
\r
77 extern uint32_t SPARE0Frequency;
\r
78 extern uint32_t SPARE1Frequency;
\r
95 SRC_ENET_RX_CLK = 2,
\r
96 SRC_ENET_TX_CLK = 3,
\r
98 RESERVED = 5, // Do NOT use
\r
101 SRC_PL550M_FRAC = 8, //New in Falcon
\r
110 NOT_DEFINED = 0xFFFFFFF, // Force a signed int enum, so every possible frequency can be entered
\r
113 typedef enum CLKBASE
\r
115 PL550M = 0, //PL550Frac is new, should be added???
\r
125 BASE_USB1_CLK = 10,
\r
127 BASE_SPIFI_CLK = 12,
\r
129 BASE_PHY_RX_CLK = 14,
\r
130 BASE_PHY_TX_CLK = 15,
\r
131 BASE_VPB1_CLK = 16,
\r
132 BASE_VPB3_CLK = 17,
\r
134 BASE_VADC_CLK = 19, //New
\r
135 BASE_SDIO_CLK = 20,
\r
136 BASE_SSP0_CLK = 21,
\r
137 BASE_SSP1_CLK = 22,
\r
138 BASE_UART0_CLK = 23,
\r
139 BASE_UART1_CLK = 24,
\r
140 BASE_UART2_CLK = 25,
\r
141 BASE_UART3_CLK = 26,
\r
143 BASE_AOTEST_CLK = 28,
\r
146 BASE_CLK_TEST = 31,
\r
147 BASE_APLL_CLK = 32, //New in Falcon
\r
148 BASE_SPARE0_CLK = 33, //New in Falcon
\r
149 BASE_SPARE1_CLK = 34, //New in Falcon
\r
156 #define MODE1A (0x3<<2) // Normal operating mode without post-divider and without pre-divider
\r
157 #define MODE1B (0x2<<2) // Normal operating mode with post-divider and without pre-divider
\r
158 #define MODE1C (0x1<<2) // Normal operating mode without post-divider and with pre-divider
\r
159 #define MODE1D (0x0<<2) // Normal operating mode with post-divider and with pre-divider.
\r
160 #define BYPASSOFF (0<<1)
\r
161 #define CLKEN (1<<4)
\r
164 #define FBSEL (1<<6)
\r
165 #define MSEL_FBDIV(n) (n<<16) // MSEL = feedback-divider value 2*M (1 to 2^15)
\r
166 #define NSEL_PREDIV(n) (n<<12) // NSEL = pre-divider value N (1 to 2^8)
\r
167 #define PSEL_POSTDIV(n) (n<<8) // PSEL = post-divider value P*2 (1 to 2^5)
\r
169 // Generic clock properties
\r
170 #define AUTO_BLOCK (1<<11)
\r
171 #define PD_ENABLE (1<<0)
\r
173 extern void SystemInit(void);
\r
174 extern void SetClock(CLKBASE_Type target_clk, CLKSRC_Type src_clk, CLKDIV_Type div);
\r
175 extern void SetPL160M(CLKSRC_Type src_clk, uint32_t mult);
\r
176 extern void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable);
\r
177 extern void EnableSourceClk(CLKSRC_Type src_clk);
\r
178 extern void DisableSourceClk(CLKSRC_Type src_clk);
\r
179 extern void IOInit(void);
\r
180 extern uint32_t GetClockFrequency(CLKSRC_Type src_clk);
\r
186 #endif /* __SYSTEM_LPC43xx_H */
\r