git.sur5r.net Git - freertos/blob - Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/asf/common/services/clock/sam4s/osc.h

   1 /**\r
   2  * \file\r
   3  *\r
   4  * \brief Chip-specific oscillator management functions.\r
   5  *\r
   6  * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
   7  *\r
   8  * \asf_license_start\r
   9  *\r
  10  * Redistribution and use in source and binary forms, with or without\r
  11  * modification, are permitted provided that the following conditions are met:\r
  12  *\r
  13  * 1. Redistributions of source code must retain the above copyright notice,\r
  14  *    this list of conditions and the following disclaimer.\r
  15  *\r
  16  * 2. Redistributions in binary form must reproduce the above copyright notice,\r
  17  *    this list of conditions and the following disclaimer in the documentation\r
  18  *    and/or other materials provided with the distribution.\r
  19  *\r
  20  * 3. The name of Atmel may not be used to endorse or promote products derived\r
  21  *    from this software without specific prior written permission.\r
  22  *\r
  23  * 4. This software may only be redistributed and used in connection with an\r
  24  *    Atmel microcontroller product.\r
  25  *\r
  26  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
  27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
  29  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
  30  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
  34  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
  35  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
  36  * POSSIBILITY OF SUCH DAMAGE.\r
  37  *\r
  38  * \asf_license_stop\r
  39  *\r
  40  */\r
  41 \r
  42 #ifndef CHIP_OSC_H_INCLUDED\r
  43 #define CHIP_OSC_H_INCLUDED\r
  44 \r
  45 #include "board.h"\r
  46 #include "pmc.h"\r
  47 \r
  48 /// @cond 0\r
  49 /**INDENT-OFF**/\r
  50 #ifdef __cplusplus\r
  51 extern "C" {\r
  52 #endif\r
  53 /**INDENT-ON**/\r
  54 /// @endcond\r
  55 \r
  56 /**\r
  57  * \weakgroup osc_group\r
  58  * @{\r
  59  */\r
  60 \r
  61 //! \name Oscillator identifiers\r
  62 //@{\r
  63 #define OSC_SLCK_32K_RC                         0    //!< Internal 32kHz RC oscillator.\r
  64 #define OSC_SLCK_32K_XTAL                       1    //!< External 32kHz crystal oscillator.\r
  65 #define OSC_SLCK_32K_BYPASS         2    //!< External 32kHz bypass oscillator.\r
  66 #define OSC_MAINCK_4M_RC                        3    //!< Internal 4MHz RC oscillator.\r
  67 #define OSC_MAINCK_8M_RC                        4    //!< Internal 8MHz RC oscillator.\r
  68 #define OSC_MAINCK_12M_RC                       5    //!< Internal 12MHz RC oscillator.\r
  69 #define OSC_MAINCK_XTAL                         6    //!< External crystal oscillator.\r
  70 #define OSC_MAINCK_BYPASS                       7    //!< External bypass oscillator.\r
  71 //@}\r
  72 \r
  73 //! \name Oscillator clock speed in hertz\r
  74 //@{\r
  75 #define OSC_SLCK_32K_RC_HZ                      CHIP_FREQ_SLCK_RC                       //!< Internal 32kHz RC oscillator.\r
  76 #define OSC_SLCK_32K_XTAL_HZ            BOARD_FREQ_SLCK_XTAL                    //!< External 32kHz crystal oscillator.\r
  77 #define OSC_SLCK_32K_BYPASS_HZ      BOARD_FREQ_SLCK_BYPASS                      //!< External 32kHz bypass oscillator.\r
  78 #define OSC_MAINCK_4M_RC_HZ                     CHIP_FREQ_MAINCK_RC_4MHZ                //!< Internal 4MHz RC oscillator.\r
  79 #define OSC_MAINCK_8M_RC_HZ                     CHIP_FREQ_MAINCK_RC_8MHZ                //!< Internal 8MHz RC oscillator.\r
  80 #define OSC_MAINCK_12M_RC_HZ            CHIP_FREQ_MAINCK_RC_12MHZ               //!< Internal 12MHz RC oscillator.\r
  81 #define OSC_MAINCK_XTAL_HZ                      BOARD_FREQ_MAINCK_XTAL                  //!< External crystal oscillator.\r
  82 #define OSC_MAINCK_BYPASS_HZ            BOARD_FREQ_MAINCK_BYPASS                //!< External bypass oscillator.\r
  83 //@}\r
  84 \r
  85 static inline void osc_enable(uint32_t ul_id)\r
  86 {\r
  87         switch (ul_id) {\r
  88         case OSC_SLCK_32K_RC:\r
  89                 break;\r
  90 \r
  91         case OSC_SLCK_32K_XTAL:\r
  92                 pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
  93                 break;\r
  94 \r
  95         case OSC_SLCK_32K_BYPASS:\r
  96                 pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);\r
  97                 break;\r
  98 \r
  99 \r
 100         case OSC_MAINCK_4M_RC:\r
 101                 pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
 102                 break;\r
 103 \r
 104         case OSC_MAINCK_8M_RC:\r
 105                 pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
 106                 break;\r
 107 \r
 108         case OSC_MAINCK_12M_RC:\r
 109                 pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
 110                 break;\r
 111 \r
 112 \r
 113         case OSC_MAINCK_XTAL:\r
 114                 pmc_switch_mainck_to_xtal(PMC_OSC_XTAL);\r
 115                 break;\r
 116 \r
 117         case OSC_MAINCK_BYPASS:\r
 118                 pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS);\r
 119                 break;\r
 120         }\r
 121 }\r
 122 \r
 123 static inline void osc_disable(uint32_t ul_id)\r
 124 {\r
 125         switch (ul_id) {\r
 126         case OSC_SLCK_32K_RC:\r
 127         case OSC_SLCK_32K_XTAL:\r
 128         case OSC_SLCK_32K_BYPASS:\r
 129                 break;\r
 130 \r
 131         case OSC_MAINCK_4M_RC:\r
 132         case OSC_MAINCK_8M_RC:\r
 133         case OSC_MAINCK_12M_RC:\r
 134                 pmc_osc_disable_fastrc();\r
 135                 break;\r
 136 \r
 137         case OSC_MAINCK_XTAL:\r
 138                 pmc_osc_disable_xtal(PMC_OSC_XTAL);\r
 139                 break;\r
 140 \r
 141         case OSC_MAINCK_BYPASS:\r
 142                 pmc_osc_disable_xtal(PMC_OSC_BYPASS);\r
 143                 break;\r
 144         }\r
 145 }\r
 146 \r
 147 static inline bool osc_is_ready(uint32_t ul_id)\r
 148 {\r
 149         switch (ul_id) {\r
 150         case OSC_SLCK_32K_RC:\r
 151                 return 1;\r
 152 \r
 153         case OSC_SLCK_32K_XTAL:\r
 154         case OSC_SLCK_32K_BYPASS:\r
 155                 return pmc_osc_is_ready_32kxtal();\r
 156 \r
 157         case OSC_MAINCK_4M_RC:\r
 158         case OSC_MAINCK_8M_RC:\r
 159         case OSC_MAINCK_12M_RC:\r
 160         case OSC_MAINCK_XTAL:\r
 161         case OSC_MAINCK_BYPASS:\r
 162                 return pmc_osc_is_ready_mainck();\r
 163         }\r
 164 \r
 165         return 0;\r
 166 }\r
 167 \r
 168 static inline uint32_t osc_get_rate(uint32_t ul_id)\r
 169 {\r
 170         switch (ul_id) {\r
 171         case OSC_SLCK_32K_RC:\r
 172                 return OSC_SLCK_32K_RC_HZ;\r
 173 \r
 174 #ifdef BOARD_FREQ_SLCK_XTAL\r
 175         case OSC_SLCK_32K_XTAL:\r
 176                 return BOARD_FREQ_SLCK_XTAL;\r
 177 #endif\r
 178 \r
 179 #ifdef BOARD_FREQ_SLCK_BYPASS\r
 180         case OSC_SLCK_32K_BYPASS:\r
 181                 return BOARD_FREQ_SLCK_BYPASS;\r
 182 #endif\r
 183 \r
 184         case OSC_MAINCK_4M_RC:\r
 185                 return OSC_MAINCK_4M_RC_HZ;\r
 186 \r
 187         case OSC_MAINCK_8M_RC:\r
 188                 return OSC_MAINCK_8M_RC_HZ;\r
 189 \r
 190         case OSC_MAINCK_12M_RC:\r
 191                 return OSC_MAINCK_12M_RC_HZ;\r
 192 \r
 193 #ifdef BOARD_FREQ_MAINCK_XTAL\r
 194         case OSC_MAINCK_XTAL:\r
 195                 return BOARD_FREQ_MAINCK_XTAL;\r
 196 #endif\r
 197 \r
 198 #ifdef BOARD_FREQ_MAINCK_BYPASS\r
 199         case OSC_MAINCK_BYPASS:\r
 200                 return BOARD_FREQ_MAINCK_BYPASS;\r
 201 #endif\r
 202         }\r
 203 \r
 204         return 0;\r
 205 }\r
 206 \r
 207 //! @}\r
 208 \r
 209 /// @cond 0\r
 210 /**INDENT-OFF**/\r
 211 #ifdef __cplusplus\r
 212 }\r
 213 #endif\r
 214 /**INDENT-ON**/\r
 215 /// @endcond\r
 216 \r
 217 #endif /* CHIP_OSC_H_INCLUDED */\r