4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * 1. Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the following disclaimer.
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14 * 2. Redistributions in binary form must reproduce the above copyright notice,
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15 * this list of conditions and the following disclaimer in the documentation
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16 * and/or other materials provided with the distribution.
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18 * 3. The name of Atmel may not be used to endorse or promote products derived
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19 * from this software without specific prior written permission.
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21 * 4. This software may only be redistributed and used in connection with an
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22 * Atmel microcontroller product.
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24 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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27 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 * POSSIBILITY OF SUCH DAMAGE.
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40 #ifndef _SAM4S_ACC_INSTANCE_
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41 #define _SAM4S_ACC_INSTANCE_
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43 /* ========== Register definition for ACC peripheral ========== */
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44 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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45 #define REG_ACC_CR (0x40040000U) /**< \brief (ACC) Control Register */
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46 #define REG_ACC_MR (0x40040004U) /**< \brief (ACC) Mode Register */
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47 #define REG_ACC_IER (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
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48 #define REG_ACC_IDR (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
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49 #define REG_ACC_IMR (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
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50 #define REG_ACC_ISR (0x40040030U) /**< \brief (ACC) Interrupt Status Register */
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51 #define REG_ACC_ACR (0x40040094U) /**< \brief (ACC) Analog Control Register */
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52 #define REG_ACC_WPMR (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
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53 #define REG_ACC_WPSR (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
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55 #define REG_ACC_CR (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */
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56 #define REG_ACC_MR (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */
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57 #define REG_ACC_IER (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
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58 #define REG_ACC_IDR (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
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59 #define REG_ACC_IMR (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
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60 #define REG_ACC_ISR (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */
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61 #define REG_ACC_ACR (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */
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62 #define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
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63 #define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
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64 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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66 #endif /* _SAM4S_ACC_INSTANCE_ */
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