4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * 1. Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the following disclaimer.
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14 * 2. Redistributions in binary form must reproduce the above copyright notice,
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15 * this list of conditions and the following disclaimer in the documentation
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16 * and/or other materials provided with the distribution.
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18 * 3. The name of Atmel may not be used to endorse or promote products derived
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19 * from this software without specific prior written permission.
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21 * 4. This software may only be redistributed and used in connection with an
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22 * Atmel microcontroller product.
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24 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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27 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 * POSSIBILITY OF SUCH DAMAGE.
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40 #ifndef _SAM4S_SPI_INSTANCE_
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41 #define _SAM4S_SPI_INSTANCE_
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43 /* ========== Register definition for SPI peripheral ========== */
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44 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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45 #define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */
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46 #define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */
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47 #define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */
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48 #define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
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49 #define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */
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50 #define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
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51 #define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
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52 #define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
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53 #define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */
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54 #define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
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55 #define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
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56 #define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
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57 #define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */
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58 #define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
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59 #define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
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60 #define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
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61 #define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
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62 #define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
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63 #define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
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64 #define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */
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65 #define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */
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67 #define REG_SPI_CR (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
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68 #define REG_SPI_MR (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
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69 #define REG_SPI_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
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70 #define REG_SPI_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
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71 #define REG_SPI_SR (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
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72 #define REG_SPI_IER (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
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73 #define REG_SPI_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
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74 #define REG_SPI_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
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75 #define REG_SPI_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
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76 #define REG_SPI_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
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77 #define REG_SPI_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
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78 #define REG_SPI_RPR (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
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79 #define REG_SPI_RCR (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
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80 #define REG_SPI_TPR (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
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81 #define REG_SPI_TCR (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
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82 #define REG_SPI_RNPR (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
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83 #define REG_SPI_RNCR (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
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84 #define REG_SPI_TNPR (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
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85 #define REG_SPI_TNCR (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
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86 #define REG_SPI_PTCR (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
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87 #define REG_SPI_PTSR (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
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88 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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90 #endif /* _SAM4S_SPI_INSTANCE_ */
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