4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * 1. Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the following disclaimer.
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14 * 2. Redistributions in binary form must reproduce the above copyright notice,
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15 * this list of conditions and the following disclaimer in the documentation
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16 * and/or other materials provided with the distribution.
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18 * 3. The name of Atmel may not be used to endorse or promote products derived
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19 * from this software without specific prior written permission.
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21 * 4. This software may only be redistributed and used in connection with an
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22 * Atmel microcontroller product.
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24 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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27 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 * POSSIBILITY OF SUCH DAMAGE.
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43 /** \addtogroup SAM4S16C_definitions SAM4S16C definitions
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44 This file defines all structures and symbols for SAM4S16C:
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45 - registers and bitfields
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46 - peripheral base address
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56 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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59 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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61 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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63 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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64 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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67 /* ************************************************************************** */
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68 /* CMSIS DEFINITIONS FOR SAM4S16C */
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69 /* ************************************************************************** */
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70 /** \addtogroup SAM4S16C_cmsis CMSIS Definitions */
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73 /**< Interrupt Number Definition */
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76 /****** Cortex-M4 Processor Exceptions Numbers ******************************/
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77 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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78 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
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79 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
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80 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
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81 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
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82 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
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83 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
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84 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
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85 /****** SAM4S16C specific Interrupt Numbers *********************************/
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87 SUPC_IRQn = 0, /**< 0 SAM4S16C Supply Controller (SUPC) */
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88 RSTC_IRQn = 1, /**< 1 SAM4S16C Reset Controller (RSTC) */
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89 RTC_IRQn = 2, /**< 2 SAM4S16C Real Time Clock (RTC) */
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90 RTT_IRQn = 3, /**< 3 SAM4S16C Real Time Timer (RTT) */
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91 WDT_IRQn = 4, /**< 4 SAM4S16C Watchdog Timer (WDT) */
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92 PMC_IRQn = 5, /**< 5 SAM4S16C Power Management Controller (PMC) */
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93 EFC_IRQn = 6, /**< 6 SAM4S16C Enhanced Embedded Flash Controller (EFC) */
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94 UART0_IRQn = 8, /**< 8 SAM4S16C UART 0 (UART0) */
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95 UART1_IRQn = 9, /**< 9 SAM4S16C UART 1 (UART1) */
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96 SMC_IRQn = 10, /**< 10 SAM4S16C Static Memory Controller (SMC) */
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97 PIOA_IRQn = 11, /**< 11 SAM4S16C Parallel I/O Controller A (PIOA) */
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98 PIOB_IRQn = 12, /**< 12 SAM4S16C Parallel I/O Controller B (PIOB) */
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99 PIOC_IRQn = 13, /**< 13 SAM4S16C Parallel I/O Controller C (PIOC) */
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100 USART0_IRQn = 14, /**< 14 SAM4S16C USART 0 (USART0) */
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101 USART1_IRQn = 15, /**< 15 SAM4S16C USART 1 (USART1) */
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102 HSMCI_IRQn = 18, /**< 18 SAM4S16C Multimedia Card Interface (HSMCI) */
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103 TWI0_IRQn = 19, /**< 19 SAM4S16C Two Wire Interface 0 (TWI0) */
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104 TWI1_IRQn = 20, /**< 20 SAM4S16C Two Wire Interface 1 (TWI1) */
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105 SPI_IRQn = 21, /**< 21 SAM4S16C Serial Peripheral Interface (SPI) */
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106 SSC_IRQn = 22, /**< 22 SAM4S16C Synchronous Serial Controller (SSC) */
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107 TC0_IRQn = 23, /**< 23 SAM4S16C Timer/Counter 0 (TC0) */
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108 TC1_IRQn = 24, /**< 24 SAM4S16C Timer/Counter 1 (TC1) */
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109 TC2_IRQn = 25, /**< 25 SAM4S16C Timer/Counter 2 (TC2) */
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110 TC3_IRQn = 26, /**< 26 SAM4S16C Timer/Counter 3 (TC3) */
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111 TC4_IRQn = 27, /**< 27 SAM4S16C Timer/Counter 4 (TC4) */
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112 TC5_IRQn = 28, /**< 28 SAM4S16C Timer/Counter 5 (TC5) */
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113 ADC_IRQn = 29, /**< 29 SAM4S16C Analog To Digital Converter (ADC) */
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114 DACC_IRQn = 30, /**< 30 SAM4S16C Digital To Analog Converter (DACC) */
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115 PWM_IRQn = 31, /**< 31 SAM4S16C Pulse Width Modulation (PWM) */
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116 CRCCU_IRQn = 32, /**< 32 SAM4S16C CRC Calculation Unit (CRCCU) */
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117 ACC_IRQn = 33, /**< 33 SAM4S16C Analog Comparator (ACC) */
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118 UDP_IRQn = 34 /**< 34 SAM4S16C USB Device Port (UDP) */
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121 typedef struct _DeviceVectors
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123 /* Stack pointer */
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126 /* Cortex-M handlers */
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127 void* pfnReset_Handler;
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128 void* pfnNMI_Handler;
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129 void* pfnHardFault_Handler;
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130 void* pfnMemManage_Handler;
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131 void* pfnBusFault_Handler;
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132 void* pfnUsageFault_Handler;
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133 void* pfnReserved1_Handler;
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134 void* pfnReserved2_Handler;
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135 void* pfnReserved3_Handler;
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136 void* pfnReserved4_Handler;
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137 void* pfnSVC_Handler;
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138 void* pfnDebugMon_Handler;
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139 void* pfnReserved5_Handler;
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140 void* pfnPendSV_Handler;
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141 void* pfnSysTick_Handler;
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143 /* Peripheral handlers */
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144 void* pfnSUPC_Handler; /* 0 Supply Controller */
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145 void* pfnRSTC_Handler; /* 1 Reset Controller */
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146 void* pfnRTC_Handler; /* 2 Real Time Clock */
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147 void* pfnRTT_Handler; /* 3 Real Time Timer */
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148 void* pfnWDT_Handler; /* 4 Watchdog Timer */
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149 void* pfnPMC_Handler; /* 5 Power Management Controller */
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150 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
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152 void* pfnUART0_Handler; /* 8 UART 0 */
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153 void* pfnUART1_Handler; /* 9 UART 1 */
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154 void* pfnSMC_Handler; /* 10 Static Memory Controller */
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155 void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
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156 void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
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157 void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */
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158 void* pfnUSART0_Handler; /* 14 USART 0 */
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159 void* pfnUSART1_Handler; /* 15 USART 1 */
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160 void* pvReserved16;
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161 void* pvReserved17;
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162 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
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163 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */
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164 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */
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165 void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */
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166 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
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167 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
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168 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
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169 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
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170 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
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171 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
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172 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
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173 void* pfnADC_Handler; /* 29 Analog To Digital Converter */
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174 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
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175 void* pfnPWM_Handler; /* 31 Pulse Width Modulation */
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176 void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */
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177 void* pfnACC_Handler; /* 33 Analog Comparator */
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178 void* pfnUDP_Handler; /* 34 USB Device Port */
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181 /* Cortex-M4 core handlers */
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182 void Reset_Handler ( void );
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183 void NMI_Handler ( void );
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184 void HardFault_Handler ( void );
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185 void MemManage_Handler ( void );
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186 void BusFault_Handler ( void );
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187 void UsageFault_Handler ( void );
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188 void SVC_Handler ( void );
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189 void DebugMon_Handler ( void );
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190 void PendSV_Handler ( void );
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191 void SysTick_Handler ( void );
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193 /* Peripherals handlers */
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194 void ACC_Handler ( void );
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195 void ADC_Handler ( void );
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196 void CRCCU_Handler ( void );
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197 void DACC_Handler ( void );
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198 void EFC_Handler ( void );
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199 void HSMCI_Handler ( void );
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200 void PIOA_Handler ( void );
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201 void PIOB_Handler ( void );
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202 void PIOC_Handler ( void );
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203 void PMC_Handler ( void );
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204 void PWM_Handler ( void );
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205 void RSTC_Handler ( void );
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206 void RTC_Handler ( void );
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207 void RTT_Handler ( void );
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208 void SMC_Handler ( void );
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209 void SPI_Handler ( void );
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210 void SSC_Handler ( void );
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211 void SUPC_Handler ( void );
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212 void TC0_Handler ( void );
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213 void TC1_Handler ( void );
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214 void TC2_Handler ( void );
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215 void TC3_Handler ( void );
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216 void TC4_Handler ( void );
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217 void TC5_Handler ( void );
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218 void TWI0_Handler ( void );
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219 void TWI1_Handler ( void );
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220 void UART0_Handler ( void );
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221 void UART1_Handler ( void );
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222 void UDP_Handler ( void );
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223 void USART0_Handler ( void );
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224 void USART1_Handler ( void );
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225 void WDT_Handler ( void );
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228 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
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231 #define __CM4_REV 0x0000 /**< SAM4S16C core revision number ([15:8] revision number, [7:0] patch number) */
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232 #define __MPU_PRESENT 1 /**< SAM4S16C does provide a MPU */
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233 #define __FPU_PRESENT 0 /**< SAM4S16C does not provide a FPU */
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234 #define __NVIC_PRIO_BITS 4 /**< SAM4S16C uses 4 Bits for the Priority Levels */
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235 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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238 * \brief CMSIS includes
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241 #include <core_cm4.h>
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242 #if !defined DONT_USE_CMSIS_INIT
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243 #include "system_sam4s.h"
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244 #endif /* DONT_USE_CMSIS_INIT */
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248 /* ************************************************************************** */
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249 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S16C */
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250 /* ************************************************************************** */
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251 /** \addtogroup SAM4S16C_api Peripheral Software API */
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254 #include "component/component_acc.h"
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255 #include "component/component_adc.h"
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256 #include "component/component_chipid.h"
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257 #include "component/component_crccu.h"
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258 #include "component/component_dacc.h"
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259 #include "component/component_efc.h"
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260 #include "component/component_gpbr.h"
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261 #include "component/component_hsmci.h"
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262 #include "component/component_matrix.h"
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263 #include "component/component_pdc.h"
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264 #include "component/component_pio.h"
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265 #include "component/component_pmc.h"
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266 #include "component/component_pwm.h"
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267 #include "component/component_rstc.h"
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268 #include "component/component_rtc.h"
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269 #include "component/component_rtt.h"
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270 #include "component/component_smc.h"
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271 #include "component/component_spi.h"
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272 #include "component/component_ssc.h"
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273 #include "component/component_supc.h"
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274 #include "component/component_tc.h"
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275 #include "component/component_twi.h"
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276 #include "component/component_uart.h"
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277 #include "component/component_udp.h"
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278 #include "component/component_usart.h"
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279 #include "component/component_wdt.h"
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282 /* ************************************************************************** */
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283 /* REGISTER ACCESS DEFINITIONS FOR SAM4S16C */
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284 /* ************************************************************************** */
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285 /** \addtogroup SAM4S16C_reg Registers Access Definitions */
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288 #include "instance/instance_hsmci.h"
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289 #include "instance/instance_ssc.h"
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290 #include "instance/instance_spi.h"
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291 #include "instance/instance_tc0.h"
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292 #include "instance/instance_tc1.h"
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293 #include "instance/instance_twi0.h"
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294 #include "instance/instance_twi1.h"
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295 #include "instance/instance_pwm.h"
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296 #include "instance/instance_usart0.h"
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297 #include "instance/instance_usart1.h"
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298 #include "instance/instance_udp.h"
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299 #include "instance/instance_adc.h"
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300 #include "instance/instance_dacc.h"
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301 #include "instance/instance_acc.h"
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302 #include "instance/instance_crccu.h"
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303 #include "instance/instance_smc.h"
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304 #include "instance/instance_matrix.h"
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305 #include "instance/instance_pmc.h"
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306 #include "instance/instance_uart0.h"
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307 #include "instance/instance_chipid.h"
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308 #include "instance/instance_uart1.h"
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309 #include "instance/instance_efc.h"
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310 #include "instance/instance_pioa.h"
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311 #include "instance/instance_piob.h"
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312 #include "instance/instance_pioc.h"
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313 #include "instance/instance_rstc.h"
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314 #include "instance/instance_supc.h"
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315 #include "instance/instance_rtt.h"
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316 #include "instance/instance_wdt.h"
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317 #include "instance/instance_rtc.h"
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318 #include "instance/instance_gpbr.h"
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321 /* ************************************************************************** */
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322 /* PERIPHERAL ID DEFINITIONS FOR SAM4S16C */
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323 /* ************************************************************************** */
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324 /** \addtogroup SAM4S16C_id Peripheral Ids Definitions */
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327 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
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328 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
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329 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
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330 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
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331 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
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332 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
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333 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
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334 #define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
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335 #define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
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336 #define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */
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337 #define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
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338 #define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
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339 #define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
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340 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */
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341 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */
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342 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
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343 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
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344 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
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345 #define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
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346 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
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347 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
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348 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
\r
349 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
\r
350 #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
\r
351 #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
\r
352 #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
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353 #define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
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354 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
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355 #define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
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356 #define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */
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357 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
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358 #define ID_UDP (34) /**< \brief USB Device Port (UDP) */
\r
361 /* ************************************************************************** */
\r
362 /* BASE ADDRESS DEFINITIONS FOR SAM4S16C */
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363 /* ************************************************************************** */
\r
364 /** \addtogroup SAM4S16C_base Peripheral Base Address Definitions */
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367 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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368 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
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369 #define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
\r
370 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
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371 #define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */
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372 #define SPI (0x40008000U) /**< \brief (SPI ) Base Address */
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373 #define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */
\r
374 #define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
\r
375 #define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */
\r
376 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */
\r
377 #define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
\r
378 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */
\r
379 #define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */
\r
380 #define PWM (0x40020000U) /**< \brief (PWM ) Base Address */
\r
381 #define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */
\r
382 #define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */
\r
383 #define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
\r
384 #define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */
\r
385 #define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
\r
386 #define UDP (0x40034000U) /**< \brief (UDP ) Base Address */
\r
387 #define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
\r
388 #define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
\r
389 #define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */
\r
390 #define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
\r
391 #define ACC (0x40040000U) /**< \brief (ACC ) Base Address */
\r
392 #define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */
\r
393 #define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */
\r
394 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
\r
395 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
\r
396 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */
\r
397 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
\r
398 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
\r
399 #define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */
\r
400 #define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
\r
401 #define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
\r
402 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
403 #define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */
\r
404 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
405 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
406 #define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
\r
407 #define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
\r
408 #define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
\r
409 #define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
\r
410 #define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
\r
411 #define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
\r
413 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
414 #define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
\r
415 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
\r
416 #define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */
\r
417 #define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */
\r
418 #define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */
\r
419 #define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
\r
420 #define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */
\r
421 #define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */
\r
422 #define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
\r
423 #define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */
\r
424 #define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */
\r
425 #define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */
\r
426 #define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */
\r
427 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */
\r
428 #define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
\r
429 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */
\r
430 #define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
\r
431 #define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */
\r
432 #define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
\r
433 #define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
\r
434 #define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */
\r
435 #define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
\r
436 #define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */
\r
437 #define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */
\r
438 #define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */
\r
439 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
\r
440 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
\r
441 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */
\r
442 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
\r
443 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
\r
444 #define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */
\r
445 #define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
\r
446 #define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
\r
447 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
448 #define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */
\r
449 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
450 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
451 #define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
\r
452 #define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
\r
453 #define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
\r
454 #define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
\r
455 #define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
\r
456 #define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
\r
457 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
460 /* ************************************************************************** */
\r
461 /* PIO DEFINITIONS FOR SAM4S16C */
\r
462 /* ************************************************************************** */
\r
463 /** \addtogroup SAM4S16C_pio Peripheral Pio Definitions */
\r
466 #include "pio/pio_sam4s16c.h"
\r
469 /* ************************************************************************** */
\r
470 /* MEMORY MAPPING DEFINITIONS FOR SAM4S16C */
\r
471 /* ************************************************************************** */
\r
473 #define IFLASH_SIZE (0x100000u)
\r
474 #define IFLASH_PAGE_SIZE (512u)
\r
475 #define IFLASH_LOCK_REGION_SIZE (8192u)
\r
476 #define IFLASH_NB_OF_PAGES (2048u)
\r
477 #define IFLASH_NB_OF_LOCK_BITS (128u)
\r
478 #define IRAM_SIZE (0x20000u)
\r
480 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
\r
481 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
\r
482 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
\r
483 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
\r
484 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
\r
485 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
\r
486 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
\r
488 /* ************************************************************************** */
\r
489 /* ELECTRICAL DEFINITIONS FOR SAM4S16C */
\r
490 /* ************************************************************************** */
\r
492 /* Device characteristics */
\r
493 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
\r
494 #define CHIP_FREQ_SLCK_RC (32000UL)
\r
495 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
\r
496 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
\r
497 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
\r
498 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
\r
499 #define CHIP_FREQ_CPU_MAX (120000000UL)
\r
500 #define CHIP_FREQ_XTAL_32K (32768UL)
\r
501 #define CHIP_FREQ_XTAL_12M (12000000UL)
\r
503 /* Embedded Flash Write Wait State */
\r
504 #define CHIP_FLASH_WRITE_WAIT_STATE (6U)
\r
506 /* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
\r
507 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
\r
508 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
\r
509 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
\r
510 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
\r
511 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
\r
519 #endif /* _SAM4S16C_ */
\r