1 /************************************************************************/
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2 /* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
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4 /* The following software deliverable is intended for and must only be */
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5 /* used for reference and in an evaluation laboratory environment. */
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6 /* It is provided on an as-is basis without charge and is subject to */
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8 /* It is the user's obligation to fully test the software in its */
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9 /* environment and to ensure proper functionality, qualification and */
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10 /* compliance with component specifications. */
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12 /* In the event the software deliverable includes the use of open */
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13 /* source components, the provisions of the governing open source */
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14 /* license agreement shall apply with respect to such software */
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16 /* FSEU does not warrant that the deliverables do not infringe any */
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17 /* third party intellectual property right (IPR). In the event that */
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18 /* the deliverables infringe a third party IPR it is the sole */
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19 /* responsibility of the customer to obtain necessary licenses to */
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20 /* continue the usage of the deliverable. */
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22 /* To the maximum extent permitted by applicable law FSEU disclaims all */
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23 /* warranties, whether express or implied, in particular, but not */
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24 /* limited to, warranties of merchantability and fitness for a */
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25 /* particular purpose for which the deliverable is not designated. */
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27 /* To the maximum extent permitted by applicable law, FSEU's liability */
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28 /* is restricted to intentional misconduct and gross negligence. */
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29 /* FSEU is not liable for consequential damages. */
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32 /************************************************************************/
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34 /* Header File for Device MB9AF314L */
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36 /* Date 2011-05-18 */
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38 /************************************************************************/
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40 #ifndef _MB9AF314L_H_
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41 #define _MB9AF314L_H_
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48 /******************************************************************************
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49 * Configuration of the Cortex-M3 Processor and Core Peripherals
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50 ******************************************************************************/
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51 #define __MPU_PRESENT 1 /* FM3 provide an MPU */
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52 #define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */
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53 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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56 /******************************************************************************
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57 * Interrupt Number Definition
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58 ******************************************************************************/
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61 NMI_IRQn = -14, /* 2 Non Maskable */
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62 HardFault_IRQn = -13, /* 3 Hard Fault */
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63 MemManage_IRQn = -12, /* 4 Memory Management */
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64 BusFault_IRQn = -11, /* 5 Bus Fault */
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65 UsageFault_IRQn = -10, /* 6 Usage Fault */
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66 SVC_IRQn = -5, /* 11 SV Call */
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67 DebugMonitor_IRQn = -4, /* 12 Debug Monitor */
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68 PendSV_IRQn = -2, /* 14 Pend SV */
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69 SysTick_IRQn = -1, /* 15 System Tick */
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71 CSV_IRQn = 0, /* Clock Super Visor */
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72 SWDT_IRQn = 1, /* Software Watchdog Timer */
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73 LVD_IRQn = 2, /* Low Voltage Detector */
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74 WFG_IRQn = 3, /* Wave Form Generator */
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75 EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */
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76 EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */
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77 DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */
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78 MFS0RX_IRQn = 7, /* MultiFunction Serial Reception ch.0 */
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79 MFS0TX_IRQn = 8, /* MultiFunction Serial Transmission ch.0 */
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80 MFS1RX_IRQn = 9, /* MultiFunction Serial Reception ch.1 */
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81 MFS1TX_IRQn = 10, /* MultiFunction Serial Transmission ch.1 */
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82 MFS2RX_IRQn = 11, /* MultiFunction Serial Reception ch.2 */
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83 MFS2TX_IRQn = 12, /* MultiFunction Serial Transmission ch.2 */
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84 MFS3RX_IRQn = 13, /* MultiFunction Serial Reception ch.3 */
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85 MFS3TX_IRQn = 14, /* MultiFunction Serial Transmission ch.3 */
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86 MFS4RX_IRQn = 15, /* MultiFunction Serial Reception ch.4 */
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87 MFS4TX_IRQn = 16, /* MultiFunction Serial Transmission ch.4 */
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88 MFS5RX_IRQn = 17, /* MultiFunction Serial Reception ch.5 */
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89 MFS5TX_IRQn = 18, /* MultiFunction Serial Transmission ch.5 */
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90 MFS6RX_IRQn = 19, /* MultiFunction Serial Reception ch.6 */
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91 MFS6TX_IRQn = 20, /* MultiFunction Serial Transmission ch.6 */
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92 MFS7RX_IRQn = 21, /* MultiFunction Serial Reception ch.7 */
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93 MFS7TX_IRQn = 22, /* MultiFunction Serial Transmission ch.7 */
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94 PPG_IRQn = 23, /* PPG */
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95 OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */
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96 ADC0_IRQn = 25, /* ADC0 */
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97 ADC1_IRQn = 26, /* ADC1 */
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99 FRTIM_IRQn = 28, /* Free-run Timer */
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100 INCAP_IRQn = 29, /* Input Capture */
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101 OUTCOMP_IRQn = 30, /* Output Compare */
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102 BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */
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103 /* Reserved = 32 */
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104 /* Reserved = 33 */
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105 USBF_IRQn = 34, /* USB Function */
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106 USBF_USBH_IRQn = 35, /* USB Function / USB Host */
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107 /* Reserved = 36 */
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108 /* Reserved = 37 */
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109 DMAC0_IRQn = 38, /* DMAC ch.0 */
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110 DMAC1_IRQn = 39, /* DMAC ch.1 */
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111 DMAC2_IRQn = 40, /* DMAC ch.2 */
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112 DMAC3_IRQn = 41, /* DMAC ch.3 */
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113 DMAC4_IRQn = 42, /* DMAC ch.4 */
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114 DMAC5_IRQn = 43, /* DMAC ch.5 */
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115 DMAC6_IRQn = 44, /* DMAC ch.6 */
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116 DMAC7_IRQn = 45 /* DMAC ch.7 */
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117 /* Reserved = 46 */
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118 /* Reserved = 47 */
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122 #include <core_cm3.h>
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123 #include "system_mb9af31x.h"
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124 #include <stdint.h>
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134 /******************************************************************************/
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135 /* Device Specific Peripheral Registers structures */
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136 /******************************************************************************/
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138 #if defined ( __CC_ARM )
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139 #pragma anon_unions
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142 /******************************************************************************
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143 * Peripheral register bit fields
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144 ******************************************************************************/
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146 /******************************************************************************
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148 ******************************************************************************/
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149 /* Flash_IF_MODULE register bit fields */
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150 typedef struct stc_flash_if_faszr_field
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152 __IO uint32_t ASZ0 : 1;
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153 __IO uint32_t ASZ1 : 1;
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154 } stc_flash_if_faszr_field_t;
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156 typedef struct stc_flash_if_frwtr_field
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158 __IO uint32_t RWT0 : 1;
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159 __IO uint32_t RWT1 : 1;
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160 } stc_flash_if_frwtr_field_t;
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162 typedef struct stc_flash_if_fstr_field
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164 __IO uint32_t RDY : 1;
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165 __IO uint32_t HNG : 1;
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166 __IO uint32_t EER : 1;
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167 } stc_flash_if_fstr_field_t;
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169 typedef struct stc_flash_if_fsyndn_field
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171 __IO uint32_t SD0 : 1;
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172 __IO uint32_t SD1 : 1;
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173 __IO uint32_t SD2 : 1;
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174 } stc_flash_if_fsyndn_field_t;
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176 typedef struct stc_flash_if_crtrmm_field
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178 __IO uint32_t TRMM0 : 1;
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179 __IO uint32_t TRMM1 : 1;
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180 __IO uint32_t TRMM2 : 1;
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181 __IO uint32_t TRMM3 : 1;
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182 __IO uint32_t TRMM4 : 1;
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183 __IO uint32_t TRMM5 : 1;
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184 __IO uint32_t TRMM6 : 1;
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185 __IO uint32_t TRMM7 : 1;
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186 __IO uint32_t TRMM8 : 1;
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187 __IO uint32_t TRMM9 : 1;
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188 } stc_flash_if_crtrmm_field_t;
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190 /******************************************************************************
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191 * Clock_Reset_MODULE
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192 ******************************************************************************/
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193 /* Clock_Reset_MODULE register bit fields */
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194 typedef struct stc_crg_scm_ctl_field
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196 uint8_t RESERVED1 : 1;
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197 __IO uint8_t MOSCE : 1;
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198 uint8_t RESERVED2 : 1;
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199 __IO uint8_t SOSCE : 1;
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200 __IO uint8_t PLLE : 1;
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201 __IO uint8_t RCS0 : 1;
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202 __IO uint8_t RCS1 : 1;
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203 __IO uint8_t RCS2 : 1;
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204 } stc_crg_scm_ctl_field_t;
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206 typedef struct stc_crg_scm_str_field
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208 uint8_t RESERVED1 : 1;
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209 __IO uint8_t MORDY : 1;
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210 uint8_t RESERVED2 : 1;
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211 __IO uint8_t SORDY : 1;
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212 __IO uint8_t PLRDY : 1;
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213 __IO uint8_t RCM0 : 1;
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214 __IO uint8_t RCM1 : 1;
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215 __IO uint8_t RCM2 : 1;
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216 } stc_crg_scm_str_field_t;
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218 typedef struct stc_crg_rst_str_field
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220 __IO uint16_t PONR : 1;
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221 __IO uint16_t INITX : 1;
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222 uint16_t RESERVED1 : 2;
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223 __IO uint16_t SWDT : 1;
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224 __IO uint16_t HWDT : 1;
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225 __IO uint16_t CSVR : 1;
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226 __IO uint16_t FCSR : 1;
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227 __IO uint16_t SRST : 1;
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228 } stc_crg_rst_str_field_t;
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230 typedef struct stc_crg_bsc_psr_field
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232 __IO uint8_t BSR0 : 1;
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233 __IO uint8_t BSR1 : 1;
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234 __IO uint8_t BSR2 : 1;
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235 } stc_crg_bsc_psr_field_t;
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237 typedef struct stc_crg_apbc0_psr_field
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239 __IO uint8_t APBC00 : 1;
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240 __IO uint8_t APBC01 : 1;
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241 } stc_crg_apbc0_psr_field_t;
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243 typedef struct stc_crg_apbc1_psr_field
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245 __IO uint8_t APBC10 : 1;
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246 __IO uint8_t APBC11 : 1;
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247 uint8_t RESERVED1 : 2;
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248 __IO uint8_t APBC1RST : 1;
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249 uint8_t RESERVED2 : 2;
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250 __IO uint8_t APBC1EN : 1;
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251 } stc_crg_apbc1_psr_field_t;
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253 typedef struct stc_crg_apbc2_psr_field
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255 __IO uint8_t APBC20 : 1;
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256 __IO uint8_t APBC21 : 1;
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257 uint8_t RESERVED1 : 2;
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258 __IO uint8_t APBC2RST : 1;
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259 uint8_t RESERVED2 : 2;
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260 __IO uint8_t APBC2EN : 1;
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261 } stc_crg_apbc2_psr_field_t;
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263 typedef struct stc_crg_swc_psr_field
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265 __IO uint8_t SWDS0 : 1;
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266 __IO uint8_t SWDS1 : 1;
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267 uint8_t RESERVED1 : 5;
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268 __IO uint8_t TESTB : 1;
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269 } stc_crg_swc_psr_field_t;
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271 typedef struct stc_crg_ttc_psr_field
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273 __IO uint8_t TTC : 1;
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274 } stc_crg_ttc_psr_field_t;
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276 typedef struct stc_crg_csw_tmr_field
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278 __IO uint8_t MOWT0 : 1;
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279 __IO uint8_t MOWT1 : 1;
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280 __IO uint8_t MOWT2 : 1;
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281 __IO uint8_t MOWT3 : 1;
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282 __IO uint8_t SOWT0 : 1;
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283 __IO uint8_t SOWT1 : 1;
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284 __IO uint8_t SOWT2 : 1;
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285 } stc_crg_csw_tmr_field_t;
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287 typedef struct stc_crg_psw_tmr_field
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289 __IO uint8_t POWT0 : 1;
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290 __IO uint8_t POWT1 : 1;
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291 __IO uint8_t POWT2 : 1;
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292 uint8_t RESERVED1 : 1;
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293 __IO uint8_t PINC : 1;
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294 } stc_crg_psw_tmr_field_t;
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296 typedef struct stc_crg_pll_ctl1_field
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298 __IO uint8_t PLLM0 : 1;
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299 __IO uint8_t PLLM1 : 1;
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300 __IO uint8_t PLLM2 : 1;
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301 __IO uint8_t PLLM3 : 1;
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302 __IO uint8_t PLLK0 : 1;
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303 __IO uint8_t PLLK1 : 1;
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304 __IO uint8_t PLLK2 : 1;
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305 __IO uint8_t PLLK3 : 1;
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306 } stc_crg_pll_ctl1_field_t;
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308 typedef struct stc_crg_pll_ctl2_field
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310 __IO uint8_t PLLN0 : 1;
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311 __IO uint8_t PLLN1 : 1;
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312 __IO uint8_t PLLN2 : 1;
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313 __IO uint8_t PLLN3 : 1;
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314 __IO uint8_t PLLN4 : 1;
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315 __IO uint8_t PLLN5 : 1;
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316 } stc_crg_pll_ctl2_field_t;
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318 typedef struct stc_crg_csv_ctl_field
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320 __IO uint16_t MCSVE : 1;
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321 __IO uint16_t SCSVE : 1;
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322 uint16_t RESERVED1 : 6;
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323 __IO uint16_t FCSDE : 1;
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324 __IO uint16_t FCSRE : 1;
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325 uint16_t RESERVED2 : 2;
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326 __IO uint16_t FCD0 : 1;
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327 __IO uint16_t FCD1 : 1;
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328 __IO uint16_t FCD2 : 1;
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329 } stc_crg_csv_ctl_field_t;
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331 typedef struct stc_crg_csv_str_field
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333 __IO uint8_t MCMF : 1;
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334 __IO uint8_t SCMF : 1;
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335 } stc_crg_csv_str_field_t;
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337 typedef struct stc_crg_dbwdt_ctl_field
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339 uint8_t RESERVED1 : 5;
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340 __IO uint8_t DPSWBE : 1;
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341 uint8_t RESERVED2 : 1;
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342 __IO uint8_t DPHWBE : 1;
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343 } stc_crg_dbwdt_ctl_field_t;
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345 typedef struct stc_crg_int_enr_field
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347 __IO uint8_t MCSE : 1;
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348 __IO uint8_t SCSE : 1;
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349 __IO uint8_t PCSE : 1;
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350 uint8_t RESERVED1 : 2;
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351 __IO uint8_t FCSE : 1;
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352 } stc_crg_int_enr_field_t;
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354 typedef struct stc_crg_int_str_field
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356 __IO uint8_t MCSI : 1;
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357 __IO uint8_t SCSI : 1;
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358 __IO uint8_t PCSI : 1;
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359 uint8_t RESERVED1 : 2;
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360 __IO uint8_t FCSI : 1;
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361 } stc_crg_int_str_field_t;
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363 typedef struct stc_crg_int_clr_field
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365 __IO uint8_t MCSC : 1;
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366 __IO uint8_t SCSC : 1;
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367 __IO uint8_t PCSC : 1;
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368 uint8_t RESERVED1 : 2;
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369 __IO uint8_t FCSC : 1;
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370 } stc_crg_int_clr_field_t;
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372 /******************************************************************************
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374 ******************************************************************************/
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375 /* HWWDT_MODULE register bit fields */
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376 typedef struct stc_hwwdt_wdg_ctl_field
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378 __IO uint8_t INTEN : 1;
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379 __IO uint8_t RESEN : 1;
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380 } stc_hwwdt_wdg_ctl_field_t;
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382 typedef struct stc_hwwdt_wdg_ris_field
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384 __IO uint8_t RIS : 1;
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385 } stc_hwwdt_wdg_ris_field_t;
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387 /******************************************************************************
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389 ******************************************************************************/
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390 /* SWWDT_MODULE register bit fields */
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391 typedef struct stc_swwdt_wdogcontrol_field
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393 __IO uint8_t INTEN : 1;
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394 __IO uint8_t RESEN : 1;
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395 } stc_swwdt_wdogcontrol_field_t;
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397 typedef struct stc_swwdt_wdogris_field
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399 __IO uint8_t RIS : 1;
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400 } stc_swwdt_wdogris_field_t;
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402 /******************************************************************************
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404 ******************************************************************************/
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405 /* DTIM_MODULE register bit fields */
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406 typedef struct stc_dtim_timer1control_field
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408 __IO uint32_t ONESHOT : 1;
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409 __IO uint32_t TIMERSIZE : 1;
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410 __IO uint32_t TIMERPRE0 : 1;
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411 __IO uint32_t TIMERPRE1 : 1;
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412 uint32_t RESERVED1 : 1;
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413 __IO uint32_t INTENABLE : 1;
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414 __IO uint32_t TIMERMODE : 1;
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415 __IO uint32_t TIMEREN : 1;
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416 } stc_dtim_timer1control_field_t;
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418 typedef struct stc_dtim_timer1ris_field
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420 __IO uint32_t TIMERXRIS : 1;
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421 } stc_dtim_timer1ris_field_t;
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423 typedef struct stc_dtim_timer1mis_field
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425 __IO uint32_t TIMERXRIS : 1;
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426 } stc_dtim_timer1mis_field_t;
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428 typedef struct stc_dtim_timer2control_field
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430 __IO uint32_t ONESHOT : 1;
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431 __IO uint32_t TIMERSIZE : 1;
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432 __IO uint32_t TIMERPRE0 : 1;
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433 __IO uint32_t TIMERPRE1 : 1;
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434 uint32_t RESERVED1 : 1;
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435 __IO uint32_t INTENABLE : 1;
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436 __IO uint32_t TIMERMODE : 1;
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437 __IO uint32_t TIMEREN : 1;
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438 } stc_dtim_timer2control_field_t;
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440 typedef struct stc_dtim_timer2ris_field
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442 __IO uint32_t TIMERXRIS : 1;
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443 } stc_dtim_timer2ris_field_t;
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445 typedef struct stc_dtim_timer2mis_field
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447 __IO uint32_t TIMERXRIS : 1;
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448 } stc_dtim_timer2mis_field_t;
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450 /******************************************************************************
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452 ******************************************************************************/
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453 /* MFT_FRT_MODULE register bit fields */
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454 typedef struct stc_mft_frt_tcsa0_field
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456 __IO uint16_t CLK0 : 1;
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457 __IO uint16_t CLK1 : 1;
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458 __IO uint16_t CLK2 : 1;
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459 __IO uint16_t CLK3 : 1;
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460 __IO uint16_t SCLR : 1;
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461 __IO uint16_t MODE : 1;
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462 __IO uint16_t STOP : 1;
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463 __IO uint16_t BFE : 1;
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464 __IO uint16_t ICRE : 1;
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465 __IO uint16_t ICLR : 1;
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466 uint16_t RESERVED1 : 3;
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467 __IO uint16_t IRQZE : 1;
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468 __IO uint16_t IRQZF : 1;
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469 __IO uint16_t ECKE : 1;
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470 } stc_mft_frt_tcsa0_field_t;
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472 typedef struct stc_mft_frt_tcsb0_field
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474 __IO uint16_t AD0E : 1;
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475 __IO uint16_t AD1E : 1;
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476 __IO uint16_t AD2E : 1;
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477 } stc_mft_frt_tcsb0_field_t;
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479 typedef struct stc_mft_frt_tcsa1_field
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481 __IO uint16_t CLK0 : 1;
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482 __IO uint16_t CLK1 : 1;
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483 __IO uint16_t CLK2 : 1;
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484 __IO uint16_t CLK3 : 1;
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485 __IO uint16_t SCLR : 1;
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486 __IO uint16_t MODE : 1;
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487 __IO uint16_t STOP : 1;
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488 __IO uint16_t BFE : 1;
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489 __IO uint16_t ICRE : 1;
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490 __IO uint16_t ICLR : 1;
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491 uint16_t RESERVED1 : 3;
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492 __IO uint16_t IRQZE : 1;
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493 __IO uint16_t IRQZF : 1;
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494 __IO uint16_t ECKE : 1;
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495 } stc_mft_frt_tcsa1_field_t;
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497 typedef struct stc_mft_frt_tcsb1_field
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499 __IO uint16_t AD0E : 1;
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500 __IO uint16_t AD1E : 1;
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501 __IO uint16_t AD2E : 1;
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502 } stc_mft_frt_tcsb1_field_t;
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504 typedef struct stc_mft_frt_tcsa2_field
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506 __IO uint16_t CLK0 : 1;
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507 __IO uint16_t CLK1 : 1;
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508 __IO uint16_t CLK2 : 1;
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509 __IO uint16_t CLK3 : 1;
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510 __IO uint16_t SCLR : 1;
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511 __IO uint16_t MODE : 1;
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512 __IO uint16_t STOP : 1;
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513 __IO uint16_t BFE : 1;
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514 __IO uint16_t ICRE : 1;
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515 __IO uint16_t ICLR : 1;
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516 uint16_t RESERVED1 : 3;
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517 __IO uint16_t IRQZE : 1;
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518 __IO uint16_t IRQZF : 1;
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519 __IO uint16_t ECKE : 1;
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520 } stc_mft_frt_tcsa2_field_t;
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522 typedef struct stc_mft_frt_tcsb2_field
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524 __IO uint16_t AD0E : 1;
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525 __IO uint16_t AD1E : 1;
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526 __IO uint16_t AD2E : 1;
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527 } stc_mft_frt_tcsb2_field_t;
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529 /******************************************************************************
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531 ******************************************************************************/
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532 /* MFT_OCU_MODULE register bit fields */
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533 typedef struct stc_mft_ocu_ocsa10_field
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535 __IO uint8_t CST0 : 1;
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536 __IO uint8_t CST1 : 1;
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537 __IO uint8_t BDIS0 : 1;
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538 __IO uint8_t BDIS1 : 1;
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539 __IO uint8_t IOE0 : 1;
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540 __IO uint8_t IOE1 : 1;
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541 __IO uint8_t IOP0 : 1;
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542 __IO uint8_t IOP1 : 1;
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543 } stc_mft_ocu_ocsa10_field_t;
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545 typedef struct stc_mft_ocu_ocsb10_field
\r
547 __IO uint8_t OTD0 : 1;
\r
548 __IO uint8_t OTD1 : 1;
\r
549 uint8_t RESERVED1 : 2;
\r
550 __IO uint8_t CMOD : 1;
\r
551 __IO uint8_t BTS0 : 1;
\r
552 __IO uint8_t BTS1 : 1;
\r
553 } stc_mft_ocu_ocsb10_field_t;
\r
555 typedef struct stc_mft_ocu_ocsa32_field
\r
557 __IO uint8_t CST2 : 1;
\r
558 __IO uint8_t CST3 : 1;
\r
559 __IO uint8_t BDIS2 : 1;
\r
560 __IO uint8_t BDIS3 : 1;
\r
561 __IO uint8_t IOE2 : 1;
\r
562 __IO uint8_t IOE3 : 1;
\r
563 __IO uint8_t IOP2 : 1;
\r
564 __IO uint8_t IOP3 : 1;
\r
565 } stc_mft_ocu_ocsa32_field_t;
\r
567 typedef struct stc_mft_ocu_ocsb32_field
\r
569 __IO uint8_t OTD2 : 1;
\r
570 __IO uint8_t OTD3 : 1;
\r
571 uint8_t RESERVED1 : 2;
\r
572 __IO uint8_t CMOD : 1;
\r
573 __IO uint8_t BTS2 : 1;
\r
574 __IO uint8_t BTS3 : 1;
\r
575 } stc_mft_ocu_ocsb32_field_t;
\r
577 typedef struct stc_mft_ocu_ocsa54_field
\r
579 __IO uint8_t CST4 : 1;
\r
580 __IO uint8_t CST5 : 1;
\r
581 __IO uint8_t BDIS4 : 1;
\r
582 __IO uint8_t BDIS5 : 1;
\r
583 __IO uint8_t IOE4 : 1;
\r
584 __IO uint8_t IOE5 : 1;
\r
585 __IO uint8_t IOP4 : 1;
\r
586 __IO uint8_t IOP5 : 1;
\r
587 } stc_mft_ocu_ocsa54_field_t;
\r
589 typedef struct stc_mft_ocu_ocsb54_field
\r
591 __IO uint8_t OTD4 : 1;
\r
592 __IO uint8_t OTD5 : 1;
\r
593 uint8_t RESERVED1 : 2;
\r
594 __IO uint8_t CMOD : 1;
\r
595 __IO uint8_t BTS4 : 1;
\r
596 __IO uint8_t BTS5 : 1;
\r
597 } stc_mft_ocu_ocsb54_field_t;
\r
599 typedef struct stc_mft_ocu_ocsc_field
\r
601 __IO uint8_t MOD0 : 1;
\r
602 __IO uint8_t MOD1 : 1;
\r
603 __IO uint8_t MOD2 : 1;
\r
604 __IO uint8_t MOD3 : 1;
\r
605 __IO uint8_t MOD4 : 1;
\r
606 __IO uint8_t MOD5 : 1;
\r
607 } stc_mft_ocu_ocsc_field_t;
\r
609 typedef struct stc_mft_ocu_ocfs10_field
\r
611 __IO uint8_t FSO00 : 1;
\r
612 __IO uint8_t FSO01 : 1;
\r
613 __IO uint8_t FSO02 : 1;
\r
614 __IO uint8_t FSO03 : 1;
\r
615 __IO uint8_t FSO10 : 1;
\r
616 __IO uint8_t FSO11 : 1;
\r
617 __IO uint8_t FSO12 : 1;
\r
618 __IO uint8_t FSO13 : 1;
\r
619 } stc_mft_ocu_ocfs10_field_t;
\r
621 typedef struct stc_mft_ocu_ocfs32_field
\r
623 __IO uint8_t FSO20 : 1;
\r
624 __IO uint8_t FSO21 : 1;
\r
625 __IO uint8_t FSO22 : 1;
\r
626 __IO uint8_t FSO23 : 1;
\r
627 __IO uint8_t FSO30 : 1;
\r
628 __IO uint8_t FSO31 : 1;
\r
629 __IO uint8_t FSO32 : 1;
\r
630 __IO uint8_t FSO33 : 1;
\r
631 } stc_mft_ocu_ocfs32_field_t;
\r
633 typedef struct stc_mft_ocu_ocfs54_field
\r
635 __IO uint8_t FSO40 : 1;
\r
636 __IO uint8_t FSO41 : 1;
\r
637 __IO uint8_t FSO42 : 1;
\r
638 __IO uint8_t FSO43 : 1;
\r
639 __IO uint8_t FSO50 : 1;
\r
640 __IO uint8_t FSO51 : 1;
\r
641 __IO uint8_t FSO52 : 1;
\r
642 __IO uint8_t FSO53 : 1;
\r
643 } stc_mft_ocu_ocfs54_field_t;
\r
645 /******************************************************************************
\r
647 ******************************************************************************/
\r
648 /* MFT_WFG_MODULE register bit fields */
\r
649 typedef struct stc_mft_wfg_wfsa10_field
\r
651 __IO uint16_t DCK0 : 1;
\r
652 __IO uint16_t DCK1 : 1;
\r
653 __IO uint16_t DCK2 : 1;
\r
654 __IO uint16_t TMD0 : 1;
\r
655 __IO uint16_t TMD1 : 1;
\r
656 __IO uint16_t TMD2 : 1;
\r
657 __IO uint16_t GTEN0 : 1;
\r
658 __IO uint16_t GTEN1 : 1;
\r
659 __IO uint16_t PSEL0 : 1;
\r
660 __IO uint16_t PSEL1 : 1;
\r
661 __IO uint16_t PGEN0 : 1;
\r
662 __IO uint16_t PGEN1 : 1;
\r
663 __IO uint16_t DMOD : 1;
\r
664 } stc_mft_wfg_wfsa10_field_t;
\r
666 typedef struct stc_mft_wfg_wfsa32_field
\r
668 __IO uint16_t DCK0 : 1;
\r
669 __IO uint16_t DCK1 : 1;
\r
670 __IO uint16_t DCK2 : 1;
\r
671 __IO uint16_t TMD0 : 1;
\r
672 __IO uint16_t TMD1 : 1;
\r
673 __IO uint16_t TMD2 : 1;
\r
674 __IO uint16_t GTEN0 : 1;
\r
675 __IO uint16_t GTEN1 : 1;
\r
676 __IO uint16_t PSEL0 : 1;
\r
677 __IO uint16_t PSEL1 : 1;
\r
678 __IO uint16_t PGEN0 : 1;
\r
679 __IO uint16_t PGEN1 : 1;
\r
680 __IO uint16_t DMOD : 1;
\r
681 } stc_mft_wfg_wfsa32_field_t;
\r
683 typedef struct stc_mft_wfg_wfsa54_field
\r
685 __IO uint16_t DCK0 : 1;
\r
686 __IO uint16_t DCK1 : 1;
\r
687 __IO uint16_t DCK2 : 1;
\r
688 __IO uint16_t TMD0 : 1;
\r
689 __IO uint16_t TMD1 : 1;
\r
690 __IO uint16_t TMD2 : 1;
\r
691 __IO uint16_t GTEN0 : 1;
\r
692 __IO uint16_t GTEN1 : 1;
\r
693 __IO uint16_t PSEL0 : 1;
\r
694 __IO uint16_t PSEL1 : 1;
\r
695 __IO uint16_t PGEN0 : 1;
\r
696 __IO uint16_t PGEN1 : 1;
\r
697 __IO uint16_t DMOD : 1;
\r
698 } stc_mft_wfg_wfsa54_field_t;
\r
700 typedef struct stc_mft_wfg_wfir_field
\r
702 __IO uint16_t DTIF : 1;
\r
703 __IO uint16_t DTIC : 1;
\r
704 uint16_t RESERVED1 : 2;
\r
705 __IO uint16_t TMIF10 : 1;
\r
706 __IO uint16_t TMIC10 : 1;
\r
707 __IO uint16_t TMIE10 : 1;
\r
708 __IO uint16_t TMIS10 : 1;
\r
709 __IO uint16_t TMIF32 : 1;
\r
710 __IO uint16_t TMIC32 : 1;
\r
711 __IO uint16_t TMIE32 : 1;
\r
712 __IO uint16_t TMIS32 : 1;
\r
713 __IO uint16_t TMIF54 : 1;
\r
714 __IO uint16_t TMIC54 : 1;
\r
715 __IO uint16_t TMIE54 : 1;
\r
716 __IO uint16_t TMIS54 : 1;
\r
717 } stc_mft_wfg_wfir_field_t;
\r
719 typedef struct stc_mft_wfg_nzcl_field
\r
721 __IO uint16_t DTIE : 1;
\r
722 __IO uint16_t NWS0 : 1;
\r
723 __IO uint16_t NWS1 : 1;
\r
724 __IO uint16_t NWS2 : 1;
\r
725 __IO uint16_t SDTI : 1;
\r
726 } stc_mft_wfg_nzcl_field_t;
\r
728 /******************************************************************************
\r
730 ******************************************************************************/
\r
731 /* MFT_ICU_MODULE register bit fields */
\r
732 typedef struct stc_mft_icu_icfs10_field
\r
734 __IO uint8_t FSI00 : 1;
\r
735 __IO uint8_t FSI01 : 1;
\r
736 __IO uint8_t FSI02 : 1;
\r
737 __IO uint8_t FSI03 : 1;
\r
738 __IO uint8_t FSI10 : 1;
\r
739 __IO uint8_t FSI11 : 1;
\r
740 __IO uint8_t FSI12 : 1;
\r
741 __IO uint8_t FSI13 : 1;
\r
742 } stc_mft_icu_icfs10_field_t;
\r
744 typedef struct stc_mft_icu_icfs32_field
\r
746 __IO uint8_t FSI20 : 1;
\r
747 __IO uint8_t FSI21 : 1;
\r
748 __IO uint8_t FSI22 : 1;
\r
749 __IO uint8_t FSI23 : 1;
\r
750 __IO uint8_t FSI30 : 1;
\r
751 __IO uint8_t FSI31 : 1;
\r
752 __IO uint8_t FSI32 : 1;
\r
753 __IO uint8_t FSI33 : 1;
\r
754 } stc_mft_icu_icfs32_field_t;
\r
756 typedef struct stc_mft_icu_icsa10_field
\r
758 __IO uint8_t EG00 : 1;
\r
759 __IO uint8_t EG01 : 1;
\r
760 __IO uint8_t EG10 : 1;
\r
761 __IO uint8_t EG11 : 1;
\r
762 __IO uint8_t ICE0 : 1;
\r
763 __IO uint8_t ICE1 : 1;
\r
764 __IO uint8_t ICP0 : 1;
\r
765 __IO uint8_t ICP1 : 1;
\r
766 } stc_mft_icu_icsa10_field_t;
\r
768 typedef struct stc_mft_icu_icsb10_field
\r
770 __IO uint8_t IEI0 : 1;
\r
771 __IO uint8_t IEI1 : 1;
\r
772 } stc_mft_icu_icsb10_field_t;
\r
774 typedef struct stc_mft_icu_icsa32_field
\r
776 __IO uint8_t EG20 : 1;
\r
777 __IO uint8_t EG21 : 1;
\r
778 __IO uint8_t EG30 : 1;
\r
779 __IO uint8_t EG31 : 1;
\r
780 __IO uint8_t ICE2 : 1;
\r
781 __IO uint8_t ICE3 : 1;
\r
782 __IO uint8_t ICP2 : 1;
\r
783 __IO uint8_t ICP3 : 1;
\r
784 } stc_mft_icu_icsa32_field_t;
\r
786 typedef struct stc_mft_icu_icsb32_field
\r
788 __IO uint8_t IEI2 : 1;
\r
789 __IO uint8_t IEI3 : 1;
\r
790 } stc_mft_icu_icsb32_field_t;
\r
792 /******************************************************************************
\r
794 ******************************************************************************/
\r
795 /* MFT_ADCMP_MODULE register bit fields */
\r
796 typedef struct stc_mft_adcmp_acsb_field
\r
798 __IO uint8_t BDIS0 : 1;
\r
799 __IO uint8_t BDIS1 : 1;
\r
800 __IO uint8_t BDIS2 : 1;
\r
801 uint8_t RESERVED1 : 1;
\r
802 __IO uint8_t BTS0 : 1;
\r
803 __IO uint8_t BTS1 : 1;
\r
804 __IO uint8_t BTS2 : 1;
\r
805 } stc_mft_adcmp_acsb_field_t;
\r
807 typedef struct stc_mft_adcmp_acsa_field
\r
809 __IO uint16_t CE00 : 1;
\r
810 __IO uint16_t CE01 : 1;
\r
811 __IO uint16_t CE10 : 1;
\r
812 __IO uint16_t CE11 : 1;
\r
813 __IO uint16_t CE20 : 1;
\r
814 __IO uint16_t CE21 : 1;
\r
815 uint16_t RESERVED1 : 2;
\r
816 __IO uint16_t SEL00 : 1;
\r
817 __IO uint16_t SEL01 : 1;
\r
818 __IO uint16_t SEL10 : 1;
\r
819 __IO uint16_t SEL11 : 1;
\r
820 __IO uint16_t SEL20 : 1;
\r
821 __IO uint16_t SEL21 : 1;
\r
822 } stc_mft_adcmp_acsa_field_t;
\r
824 typedef struct stc_mft_adcmp_atsa_field
\r
826 __IO uint16_t AD0S0 : 1;
\r
827 __IO uint16_t AD0S1 : 1;
\r
828 __IO uint16_t AD1S0 : 1;
\r
829 __IO uint16_t AD1S1 : 1;
\r
830 __IO uint16_t AD2S0 : 1;
\r
831 __IO uint16_t AD2S1 : 1;
\r
832 uint16_t RESERVED1 : 2;
\r
833 __IO uint16_t AD0P0 : 1;
\r
834 __IO uint16_t AD0P1 : 1;
\r
835 __IO uint16_t AD1P0 : 1;
\r
836 __IO uint16_t AD1P1 : 1;
\r
837 __IO uint16_t AD2P0 : 1;
\r
838 __IO uint16_t AD2P1 : 1;
\r
839 } stc_mft_adcmp_atsa_field_t;
\r
841 /******************************************************************************
\r
843 ******************************************************************************/
\r
844 /* MFT_PPG_MODULE register bit fields */
\r
845 typedef struct stc_mft_ppg_ttcr0_field
\r
847 __IO uint8_t STR0 : 1;
\r
848 __IO uint8_t MONI0 : 1;
\r
849 __IO uint8_t CS00 : 1;
\r
850 __IO uint8_t CS01 : 1;
\r
851 __IO uint8_t TRG0O : 1;
\r
852 __IO uint8_t TRG2O : 1;
\r
853 __IO uint8_t TRG4O : 1;
\r
854 __IO uint8_t TRG6O : 1;
\r
855 } stc_mft_ppg_ttcr0_field_t;
\r
857 typedef struct stc_mft_ppg_ttcr1_field
\r
859 __IO uint8_t STR1 : 1;
\r
860 __IO uint8_t MONI1 : 1;
\r
861 __IO uint8_t CS10 : 1;
\r
862 __IO uint8_t CS11 : 1;
\r
863 __IO uint8_t TRG1O : 1;
\r
864 __IO uint8_t TRG3O : 1;
\r
865 __IO uint8_t TRG5O : 1;
\r
866 __IO uint8_t TRG7O : 1;
\r
867 } stc_mft_ppg_ttcr1_field_t;
\r
869 typedef struct stc_mft_ppg_trg_field
\r
871 __IO uint16_t PEN00 : 1;
\r
872 __IO uint16_t PEN01 : 1;
\r
873 __IO uint16_t PEN02 : 1;
\r
874 __IO uint16_t PEN03 : 1;
\r
875 __IO uint16_t PEN04 : 1;
\r
876 __IO uint16_t PEN05 : 1;
\r
877 __IO uint16_t PEN06 : 1;
\r
878 __IO uint16_t PEN07 : 1;
\r
879 __IO uint16_t PEN08 : 1;
\r
880 __IO uint16_t PEN09 : 1;
\r
881 __IO uint16_t PEN10 : 1;
\r
882 __IO uint16_t PEN11 : 1;
\r
883 __IO uint16_t PEN12 : 1;
\r
884 __IO uint16_t PEN13 : 1;
\r
885 __IO uint16_t PEN14 : 1;
\r
886 __IO uint16_t PEN15 : 1;
\r
887 } stc_mft_ppg_trg_field_t;
\r
889 typedef struct stc_mft_ppg_revc_field
\r
891 __IO uint16_t REV00 : 1;
\r
892 __IO uint16_t REV01 : 1;
\r
893 __IO uint16_t REV02 : 1;
\r
894 __IO uint16_t REV03 : 1;
\r
895 __IO uint16_t REV04 : 1;
\r
896 __IO uint16_t REV05 : 1;
\r
897 __IO uint16_t REV06 : 1;
\r
898 __IO uint16_t REV07 : 1;
\r
899 __IO uint16_t REV08 : 1;
\r
900 __IO uint16_t REV09 : 1;
\r
901 __IO uint16_t REV10 : 1;
\r
902 __IO uint16_t REV11 : 1;
\r
903 __IO uint16_t REV12 : 1;
\r
904 __IO uint16_t REV13 : 1;
\r
905 __IO uint16_t REV14 : 1;
\r
906 __IO uint16_t REV15 : 1;
\r
907 } stc_mft_ppg_revc_field_t;
\r
909 typedef struct stc_mft_ppg_ppgc1_field
\r
911 __IO uint8_t TTRG : 1;
\r
912 __IO uint8_t MD0 : 1;
\r
913 __IO uint8_t MD1 : 1;
\r
914 __IO uint8_t PCS0 : 1;
\r
915 __IO uint8_t PCS1 : 1;
\r
916 __IO uint8_t INTM : 1;
\r
917 __IO uint8_t PUF : 1;
\r
918 __IO uint8_t PIE : 1;
\r
919 } stc_mft_ppg_ppgc1_field_t;
\r
921 typedef struct stc_mft_ppg_ppgc0_field
\r
923 __IO uint8_t TTRG : 1;
\r
924 __IO uint8_t MD0 : 1;
\r
925 __IO uint8_t MD1 : 1;
\r
926 __IO uint8_t PCS0 : 1;
\r
927 __IO uint8_t PCS1 : 1;
\r
928 __IO uint8_t INTM : 1;
\r
929 __IO uint8_t PUF : 1;
\r
930 __IO uint8_t PIE : 1;
\r
931 } stc_mft_ppg_ppgc0_field_t;
\r
933 typedef struct stc_mft_ppg_ppgc3_field
\r
935 __IO uint8_t TTRG : 1;
\r
936 __IO uint8_t MD0 : 1;
\r
937 __IO uint8_t MD1 : 1;
\r
938 __IO uint8_t PCS0 : 1;
\r
939 __IO uint8_t PCS1 : 1;
\r
940 __IO uint8_t INTM : 1;
\r
941 __IO uint8_t PUF : 1;
\r
942 __IO uint8_t PIE : 1;
\r
943 } stc_mft_ppg_ppgc3_field_t;
\r
945 typedef struct stc_mft_ppg_ppgc2_field
\r
947 __IO uint8_t TTRG : 1;
\r
948 __IO uint8_t MD0 : 1;
\r
949 __IO uint8_t MD1 : 1;
\r
950 __IO uint8_t PCS0 : 1;
\r
951 __IO uint8_t PCS1 : 1;
\r
952 __IO uint8_t INTM : 1;
\r
953 __IO uint8_t PUF : 1;
\r
954 __IO uint8_t PIE : 1;
\r
955 } stc_mft_ppg_ppgc2_field_t;
\r
957 typedef struct stc_mft_ppg_gatec0_field
\r
959 __IO uint8_t EDGE0 : 1;
\r
960 __IO uint8_t STRG0 : 1;
\r
961 uint8_t RESERVED1 : 2;
\r
962 __IO uint8_t EDGE2 : 1;
\r
963 __IO uint8_t STRG2 : 1;
\r
964 } stc_mft_ppg_gatec0_field_t;
\r
966 typedef struct stc_mft_ppg_ppgc5_field
\r
968 __IO uint8_t TTRG : 1;
\r
969 __IO uint8_t MD0 : 1;
\r
970 __IO uint8_t MD1 : 1;
\r
971 __IO uint8_t PCS0 : 1;
\r
972 __IO uint8_t PCS1 : 1;
\r
973 __IO uint8_t INTM : 1;
\r
974 __IO uint8_t PUF : 1;
\r
975 __IO uint8_t PIE : 1;
\r
976 } stc_mft_ppg_ppgc5_field_t;
\r
978 typedef struct stc_mft_ppg_ppgc4_field
\r
980 __IO uint8_t TTRG : 1;
\r
981 __IO uint8_t MD0 : 1;
\r
982 __IO uint8_t MD1 : 1;
\r
983 __IO uint8_t PCS0 : 1;
\r
984 __IO uint8_t PCS1 : 1;
\r
985 __IO uint8_t INTM : 1;
\r
986 __IO uint8_t PUF : 1;
\r
987 __IO uint8_t PIE : 1;
\r
988 } stc_mft_ppg_ppgc4_field_t;
\r
990 typedef struct stc_mft_ppg_ppgc7_field
\r
992 __IO uint8_t TTRG : 1;
\r
993 __IO uint8_t MD0 : 1;
\r
994 __IO uint8_t MD1 : 1;
\r
995 __IO uint8_t PCS0 : 1;
\r
996 __IO uint8_t PCS1 : 1;
\r
997 __IO uint8_t INTM : 1;
\r
998 __IO uint8_t PUF : 1;
\r
999 __IO uint8_t PIE : 1;
\r
1000 } stc_mft_ppg_ppgc7_field_t;
\r
1002 typedef struct stc_mft_ppg_ppgc6_field
\r
1004 __IO uint8_t TTRG : 1;
\r
1005 __IO uint8_t MD0 : 1;
\r
1006 __IO uint8_t MD1 : 1;
\r
1007 __IO uint8_t PCS0 : 1;
\r
1008 __IO uint8_t PCS1 : 1;
\r
1009 __IO uint8_t INTM : 1;
\r
1010 __IO uint8_t PUF : 1;
\r
1011 __IO uint8_t PIE : 1;
\r
1012 } stc_mft_ppg_ppgc6_field_t;
\r
1014 typedef struct stc_mft_ppg_gatec4_field
\r
1016 __IO uint8_t EDGE4 : 1;
\r
1017 __IO uint8_t STRG4 : 1;
\r
1018 uint8_t RESERVED1 : 2;
\r
1019 __IO uint8_t EDGE6 : 1;
\r
1020 __IO uint8_t STRG6 : 1;
\r
1021 } stc_mft_ppg_gatec4_field_t;
\r
1023 typedef struct stc_mft_ppg_ppgc9_field
\r
1025 __IO uint8_t TTRG : 1;
\r
1026 __IO uint8_t MD0 : 1;
\r
1027 __IO uint8_t MD1 : 1;
\r
1028 __IO uint8_t PCS0 : 1;
\r
1029 __IO uint8_t PCS1 : 1;
\r
1030 __IO uint8_t INTM : 1;
\r
1031 __IO uint8_t PUF : 1;
\r
1032 __IO uint8_t PIE : 1;
\r
1033 } stc_mft_ppg_ppgc9_field_t;
\r
1035 typedef struct stc_mft_ppg_ppgc8_field
\r
1037 __IO uint8_t TTRG : 1;
\r
1038 __IO uint8_t MD0 : 1;
\r
1039 __IO uint8_t MD1 : 1;
\r
1040 __IO uint8_t PCS0 : 1;
\r
1041 __IO uint8_t PCS1 : 1;
\r
1042 __IO uint8_t INTM : 1;
\r
1043 __IO uint8_t PUF : 1;
\r
1044 __IO uint8_t PIE : 1;
\r
1045 } stc_mft_ppg_ppgc8_field_t;
\r
1047 typedef struct stc_mft_ppg_ppgc11_field
\r
1049 __IO uint8_t TTRG : 1;
\r
1050 __IO uint8_t MD0 : 1;
\r
1051 __IO uint8_t MD1 : 1;
\r
1052 __IO uint8_t PCS0 : 1;
\r
1053 __IO uint8_t PCS1 : 1;
\r
1054 __IO uint8_t INTM : 1;
\r
1055 __IO uint8_t PUF : 1;
\r
1056 __IO uint8_t PIE : 1;
\r
1057 } stc_mft_ppg_ppgc11_field_t;
\r
1059 typedef struct stc_mft_ppg_ppgc10_field
\r
1061 __IO uint8_t TTRG : 1;
\r
1062 __IO uint8_t MD0 : 1;
\r
1063 __IO uint8_t MD1 : 1;
\r
1064 __IO uint8_t PCS0 : 1;
\r
1065 __IO uint8_t PCS1 : 1;
\r
1066 __IO uint8_t INTM : 1;
\r
1067 __IO uint8_t PUF : 1;
\r
1068 __IO uint8_t PIE : 1;
\r
1069 } stc_mft_ppg_ppgc10_field_t;
\r
1071 typedef struct stc_mft_ppg_gatec8_field
\r
1073 __IO uint8_t EDGE8 : 1;
\r
1074 __IO uint8_t STRG8 : 1;
\r
1075 uint8_t RESERVED1 : 2;
\r
1076 __IO uint8_t EDGE10 : 1;
\r
1077 __IO uint8_t STRG10 : 1;
\r
1078 } stc_mft_ppg_gatec8_field_t;
\r
1080 typedef struct stc_mft_ppg_ppgc13_field
\r
1082 __IO uint8_t TTRG : 1;
\r
1083 __IO uint8_t MD0 : 1;
\r
1084 __IO uint8_t MD1 : 1;
\r
1085 __IO uint8_t PCS0 : 1;
\r
1086 __IO uint8_t PCS1 : 1;
\r
1087 __IO uint8_t INTM : 1;
\r
1088 __IO uint8_t PUF : 1;
\r
1089 __IO uint8_t PIE : 1;
\r
1090 } stc_mft_ppg_ppgc13_field_t;
\r
1092 typedef struct stc_mft_ppg_ppgc12_field
\r
1094 __IO uint8_t TTRG : 1;
\r
1095 __IO uint8_t MD0 : 1;
\r
1096 __IO uint8_t MD1 : 1;
\r
1097 __IO uint8_t PCS0 : 1;
\r
1098 __IO uint8_t PCS1 : 1;
\r
1099 __IO uint8_t INTM : 1;
\r
1100 __IO uint8_t PUF : 1;
\r
1101 __IO uint8_t PIE : 1;
\r
1102 } stc_mft_ppg_ppgc12_field_t;
\r
1104 typedef struct stc_mft_ppg_ppgc15_field
\r
1106 __IO uint8_t TTRG : 1;
\r
1107 __IO uint8_t MD0 : 1;
\r
1108 __IO uint8_t MD1 : 1;
\r
1109 __IO uint8_t PCS0 : 1;
\r
1110 __IO uint8_t PCS1 : 1;
\r
1111 __IO uint8_t INTM : 1;
\r
1112 __IO uint8_t PUF : 1;
\r
1113 __IO uint8_t PIE : 1;
\r
1114 } stc_mft_ppg_ppgc15_field_t;
\r
1116 typedef struct stc_mft_ppg_ppgc14_field
\r
1118 __IO uint8_t TTRG : 1;
\r
1119 __IO uint8_t MD0 : 1;
\r
1120 __IO uint8_t MD1 : 1;
\r
1121 __IO uint8_t PCS0 : 1;
\r
1122 __IO uint8_t PCS1 : 1;
\r
1123 __IO uint8_t INTM : 1;
\r
1124 __IO uint8_t PUF : 1;
\r
1125 __IO uint8_t PIE : 1;
\r
1126 } stc_mft_ppg_ppgc14_field_t;
\r
1128 typedef struct stc_mft_ppg_gatec12_field
\r
1130 __IO uint8_t EDGE12 : 1;
\r
1131 __IO uint8_t STRG12 : 1;
\r
1132 uint8_t RESERVED1 : 2;
\r
1133 __IO uint8_t EDGE14 : 1;
\r
1134 __IO uint8_t STRG14 : 1;
\r
1135 } stc_mft_ppg_gatec12_field_t;
\r
1137 /******************************************************************************
\r
1139 ******************************************************************************/
\r
1140 /* BT_PPG_MODULE register bit fields */
\r
1141 typedef struct stc_bt_ppg_tmcr_field
\r
1143 __IO uint16_t STRG : 1;
\r
1144 __IO uint16_t CTEN : 1;
\r
1145 __IO uint16_t MDSE : 1;
\r
1146 __IO uint16_t OSEL : 1;
\r
1147 __IO uint16_t FMD0 : 1;
\r
1148 __IO uint16_t FMD1 : 1;
\r
1149 __IO uint16_t FMD2 : 1;
\r
1150 uint16_t RESERVED1 : 1;
\r
1151 __IO uint16_t EGS0 : 1;
\r
1152 __IO uint16_t EGS1 : 1;
\r
1153 __IO uint16_t PMSK : 1;
\r
1154 __IO uint16_t RTGEN : 1;
\r
1155 __IO uint16_t CKS0 : 1;
\r
1156 __IO uint16_t CKS1 : 1;
\r
1157 __IO uint16_t CKS2 : 1;
\r
1158 } stc_bt_ppg_tmcr_field_t;
\r
1160 typedef struct stc_bt_ppg_stc_field
\r
1162 __IO uint8_t UDIR : 1;
\r
1163 uint8_t RESERVED1 : 1;
\r
1164 __IO uint8_t TGIR : 1;
\r
1165 uint8_t RESERVED2 : 1;
\r
1166 __IO uint8_t UDIE : 1;
\r
1167 uint8_t RESERVED3 : 1;
\r
1168 __IO uint8_t TGIE : 1;
\r
1169 } stc_bt_ppg_stc_field_t;
\r
1171 typedef struct stc_bt_ppg_tmcr2_field
\r
1173 __IO uint8_t CKS3 : 1;
\r
1174 } stc_bt_ppg_tmcr2_field_t;
\r
1176 /******************************************************************************
\r
1178 ******************************************************************************/
\r
1179 /* BT_PWM_MODULE register bit fields */
\r
1180 typedef struct stc_bt_pwm_tmcr_field
\r
1182 __IO uint16_t STRG : 1;
\r
1183 __IO uint16_t CTEN : 1;
\r
1184 __IO uint16_t MDSE : 1;
\r
1185 __IO uint16_t OSEL : 1;
\r
1186 __IO uint16_t FMD0 : 1;
\r
1187 __IO uint16_t FMD1 : 1;
\r
1188 __IO uint16_t FMD2 : 1;
\r
1189 uint16_t RESERVED1 : 1;
\r
1190 __IO uint16_t EGS0 : 1;
\r
1191 __IO uint16_t EGS1 : 1;
\r
1192 __IO uint16_t PMSK : 1;
\r
1193 __IO uint16_t RTGEN : 1;
\r
1194 __IO uint16_t CKS0 : 1;
\r
1195 __IO uint16_t CKS1 : 1;
\r
1196 __IO uint16_t CKS2 : 1;
\r
1197 } stc_bt_pwm_tmcr_field_t;
\r
1199 typedef struct stc_bt_pwm_stc_field
\r
1201 __IO uint8_t UDIR : 1;
\r
1202 __IO uint8_t DTIR : 1;
\r
1203 __IO uint8_t TGIR : 1;
\r
1204 uint8_t RESERVED1 : 1;
\r
1205 __IO uint8_t UDIE : 1;
\r
1206 __IO uint8_t DTIE : 1;
\r
1207 __IO uint8_t TGIE : 1;
\r
1208 } stc_bt_pwm_stc_field_t;
\r
1210 typedef struct stc_bt_pwm_tmcr2_field
\r
1212 __IO uint8_t CKS3 : 1;
\r
1213 } stc_bt_pwm_tmcr2_field_t;
\r
1215 /******************************************************************************
\r
1217 ******************************************************************************/
\r
1218 /* BT_RT_MODULE register bit fields */
\r
1219 typedef struct stc_bt_rt_tmcr_field
\r
1221 __IO uint16_t STRG : 1;
\r
1222 __IO uint16_t CTEN : 1;
\r
1223 __IO uint16_t MDSE : 1;
\r
1224 __IO uint16_t OSEL : 1;
\r
1225 __IO uint16_t FMD0 : 1;
\r
1226 __IO uint16_t FMD1 : 1;
\r
1227 __IO uint16_t FMD2 : 1;
\r
1228 __IO uint16_t T32 : 1;
\r
1229 __IO uint16_t EGS0 : 1;
\r
1230 __IO uint16_t EGS1 : 1;
\r
1231 uint16_t RESERVED1 : 2;
\r
1232 __IO uint16_t CKS0 : 1;
\r
1233 __IO uint16_t CKS1 : 1;
\r
1234 __IO uint16_t CKS2 : 1;
\r
1235 } stc_bt_rt_tmcr_field_t;
\r
1237 typedef struct stc_bt_rt_stc_field
\r
1239 __IO uint8_t UDIR : 1;
\r
1240 uint8_t RESERVED1 : 1;
\r
1241 __IO uint8_t TGIR : 1;
\r
1242 uint8_t RESERVED2 : 1;
\r
1243 __IO uint8_t UDIE : 1;
\r
1244 uint8_t RESERVED3 : 1;
\r
1245 __IO uint8_t TGIE : 1;
\r
1246 } stc_bt_rt_stc_field_t;
\r
1248 typedef struct stc_bt_rt_tmcr2_field
\r
1250 __IO uint8_t CKS3 : 1;
\r
1251 } stc_bt_rt_tmcr2_field_t;
\r
1253 /******************************************************************************
\r
1255 ******************************************************************************/
\r
1256 /* BT_PWC_MODULE register bit fields */
\r
1257 typedef struct stc_bt_pwc_tmcr_field
\r
1259 uint16_t RESERVED1 : 1;
\r
1260 __IO uint16_t CTEN : 1;
\r
1261 __IO uint16_t MDSE : 1;
\r
1262 uint16_t RESERVED2 : 1;
\r
1263 __IO uint16_t FMD0 : 1;
\r
1264 __IO uint16_t FMD1 : 1;
\r
1265 __IO uint16_t FMD2 : 1;
\r
1266 __IO uint16_t T32 : 1;
\r
1267 __IO uint16_t EGS0 : 1;
\r
1268 __IO uint16_t EGS1 : 1;
\r
1269 __IO uint16_t EGS2 : 1;
\r
1270 uint16_t RESERVED3 : 1;
\r
1271 __IO uint16_t CKS0 : 1;
\r
1272 __IO uint16_t CKS1 : 1;
\r
1273 __IO uint16_t CKS2 : 1;
\r
1274 } stc_bt_pwc_tmcr_field_t;
\r
1276 typedef struct stc_bt_pwc_stc_field
\r
1278 __IO uint8_t OVIR : 1;
\r
1279 uint8_t RESERVED1 : 1;
\r
1280 __IO uint8_t EDIR : 1;
\r
1281 uint8_t RESERVED2 : 1;
\r
1282 __IO uint8_t OVIE : 1;
\r
1283 uint8_t RESERVED3 : 1;
\r
1284 __IO uint8_t EDIE : 1;
\r
1285 __IO uint8_t ERR : 1;
\r
1286 } stc_bt_pwc_stc_field_t;
\r
1288 typedef struct stc_bt_pwc_tmcr2_field
\r
1290 __IO uint8_t CKS3 : 1;
\r
1291 } stc_bt_pwc_tmcr2_field_t;
\r
1293 /******************************************************************************
\r
1294 * BTIOSEL03_MODULE
\r
1295 ******************************************************************************/
\r
1296 /* BTIOSEL03_MODULE register bit fields */
\r
1297 typedef struct stc_btiosel03_btsel0123_field
\r
1299 __IO uint8_t SEL01_0 : 1;
\r
1300 __IO uint8_t SEL01_1 : 1;
\r
1301 __IO uint8_t SEL01_2 : 1;
\r
1302 __IO uint8_t SEL01_3 : 1;
\r
1303 __IO uint8_t SEL23_0 : 1;
\r
1304 __IO uint8_t SEL23_1 : 1;
\r
1305 __IO uint8_t SEL23_2 : 1;
\r
1306 __IO uint8_t SEL23_3 : 1;
\r
1307 } stc_btiosel03_btsel0123_field_t;
\r
1309 /******************************************************************************
\r
1310 * BTIOSEL47_MODULE
\r
1311 ******************************************************************************/
\r
1312 /* BTIOSEL47_MODULE register bit fields */
\r
1313 typedef struct stc_btiosel47_btsel4567_field
\r
1315 __IO uint8_t SEL45_0 : 1;
\r
1316 __IO uint8_t SEL45_1 : 1;
\r
1317 __IO uint8_t SEL45_2 : 1;
\r
1318 __IO uint8_t SEL45_3 : 1;
\r
1319 __IO uint8_t SEL67_0 : 1;
\r
1320 __IO uint8_t SEL67_1 : 1;
\r
1321 __IO uint8_t SEL67_2 : 1;
\r
1322 __IO uint8_t SEL67_3 : 1;
\r
1323 } stc_btiosel47_btsel4567_field_t;
\r
1325 /******************************************************************************
\r
1327 ******************************************************************************/
\r
1328 /* SBSSR_MODULE register bit fields */
\r
1329 typedef struct stc_sbssr_btsssr_field
\r
1331 __IO uint16_t SSR0 : 1;
\r
1332 __IO uint16_t SSR1 : 1;
\r
1333 __IO uint16_t SSR2 : 1;
\r
1334 __IO uint16_t SSR3 : 1;
\r
1335 __IO uint16_t SSR4 : 1;
\r
1336 __IO uint16_t SSR5 : 1;
\r
1337 __IO uint16_t SSR6 : 1;
\r
1338 __IO uint16_t SSR7 : 1;
\r
1339 __IO uint16_t SSR8 : 1;
\r
1340 __IO uint16_t SSR9 : 1;
\r
1341 __IO uint16_t SSR10 : 1;
\r
1342 __IO uint16_t SSR11 : 1;
\r
1343 __IO uint16_t SSR12 : 1;
\r
1344 __IO uint16_t SSR13 : 1;
\r
1345 __IO uint16_t SSR14 : 1;
\r
1346 __IO uint16_t SSR15 : 1;
\r
1347 } stc_sbssr_btsssr_field_t;
\r
1349 /******************************************************************************
\r
1351 ******************************************************************************/
\r
1352 /* QPRC_MODULE register bit fields */
\r
1353 typedef struct stc_qprc_qicr_field
\r
1355 __IO uint16_t QPCMIE : 1;
\r
1356 __IO uint16_t QPCMF : 1;
\r
1357 __IO uint16_t QPRCMIE : 1;
\r
1358 __IO uint16_t QPRCMF : 1;
\r
1359 __IO uint16_t OUZIE : 1;
\r
1360 __IO uint16_t UFDF : 1;
\r
1361 __IO uint16_t OFDF : 1;
\r
1362 __IO uint16_t ZIIF : 1;
\r
1363 __IO uint16_t CDCIE : 1;
\r
1364 __IO uint16_t CDCF : 1;
\r
1365 __IO uint16_t DIRPC : 1;
\r
1366 __IO uint16_t DIROU : 1;
\r
1367 __IO uint16_t QPCNRCMIE : 1;
\r
1368 __IO uint16_t QPCNRCMF : 1;
\r
1369 } stc_qprc_qicr_field_t;
\r
1371 typedef struct stc_qprc_qicrl_field
\r
1373 __IO uint8_t QPCMIE : 1;
\r
1374 __IO uint8_t QPCMF : 1;
\r
1375 __IO uint8_t QPRCMIE : 1;
\r
1376 __IO uint8_t QPRCMF : 1;
\r
1377 __IO uint8_t OUZIE : 1;
\r
1378 __IO uint8_t UFDF : 1;
\r
1379 __IO uint8_t OFDF : 1;
\r
1380 __IO uint8_t ZIIF : 1;
\r
1381 } stc_qprc_qicrl_field_t;
\r
1383 typedef struct stc_qprc_qicrh_field
\r
1385 __IO uint8_t CDCIE : 1;
\r
1386 __IO uint8_t CDCF : 1;
\r
1387 __IO uint8_t DIRPC : 1;
\r
1388 __IO uint8_t DIROU : 1;
\r
1389 __IO uint8_t QPCNRCMIE : 1;
\r
1390 __IO uint8_t QPCNRCMF : 1;
\r
1391 } stc_qprc_qicrh_field_t;
\r
1393 typedef struct stc_qprc_qcr_field
\r
1395 __IO uint16_t PCM0 : 1;
\r
1396 __IO uint16_t PCM1 : 1;
\r
1397 __IO uint16_t RCM0 : 1;
\r
1398 __IO uint16_t RCM1 : 1;
\r
1399 __IO uint16_t PSTP : 1;
\r
1400 __IO uint16_t CGSC : 1;
\r
1401 __IO uint16_t RSEL : 1;
\r
1402 __IO uint16_t SWAP : 1;
\r
1403 __IO uint16_t PCRM0 : 1;
\r
1404 __IO uint16_t PCRM1 : 1;
\r
1405 __IO uint16_t AES0 : 1;
\r
1406 __IO uint16_t AES1 : 1;
\r
1407 __IO uint16_t BES0 : 1;
\r
1408 __IO uint16_t BES1 : 1;
\r
1409 __IO uint16_t CGE0 : 1;
\r
1410 __IO uint16_t CGE1 : 1;
\r
1411 } stc_qprc_qcr_field_t;
\r
1413 typedef struct stc_qprc_qcrl_field
\r
1415 __IO uint8_t PCM0 : 1;
\r
1416 __IO uint8_t PCM1 : 1;
\r
1417 __IO uint8_t RCM0 : 1;
\r
1418 __IO uint8_t RCM1 : 1;
\r
1419 __IO uint8_t PSTP : 1;
\r
1420 __IO uint8_t CGSC : 1;
\r
1421 __IO uint8_t RSEL : 1;
\r
1422 __IO uint8_t SWAP : 1;
\r
1423 } stc_qprc_qcrl_field_t;
\r
1425 typedef struct stc_qprc_qcrh_field
\r
1427 __IO uint8_t PCRM0 : 1;
\r
1428 __IO uint8_t PCRM1 : 1;
\r
1429 __IO uint8_t AES0 : 1;
\r
1430 __IO uint8_t AES1 : 1;
\r
1431 __IO uint8_t BES0 : 1;
\r
1432 __IO uint8_t BES1 : 1;
\r
1433 __IO uint8_t CGE0 : 1;
\r
1434 __IO uint8_t CGE1 : 1;
\r
1435 } stc_qprc_qcrh_field_t;
\r
1437 typedef struct stc_qprc_qecr_field
\r
1439 __IO uint16_t ORNGMD : 1;
\r
1440 __IO uint16_t ORNGF : 1;
\r
1441 __IO uint16_t ORNGIE : 1;
\r
1442 } stc_qprc_qecr_field_t;
\r
1444 /******************************************************************************
\r
1446 ******************************************************************************/
\r
1447 /* ADC12_MODULE register bit fields */
\r
1448 typedef struct stc_adc_adsr_field
\r
1450 __IO uint8_t SCS : 1;
\r
1451 __IO uint8_t PCS : 1;
\r
1452 __IO uint8_t PCNS : 1;
\r
1453 uint8_t RESERVED1 : 3;
\r
1454 __IO uint8_t FDAS : 1;
\r
1455 __IO uint8_t ADSTP : 1;
\r
1456 } stc_adc_adsr_field_t;
\r
1458 typedef struct stc_adc_adcr_field
\r
1460 __IO uint8_t OVRIE : 1;
\r
1461 __IO uint8_t CMPIE : 1;
\r
1462 __IO uint8_t PCIE : 1;
\r
1463 __IO uint8_t SCIE : 1;
\r
1464 uint8_t RESERVED1 : 1;
\r
1465 __IO uint8_t CMPIF : 1;
\r
1466 __IO uint8_t PCIF : 1;
\r
1467 __IO uint8_t SCIF : 1;
\r
1468 } stc_adc_adcr_field_t;
\r
1470 typedef struct stc_adc_sfns_field
\r
1472 __IO uint8_t SFS0 : 1;
\r
1473 __IO uint8_t SFS1 : 1;
\r
1474 __IO uint8_t SFS2 : 1;
\r
1475 __IO uint8_t SFS3 : 1;
\r
1476 } stc_adc_sfns_field_t;
\r
1478 typedef struct stc_adc_sccr_field
\r
1480 __IO uint8_t SSTR : 1;
\r
1481 __IO uint8_t SHEN : 1;
\r
1482 __IO uint8_t RPT : 1;
\r
1483 uint8_t RESERVED1 : 1;
\r
1484 __IO uint8_t SFCLR : 1;
\r
1485 __IO uint8_t SOVR : 1;
\r
1486 __IO uint8_t SFUL : 1;
\r
1487 __IO uint8_t SEMP : 1;
\r
1488 } stc_adc_sccr_field_t;
\r
1490 typedef struct stc_adc_scfd_field
\r
1492 __IO uint32_t SC0 : 1;
\r
1493 __IO uint32_t SC1 : 1;
\r
1494 __IO uint32_t SC2 : 1;
\r
1495 __IO uint32_t SC3 : 1;
\r
1496 __IO uint32_t SC4 : 1;
\r
1497 uint32_t RESERVED1 : 3;
\r
1498 __IO uint32_t RS0 : 1;
\r
1499 __IO uint32_t RS1 : 1;
\r
1500 uint32_t RESERVED2 : 2;
\r
1501 __IO uint32_t INVL : 1;
\r
1502 uint32_t RESERVED3 : 7;
\r
1503 __IO uint32_t SD0 : 1;
\r
1504 __IO uint32_t SD1 : 1;
\r
1505 __IO uint32_t SD2 : 1;
\r
1506 __IO uint32_t SD3 : 1;
\r
1507 __IO uint32_t SD4 : 1;
\r
1508 __IO uint32_t SD5 : 1;
\r
1509 __IO uint32_t SD6 : 1;
\r
1510 __IO uint32_t SD7 : 1;
\r
1511 __IO uint32_t SD8 : 1;
\r
1512 __IO uint32_t SD9 : 1;
\r
1513 __IO uint32_t SD10 : 1;
\r
1514 __IO uint32_t SD11 : 1;
\r
1515 } stc_adc_scfd_field_t;
\r
1517 typedef struct stc_adc_scfdl_field
\r
1519 __IO uint16_t SC0 : 1;
\r
1520 __IO uint16_t SC1 : 1;
\r
1521 __IO uint16_t SC2 : 1;
\r
1522 __IO uint16_t SC3 : 1;
\r
1523 __IO uint16_t SC4 : 1;
\r
1524 uint16_t RESERVED1 : 3;
\r
1525 __IO uint16_t RS0 : 1;
\r
1526 __IO uint16_t RS1 : 1;
\r
1527 uint16_t RESERVED2 : 2;
\r
1528 __IO uint16_t INVL : 1;
\r
1529 } stc_adc_scfdl_field_t;
\r
1531 typedef struct stc_adc_scfdh_field
\r
1533 uint16_t RESERVED1 : 4;
\r
1534 __IO uint16_t SD0 : 1;
\r
1535 __IO uint16_t SD1 : 1;
\r
1536 __IO uint16_t SD2 : 1;
\r
1537 __IO uint16_t SD3 : 1;
\r
1538 __IO uint16_t SD4 : 1;
\r
1539 __IO uint16_t SD5 : 1;
\r
1540 __IO uint16_t SD6 : 1;
\r
1541 __IO uint16_t SD7 : 1;
\r
1542 __IO uint16_t SD8 : 1;
\r
1543 __IO uint16_t SD9 : 1;
\r
1544 __IO uint16_t SD10 : 1;
\r
1545 __IO uint16_t SD11 : 1;
\r
1546 } stc_adc_scfdh_field_t;
\r
1548 typedef struct stc_adc_scis23_field
\r
1550 __IO uint16_t AN16 : 1;
\r
1551 __IO uint16_t AN17 : 1;
\r
1552 __IO uint16_t AN18 : 1;
\r
1553 __IO uint16_t AN19 : 1;
\r
1554 __IO uint16_t AN20 : 1;
\r
1555 __IO uint16_t AN21 : 1;
\r
1556 __IO uint16_t AN22 : 1;
\r
1557 __IO uint16_t AN23 : 1;
\r
1558 __IO uint16_t AN24 : 1;
\r
1559 __IO uint16_t AN25 : 1;
\r
1560 __IO uint16_t AN26 : 1;
\r
1561 __IO uint16_t AN27 : 1;
\r
1562 __IO uint16_t AN28 : 1;
\r
1563 __IO uint16_t AN29 : 1;
\r
1564 __IO uint16_t AN30 : 1;
\r
1565 __IO uint16_t AN31 : 1;
\r
1566 } stc_adc_scis23_field_t;
\r
1568 typedef struct stc_adc_scis2_field
\r
1570 __IO uint8_t AN16 : 1;
\r
1571 __IO uint8_t AN17 : 1;
\r
1572 __IO uint8_t AN18 : 1;
\r
1573 __IO uint8_t AN19 : 1;
\r
1574 __IO uint8_t AN20 : 1;
\r
1575 __IO uint8_t AN21 : 1;
\r
1576 __IO uint8_t AN22 : 1;
\r
1577 __IO uint8_t AN23 : 1;
\r
1578 } stc_adc_scis2_field_t;
\r
1580 typedef struct stc_adc_scis3_field
\r
1582 __IO uint8_t AN24 : 1;
\r
1583 __IO uint8_t AN25 : 1;
\r
1584 __IO uint8_t AN26 : 1;
\r
1585 __IO uint8_t AN27 : 1;
\r
1586 __IO uint8_t AN28 : 1;
\r
1587 __IO uint8_t AN29 : 1;
\r
1588 __IO uint8_t AN30 : 1;
\r
1589 __IO uint8_t AN31 : 1;
\r
1590 } stc_adc_scis3_field_t;
\r
1592 typedef struct stc_adc_scis01_field
\r
1594 __IO uint16_t AN0 : 1;
\r
1595 __IO uint16_t AN1 : 1;
\r
1596 __IO uint16_t AN2 : 1;
\r
1597 __IO uint16_t AN3 : 1;
\r
1598 __IO uint16_t AN4 : 1;
\r
1599 __IO uint16_t AN5 : 1;
\r
1600 __IO uint16_t AN6 : 1;
\r
1601 __IO uint16_t AN7 : 1;
\r
1602 __IO uint16_t AN8 : 1;
\r
1603 __IO uint16_t AN9 : 1;
\r
1604 __IO uint16_t AN10 : 1;
\r
1605 __IO uint16_t AN11 : 1;
\r
1606 __IO uint16_t AN12 : 1;
\r
1607 __IO uint16_t AN13 : 1;
\r
1608 __IO uint16_t AN14 : 1;
\r
1609 __IO uint16_t AN15 : 1;
\r
1610 } stc_adc_scis01_field_t;
\r
1612 typedef struct stc_adc_scis0_field
\r
1614 __IO uint8_t AN0 : 1;
\r
1615 __IO uint8_t AN1 : 1;
\r
1616 __IO uint8_t AN2 : 1;
\r
1617 __IO uint8_t AN3 : 1;
\r
1618 __IO uint8_t AN4 : 1;
\r
1619 __IO uint8_t AN5 : 1;
\r
1620 __IO uint8_t AN6 : 1;
\r
1621 __IO uint8_t AN7 : 1;
\r
1622 } stc_adc_scis0_field_t;
\r
1624 typedef struct stc_adc_scis1_field
\r
1626 __IO uint8_t AN8 : 1;
\r
1627 __IO uint8_t AN9 : 1;
\r
1628 __IO uint8_t AN10 : 1;
\r
1629 __IO uint8_t AN11 : 1;
\r
1630 __IO uint8_t AN12 : 1;
\r
1631 __IO uint8_t AN13 : 1;
\r
1632 __IO uint8_t AN14 : 1;
\r
1633 __IO uint8_t AN15 : 1;
\r
1634 } stc_adc_scis1_field_t;
\r
1636 typedef struct stc_adc_pfns_field
\r
1638 __IO uint8_t PFS0 : 1;
\r
1639 __IO uint8_t PFS1 : 1;
\r
1640 uint8_t RESERVED1 : 2;
\r
1641 __IO uint8_t TEST0 : 1;
\r
1642 __IO uint8_t TEST1 : 1;
\r
1643 } stc_adc_pfns_field_t;
\r
1645 typedef struct stc_adc_pccr_field
\r
1647 __IO uint8_t PSTR : 1;
\r
1648 __IO uint8_t PHEN : 1;
\r
1649 __IO uint8_t PEEN : 1;
\r
1650 __IO uint8_t ESCE : 1;
\r
1651 __IO uint8_t PFCLR : 1;
\r
1652 __IO uint8_t POVR : 1;
\r
1653 __IO uint8_t PFUL : 1;
\r
1654 __IO uint8_t PEMP : 1;
\r
1655 } stc_adc_pccr_field_t;
\r
1657 typedef struct stc_adc_pcfd_field
\r
1659 __IO uint32_t PC0 : 1;
\r
1660 __IO uint32_t PC1 : 1;
\r
1661 __IO uint32_t PC2 : 1;
\r
1662 __IO uint32_t PC3 : 1;
\r
1663 __IO uint32_t PC4 : 1;
\r
1664 uint32_t RESERVED1 : 3;
\r
1665 __IO uint32_t RS0 : 1;
\r
1666 __IO uint32_t RS1 : 1;
\r
1667 __IO uint32_t RS2 : 1;
\r
1668 uint32_t RESERVED2 : 1;
\r
1669 __IO uint32_t INVL : 1;
\r
1670 uint32_t RESERVED3 : 7;
\r
1671 __IO uint32_t PD0 : 1;
\r
1672 __IO uint32_t PD1 : 1;
\r
1673 __IO uint32_t PD2 : 1;
\r
1674 __IO uint32_t PD3 : 1;
\r
1675 __IO uint32_t PD4 : 1;
\r
1676 __IO uint32_t PD5 : 1;
\r
1677 __IO uint32_t PD6 : 1;
\r
1678 __IO uint32_t PD7 : 1;
\r
1679 __IO uint32_t PD8 : 1;
\r
1680 __IO uint32_t PD9 : 1;
\r
1681 __IO uint32_t PD10 : 1;
\r
1682 __IO uint32_t PD11 : 1;
\r
1683 } stc_adc_pcfd_field_t;
\r
1685 typedef struct stc_adc_pcfdl_field
\r
1687 __IO uint16_t PC0 : 1;
\r
1688 __IO uint16_t PC1 : 1;
\r
1689 __IO uint16_t PC2 : 1;
\r
1690 __IO uint16_t PC3 : 1;
\r
1691 __IO uint16_t PC4 : 1;
\r
1692 uint16_t RESERVED1 : 3;
\r
1693 __IO uint16_t RS0 : 1;
\r
1694 __IO uint16_t RS1 : 1;
\r
1695 __IO uint16_t RS2 : 1;
\r
1696 uint16_t RESERVED2 : 1;
\r
1697 __IO uint16_t INVL : 1;
\r
1698 } stc_adc_pcfdl_field_t;
\r
1700 typedef struct stc_adc_pcfdh_field
\r
1702 uint16_t RESERVED1 : 4;
\r
1703 __IO uint16_t PD0 : 1;
\r
1704 __IO uint16_t PD1 : 1;
\r
1705 __IO uint16_t PD2 : 1;
\r
1706 __IO uint16_t PD3 : 1;
\r
1707 __IO uint16_t PD4 : 1;
\r
1708 __IO uint16_t PD5 : 1;
\r
1709 __IO uint16_t PD6 : 1;
\r
1710 __IO uint16_t PD7 : 1;
\r
1711 __IO uint16_t PD8 : 1;
\r
1712 __IO uint16_t PD9 : 1;
\r
1713 __IO uint16_t PD10 : 1;
\r
1714 __IO uint16_t PD11 : 1;
\r
1715 } stc_adc_pcfdh_field_t;
\r
1717 typedef struct stc_adc_pcis_field
\r
1719 __IO uint8_t P1A0 : 1;
\r
1720 __IO uint8_t P1A1 : 1;
\r
1721 __IO uint8_t P1A2 : 1;
\r
1722 __IO uint8_t P2A0 : 1;
\r
1723 __IO uint8_t P2A1 : 1;
\r
1724 __IO uint8_t P2A2 : 1;
\r
1725 __IO uint8_t P2A3 : 1;
\r
1726 __IO uint8_t P2A4 : 1;
\r
1727 } stc_adc_pcis_field_t;
\r
1729 typedef struct stc_adc_cmpcr_field
\r
1731 __IO uint8_t CCH0 : 1;
\r
1732 __IO uint8_t CCH1 : 1;
\r
1733 __IO uint8_t CCH2 : 1;
\r
1734 __IO uint8_t CCH3 : 1;
\r
1735 __IO uint8_t CCH4 : 1;
\r
1736 __IO uint8_t CMD0 : 1;
\r
1737 __IO uint8_t CMD1 : 1;
\r
1738 __IO uint8_t CMPEN : 1;
\r
1739 } stc_adc_cmpcr_field_t;
\r
1741 typedef struct stc_adc_cmpd_field
\r
1743 uint16_t RESERVED1 : 6;
\r
1744 __IO uint16_t CMAD2 : 1;
\r
1745 __IO uint16_t CMAD3 : 1;
\r
1746 __IO uint16_t CMAD4 : 1;
\r
1747 __IO uint16_t CMAD5 : 1;
\r
1748 __IO uint16_t CMAD6 : 1;
\r
1749 __IO uint16_t CMAD7 : 1;
\r
1750 __IO uint16_t CMAD8 : 1;
\r
1751 __IO uint16_t CMAD9 : 1;
\r
1752 __IO uint16_t CMAD10 : 1;
\r
1753 __IO uint16_t CMAD11 : 1;
\r
1754 } stc_adc_cmpd_field_t;
\r
1756 typedef struct stc_adc_adss23_field
\r
1758 __IO uint16_t TS16 : 1;
\r
1759 __IO uint16_t TS17 : 1;
\r
1760 __IO uint16_t TS18 : 1;
\r
1761 __IO uint16_t TS19 : 1;
\r
1762 __IO uint16_t TS20 : 1;
\r
1763 __IO uint16_t TS21 : 1;
\r
1764 __IO uint16_t TS22 : 1;
\r
1765 __IO uint16_t TS23 : 1;
\r
1766 __IO uint16_t TS24 : 1;
\r
1767 __IO uint16_t TS25 : 1;
\r
1768 __IO uint16_t TS26 : 1;
\r
1769 __IO uint16_t TS27 : 1;
\r
1770 __IO uint16_t TS28 : 1;
\r
1771 __IO uint16_t TS29 : 1;
\r
1772 __IO uint16_t TS30 : 1;
\r
1773 __IO uint16_t TS31 : 1;
\r
1774 } stc_adc_adss23_field_t;
\r
1776 typedef struct stc_adc_adss2_field
\r
1778 __IO uint8_t TS16 : 1;
\r
1779 __IO uint8_t TS17 : 1;
\r
1780 __IO uint8_t TS18 : 1;
\r
1781 __IO uint8_t TS19 : 1;
\r
1782 __IO uint8_t TS20 : 1;
\r
1783 __IO uint8_t TS21 : 1;
\r
1784 __IO uint8_t TS22 : 1;
\r
1785 __IO uint8_t TS23 : 1;
\r
1786 } stc_adc_adss2_field_t;
\r
1788 typedef struct stc_adc_adss3_field
\r
1790 __IO uint8_t TS24 : 1;
\r
1791 __IO uint8_t TS25 : 1;
\r
1792 __IO uint8_t TS26 : 1;
\r
1793 __IO uint8_t TS27 : 1;
\r
1794 __IO uint8_t TS28 : 1;
\r
1795 __IO uint8_t TS29 : 1;
\r
1796 __IO uint8_t TS30 : 1;
\r
1797 __IO uint8_t TS31 : 1;
\r
1798 } stc_adc_adss3_field_t;
\r
1800 typedef struct stc_adc_adss01_field
\r
1802 __IO uint16_t TS0 : 1;
\r
1803 __IO uint16_t TS1 : 1;
\r
1804 __IO uint16_t TS2 : 1;
\r
1805 __IO uint16_t TS3 : 1;
\r
1806 __IO uint16_t TS4 : 1;
\r
1807 __IO uint16_t TS5 : 1;
\r
1808 __IO uint16_t TS6 : 1;
\r
1809 __IO uint16_t TS7 : 1;
\r
1810 __IO uint16_t TS8 : 1;
\r
1811 __IO uint16_t TS9 : 1;
\r
1812 __IO uint16_t TS10 : 1;
\r
1813 __IO uint16_t TS11 : 1;
\r
1814 __IO uint16_t TS12 : 1;
\r
1815 __IO uint16_t TS13 : 1;
\r
1816 __IO uint16_t TS14 : 1;
\r
1817 __IO uint16_t TS15 : 1;
\r
1818 } stc_adc_adss01_field_t;
\r
1820 typedef struct stc_adc_adss0_field
\r
1822 __IO uint8_t TS0 : 1;
\r
1823 __IO uint8_t TS1 : 1;
\r
1824 __IO uint8_t TS2 : 1;
\r
1825 __IO uint8_t TS3 : 1;
\r
1826 __IO uint8_t TS4 : 1;
\r
1827 __IO uint8_t TS5 : 1;
\r
1828 __IO uint8_t TS6 : 1;
\r
1829 __IO uint8_t TS7 : 1;
\r
1830 } stc_adc_adss0_field_t;
\r
1832 typedef struct stc_adc_adss1_field
\r
1834 __IO uint8_t TS8 : 1;
\r
1835 __IO uint8_t TS9 : 1;
\r
1836 __IO uint8_t TS10 : 1;
\r
1837 __IO uint8_t TS11 : 1;
\r
1838 __IO uint8_t TS12 : 1;
\r
1839 __IO uint8_t TS13 : 1;
\r
1840 __IO uint8_t TS14 : 1;
\r
1841 __IO uint8_t TS15 : 1;
\r
1842 } stc_adc_adss1_field_t;
\r
1844 typedef struct stc_adc_adst01_field
\r
1846 __IO uint16_t ST10 : 1;
\r
1847 __IO uint16_t ST11 : 1;
\r
1848 __IO uint16_t ST12 : 1;
\r
1849 __IO uint16_t ST13 : 1;
\r
1850 __IO uint16_t ST14 : 1;
\r
1851 __IO uint16_t STX10 : 1;
\r
1852 __IO uint16_t STX11 : 1;
\r
1853 __IO uint16_t STX12 : 1;
\r
1854 __IO uint16_t ST00 : 1;
\r
1855 __IO uint16_t ST01 : 1;
\r
1856 __IO uint16_t ST02 : 1;
\r
1857 __IO uint16_t ST03 : 1;
\r
1858 __IO uint16_t ST04 : 1;
\r
1859 __IO uint16_t STX00 : 1;
\r
1860 __IO uint16_t STX01 : 1;
\r
1861 __IO uint16_t STX02 : 1;
\r
1862 } stc_adc_adst01_field_t;
\r
1864 typedef struct stc_adc_adst1_field
\r
1866 __IO uint8_t ST10 : 1;
\r
1867 __IO uint8_t ST11 : 1;
\r
1868 __IO uint8_t ST12 : 1;
\r
1869 __IO uint8_t ST13 : 1;
\r
1870 __IO uint8_t ST14 : 1;
\r
1871 __IO uint8_t STX10 : 1;
\r
1872 __IO uint8_t STX11 : 1;
\r
1873 __IO uint8_t STX12 : 1;
\r
1874 } stc_adc_adst1_field_t;
\r
1876 typedef struct stc_adc_adst0_field
\r
1878 __IO uint8_t ST00 : 1;
\r
1879 __IO uint8_t ST01 : 1;
\r
1880 __IO uint8_t ST02 : 1;
\r
1881 __IO uint8_t ST03 : 1;
\r
1882 __IO uint8_t ST04 : 1;
\r
1883 __IO uint8_t STX00 : 1;
\r
1884 __IO uint8_t STX01 : 1;
\r
1885 __IO uint8_t STX02 : 1;
\r
1886 } stc_adc_adst0_field_t;
\r
1888 typedef struct stc_adc_adct_field
\r
1890 __IO uint8_t CT0 : 1;
\r
1891 __IO uint8_t CT1 : 1;
\r
1892 __IO uint8_t CT2 : 1;
\r
1893 __IO uint8_t CT3 : 1;
\r
1894 __IO uint8_t CT4 : 1;
\r
1895 __IO uint8_t CT5 : 1;
\r
1896 __IO uint8_t CT6 : 1;
\r
1897 __IO uint8_t CT7 : 1;
\r
1898 } stc_adc_adct_field_t;
\r
1900 typedef struct stc_adc_prtsl_field
\r
1902 __IO uint8_t PRTSL0 : 1;
\r
1903 __IO uint8_t PRTSL1 : 1;
\r
1904 __IO uint8_t PRTSL2 : 1;
\r
1905 __IO uint8_t PRTSL3 : 1;
\r
1906 } stc_adc_prtsl_field_t;
\r
1908 typedef struct stc_adc_sctsl_field
\r
1910 __IO uint8_t SCTSL0 : 1;
\r
1911 __IO uint8_t SCTSL1 : 1;
\r
1912 __IO uint8_t SCTSL2 : 1;
\r
1913 __IO uint8_t SCTSL3 : 1;
\r
1914 } stc_adc_sctsl_field_t;
\r
1916 typedef struct stc_adc_adcen_field
\r
1918 __IO uint8_t ENBL : 1;
\r
1919 __IO uint8_t READY : 1;
\r
1920 uint8_t RESERVED1 : 2;
\r
1921 __IO uint8_t CYCLSL0 : 1;
\r
1922 __IO uint8_t CYCLSL1 : 1;
\r
1923 } stc_adc_adcen_field_t;
\r
1925 /******************************************************************************
\r
1927 ******************************************************************************/
\r
1928 /* CRTRIM_MODULE register bit fields */
\r
1929 typedef struct stc_crtrim_mcr_psr_field
\r
1931 __IO uint8_t CSR0 : 1;
\r
1932 __IO uint8_t CSR1 : 1;
\r
1933 } stc_crtrim_mcr_psr_field_t;
\r
1935 typedef struct stc_crtrim_mcr_ftrm_field
\r
1937 __IO uint16_t TRD0 : 1;
\r
1938 __IO uint16_t TRD1 : 1;
\r
1939 __IO uint16_t TRD2 : 1;
\r
1940 __IO uint16_t TRD3 : 1;
\r
1941 __IO uint16_t TRD4 : 1;
\r
1942 __IO uint16_t TRD5 : 1;
\r
1943 __IO uint16_t TRD6 : 1;
\r
1944 __IO uint16_t TRD7 : 1;
\r
1945 } stc_crtrim_mcr_ftrm_field_t;
\r
1947 /******************************************************************************
\r
1949 ******************************************************************************/
\r
1950 /* EXTI_MODULE register bit fields */
\r
1951 typedef struct stc_exti_enir_field
\r
1953 __IO uint16_t EN0 : 1;
\r
1954 __IO uint16_t EN1 : 1;
\r
1955 __IO uint16_t EN2 : 1;
\r
1956 __IO uint16_t EN3 : 1;
\r
1957 __IO uint16_t EN4 : 1;
\r
1958 __IO uint16_t EN5 : 1;
\r
1959 __IO uint16_t EN6 : 1;
\r
1960 __IO uint16_t EN7 : 1;
\r
1961 __IO uint16_t EN8 : 1;
\r
1962 uint16_t RESERVED1 : 5;
\r
1963 __IO uint16_t EN14 : 1;
\r
1964 __IO uint16_t EN15 : 1;
\r
1965 } stc_exti_enir_field_t;
\r
1967 typedef struct stc_exti_eirr_field
\r
1969 __IO uint16_t ER0 : 1;
\r
1970 __IO uint16_t ER1 : 1;
\r
1971 __IO uint16_t ER2 : 1;
\r
1972 __IO uint16_t ER3 : 1;
\r
1973 __IO uint16_t ER4 : 1;
\r
1974 __IO uint16_t ER5 : 1;
\r
1975 __IO uint16_t ER6 : 1;
\r
1976 __IO uint16_t ER7 : 1;
\r
1977 __IO uint16_t ER8 : 1;
\r
1978 uint16_t RESERVED1 : 5;
\r
1979 __IO uint16_t ER14 : 1;
\r
1980 __IO uint16_t ER15 : 1;
\r
1981 } stc_exti_eirr_field_t;
\r
1983 typedef struct stc_exti_eicl_field
\r
1985 __IO uint16_t ECL0 : 1;
\r
1986 __IO uint16_t ECL1 : 1;
\r
1987 __IO uint16_t ECL2 : 1;
\r
1988 __IO uint16_t ECL3 : 1;
\r
1989 __IO uint16_t ECL4 : 1;
\r
1990 __IO uint16_t ECL5 : 1;
\r
1991 __IO uint16_t ECL6 : 1;
\r
1992 __IO uint16_t ECL7 : 1;
\r
1993 __IO uint16_t ECL8 : 1;
\r
1994 uint16_t RESERVED1 : 5;
\r
1995 __IO uint16_t ECL14 : 1;
\r
1996 __IO uint16_t ECL15 : 1;
\r
1997 } stc_exti_eicl_field_t;
\r
1999 typedef struct stc_exti_elvr_field
\r
2001 __IO uint32_t LA0 : 1;
\r
2002 __IO uint32_t LB0 : 1;
\r
2003 __IO uint32_t LA1 : 1;
\r
2004 __IO uint32_t LB1 : 1;
\r
2005 __IO uint32_t LA2 : 1;
\r
2006 __IO uint32_t LB2 : 1;
\r
2007 __IO uint32_t LA3 : 1;
\r
2008 __IO uint32_t LB3 : 1;
\r
2009 __IO uint32_t LA4 : 1;
\r
2010 __IO uint32_t LB4 : 1;
\r
2011 __IO uint32_t LA5 : 1;
\r
2012 __IO uint32_t LB5 : 1;
\r
2013 __IO uint32_t LA6 : 1;
\r
2014 __IO uint32_t LB6 : 1;
\r
2015 __IO uint32_t LA7 : 1;
\r
2016 __IO uint32_t LB7 : 1;
\r
2017 __IO uint32_t LA8 : 1;
\r
2018 __IO uint32_t LB8 : 1;
\r
2019 uint32_t RESERVED1 : 10;
\r
2020 __IO uint32_t LA14 : 1;
\r
2021 __IO uint32_t LB14 : 1;
\r
2022 __IO uint32_t LA15 : 1;
\r
2023 __IO uint32_t LB15 : 1;
\r
2024 } stc_exti_elvr_field_t;
\r
2026 typedef struct stc_exti_nmirr_field
\r
2028 __IO uint8_t NR0 : 1;
\r
2029 } stc_exti_nmirr_field_t;
\r
2031 typedef struct stc_exti_nmicl_field
\r
2033 __IO uint8_t NCL0 : 1;
\r
2034 } stc_exti_nmicl_field_t;
\r
2036 /******************************************************************************
\r
2038 ******************************************************************************/
\r
2039 /* INTREQ_MODULE register bit fields */
\r
2040 typedef struct stc_intreq_drqsel_field
\r
2042 __IO uint32_t DRQSEL0 : 1;
\r
2043 __IO uint32_t DRQSEL1 : 1;
\r
2044 __IO uint32_t DRQSEL2 : 1;
\r
2045 __IO uint32_t DRQSEL3 : 1;
\r
2046 __IO uint32_t DRQSEL4 : 1;
\r
2047 __IO uint32_t DRQSEL5 : 1;
\r
2048 __IO uint32_t DRQSEL6 : 1;
\r
2049 __IO uint32_t DRQSEL7 : 1;
\r
2050 __IO uint32_t DRQSEL8 : 1;
\r
2051 __IO uint32_t DRQSEL9 : 1;
\r
2052 __IO uint32_t DRQSEL10 : 1;
\r
2053 __IO uint32_t DRQSEL11 : 1;
\r
2054 __IO uint32_t DRQSEL12 : 1;
\r
2055 __IO uint32_t DRQSEL13 : 1;
\r
2056 __IO uint32_t DRQSEL14 : 1;
\r
2057 __IO uint32_t DRQSEL15 : 1;
\r
2058 __IO uint32_t DRQSEL16 : 1;
\r
2059 __IO uint32_t DRQSEL17 : 1;
\r
2060 __IO uint32_t DRQSEL18 : 1;
\r
2061 __IO uint32_t DRQSEL19 : 1;
\r
2062 __IO uint32_t DRQSEL20 : 1;
\r
2063 __IO uint32_t DRQSEL21 : 1;
\r
2064 __IO uint32_t DRQSEL22 : 1;
\r
2065 __IO uint32_t DRQSEL23 : 1;
\r
2066 __IO uint32_t DRQSEL24 : 1;
\r
2067 __IO uint32_t DRQSEL25 : 1;
\r
2068 __IO uint32_t DRQSEL26 : 1;
\r
2069 __IO uint32_t DRQSEL27 : 1;
\r
2070 __IO uint32_t DRQSEL28 : 1;
\r
2071 __IO uint32_t DRQSEL29 : 1;
\r
2072 __IO uint32_t DRQSEL30 : 1;
\r
2073 __IO uint32_t DRQSEL31 : 1;
\r
2074 } stc_intreq_drqsel_field_t;
\r
2076 typedef struct stc_intreq_oddpks_field
\r
2078 __IO uint32_t ODDPKS0 : 1;
\r
2079 __IO uint32_t ODDPKS1 : 1;
\r
2080 __IO uint32_t ODDPKS2 : 1;
\r
2081 __IO uint32_t ODDPKS3 : 1;
\r
2082 __IO uint32_t ODDPKS4 : 1;
\r
2083 } stc_intreq_oddpks_field_t;
\r
2085 typedef struct stc_intreq_exc02mon_field
\r
2087 __IO uint32_t NMI : 1;
\r
2088 __IO uint32_t HWINT : 1;
\r
2089 } stc_intreq_exc02mon_field_t;
\r
2091 typedef struct stc_intreq_irq00mon_field
\r
2093 __IO uint32_t FCSINT : 1;
\r
2094 } stc_intreq_irq00mon_field_t;
\r
2096 typedef struct stc_intreq_irq01mon_field
\r
2098 __IO uint32_t SWWDTINT : 1;
\r
2099 } stc_intreq_irq01mon_field_t;
\r
2101 typedef struct stc_intreq_irq02mon_field
\r
2103 __IO uint32_t LVDINT : 1;
\r
2104 } stc_intreq_irq02mon_field_t;
\r
2106 typedef struct stc_intreq_irq03mon_field
\r
2108 __IO uint32_t WAVE0INT0 : 1;
\r
2109 __IO uint32_t WAVE0INT1 : 1;
\r
2110 __IO uint32_t WAVE0INT2 : 1;
\r
2111 __IO uint32_t WAVE0INT3 : 1;
\r
2112 __IO uint32_t WAVE1INT0 : 1;
\r
2113 __IO uint32_t WAVE1INT1 : 1;
\r
2114 __IO uint32_t WAVE1INT2 : 1;
\r
2115 __IO uint32_t WAVE1INT3 : 1;
\r
2116 } stc_intreq_irq03mon_field_t;
\r
2118 typedef struct stc_intreq_irq04mon_field
\r
2120 __IO uint32_t EXTINT0 : 1;
\r
2121 __IO uint32_t EXTINT1 : 1;
\r
2122 __IO uint32_t EXTINT2 : 1;
\r
2123 __IO uint32_t EXTINT3 : 1;
\r
2124 __IO uint32_t EXTINT4 : 1;
\r
2125 __IO uint32_t EXTINT5 : 1;
\r
2126 __IO uint32_t EXTINT6 : 1;
\r
2127 } stc_intreq_irq04mon_field_t;
\r
2129 typedef struct stc_intreq_irq05mon_field
\r
2131 uint32_t RESERVED1 : 7;
\r
2132 __IO uint32_t EXTINT7 : 1;
\r
2133 } stc_intreq_irq05mon_field_t;
\r
2135 typedef struct stc_intreq_irq06mon_field
\r
2137 __IO uint32_t TIMINT0 : 1;
\r
2138 __IO uint32_t TIMINT1 : 1;
\r
2139 __IO uint32_t QUD0INT0 : 1;
\r
2140 __IO uint32_t QUD0INT1 : 1;
\r
2141 __IO uint32_t QUD0INT2 : 1;
\r
2142 __IO uint32_t QUD0INT3 : 1;
\r
2143 __IO uint32_t QUD0INT4 : 1;
\r
2144 __IO uint32_t QUD0INT5 : 1;
\r
2145 __IO uint32_t QUD1INT0 : 1;
\r
2146 __IO uint32_t QUD1INT1 : 1;
\r
2147 __IO uint32_t QUD1INT2 : 1;
\r
2148 __IO uint32_t QUD1INT3 : 1;
\r
2149 __IO uint32_t QUD1INT4 : 1;
\r
2150 __IO uint32_t QUD1INT5 : 1;
\r
2151 } stc_intreq_irq06mon_field_t;
\r
2153 typedef struct stc_intreq_irq07mon_field
\r
2155 __IO uint32_t FMSINT : 1;
\r
2156 } stc_intreq_irq07mon_field_t;
\r
2158 typedef struct stc_intreq_irq08mon_field
\r
2160 __IO uint32_t MFSINT0 : 1;
\r
2161 __IO uint32_t MFSINT1 : 1;
\r
2162 } stc_intreq_irq08mon_field_t;
\r
2164 typedef struct stc_intreq_irq09mon_field
\r
2166 __IO uint32_t FMSINT : 1;
\r
2167 } stc_intreq_irq09mon_field_t;
\r
2169 typedef struct stc_intreq_irq10mon_field
\r
2171 __IO uint32_t MFSINT0 : 1;
\r
2172 __IO uint32_t MFSINT1 : 1;
\r
2173 } stc_intreq_irq10mon_field_t;
\r
2175 typedef struct stc_intreq_irq11mon_field
\r
2177 __IO uint32_t FMSINT : 1;
\r
2178 } stc_intreq_irq11mon_field_t;
\r
2180 typedef struct stc_intreq_irq12mon_field
\r
2182 __IO uint32_t MFSINT0 : 1;
\r
2183 __IO uint32_t MFSINT1 : 1;
\r
2184 } stc_intreq_irq12mon_field_t;
\r
2186 typedef struct stc_intreq_irq13mon_field
\r
2188 __IO uint32_t FMSINT : 1;
\r
2189 } stc_intreq_irq13mon_field_t;
\r
2191 typedef struct stc_intreq_irq14mon_field
\r
2193 __IO uint32_t MFSINT0 : 1;
\r
2194 __IO uint32_t MFSINT1 : 1;
\r
2195 } stc_intreq_irq14mon_field_t;
\r
2197 typedef struct stc_intreq_irq15mon_field
\r
2199 __IO uint32_t FMSINT : 1;
\r
2200 } stc_intreq_irq15mon_field_t;
\r
2202 typedef struct stc_intreq_irq16mon_field
\r
2204 __IO uint32_t MFSINT0 : 1;
\r
2205 __IO uint32_t MFSINT1 : 1;
\r
2206 } stc_intreq_irq16mon_field_t;
\r
2208 typedef struct stc_intreq_irq17mon_field
\r
2210 __IO uint32_t FMSINT : 1;
\r
2211 } stc_intreq_irq17mon_field_t;
\r
2213 typedef struct stc_intreq_irq18mon_field
\r
2215 __IO uint32_t MFSINT0 : 1;
\r
2216 __IO uint32_t MFSINT1 : 1;
\r
2217 } stc_intreq_irq18mon_field_t;
\r
2219 typedef struct stc_intreq_irq19mon_field
\r
2221 __IO uint32_t FMSINT : 1;
\r
2222 } stc_intreq_irq19mon_field_t;
\r
2224 typedef struct stc_intreq_irq20mon_field
\r
2226 __IO uint32_t MFSINT0 : 1;
\r
2227 __IO uint32_t MFSINT1 : 1;
\r
2228 } stc_intreq_irq20mon_field_t;
\r
2230 typedef struct stc_intreq_irq21mon_field
\r
2232 __IO uint32_t FMSINT : 1;
\r
2233 } stc_intreq_irq21mon_field_t;
\r
2235 typedef struct stc_intreq_irq22mon_field
\r
2237 __IO uint32_t MFSINT0 : 1;
\r
2238 __IO uint32_t MFSINT1 : 1;
\r
2239 } stc_intreq_irq22mon_field_t;
\r
2241 typedef struct stc_intreq_irq23mon_field
\r
2243 __IO uint32_t PPGINT0 : 1;
\r
2244 __IO uint32_t PPGINT1 : 1;
\r
2245 __IO uint32_t PPGINT2 : 1;
\r
2246 __IO uint32_t PPGINT3 : 1;
\r
2247 __IO uint32_t PPGINT4 : 1;
\r
2248 __IO uint32_t PPGINT5 : 1;
\r
2249 } stc_intreq_irq23mon_field_t;
\r
2251 typedef struct stc_intreq_irq24mon_field
\r
2253 __IO uint32_t MOSCINT : 1;
\r
2254 __IO uint32_t SOSCINT : 1;
\r
2255 __IO uint32_t MPLLINT : 1;
\r
2256 __IO uint32_t UPLLINT : 1;
\r
2257 __IO uint32_t WCINT : 1;
\r
2258 } stc_intreq_irq24mon_field_t;
\r
2260 typedef struct stc_intreq_irq25mon_field
\r
2262 __IO uint32_t ADCINT0 : 1;
\r
2263 __IO uint32_t ADCINT1 : 1;
\r
2264 __IO uint32_t ADCINT2 : 1;
\r
2265 __IO uint32_t ADCINT3 : 1;
\r
2266 } stc_intreq_irq25mon_field_t;
\r
2268 typedef struct stc_intreq_irq26mon_field
\r
2270 __IO uint32_t ADCINT0 : 1;
\r
2271 __IO uint32_t ADCINT1 : 1;
\r
2272 __IO uint32_t ADCINT2 : 1;
\r
2273 __IO uint32_t ADCINT3 : 1;
\r
2274 } stc_intreq_irq26mon_field_t;
\r
2276 typedef struct stc_intreq_irq28mon_field
\r
2278 __IO uint32_t FRT0INT0 : 1;
\r
2279 __IO uint32_t FRT0INT1 : 1;
\r
2280 __IO uint32_t FRT0INT2 : 1;
\r
2281 __IO uint32_t FRT0INT3 : 1;
\r
2282 __IO uint32_t FRT0INT4 : 1;
\r
2283 __IO uint32_t FRT0INT5 : 1;
\r
2284 __IO uint32_t FRT1INT0 : 1;
\r
2285 __IO uint32_t FRT1INT1 : 1;
\r
2286 __IO uint32_t FRT1INT2 : 1;
\r
2287 __IO uint32_t FRT1INT3 : 1;
\r
2288 __IO uint32_t FRT1INT4 : 1;
\r
2289 __IO uint32_t FRT1INT5 : 1;
\r
2290 } stc_intreq_irq28mon_field_t;
\r
2292 typedef struct stc_intreq_irq29mon_field
\r
2294 __IO uint32_t ICU0INT0 : 1;
\r
2295 __IO uint32_t ICU0INT1 : 1;
\r
2296 __IO uint32_t ICU0INT2 : 1;
\r
2297 __IO uint32_t ICU0INT3 : 1;
\r
2298 __IO uint32_t ICU1INT0 : 1;
\r
2299 __IO uint32_t ICU1INT1 : 1;
\r
2300 __IO uint32_t ICU1INT2 : 1;
\r
2301 __IO uint32_t ICU1INT3 : 1;
\r
2302 } stc_intreq_irq29mon_field_t;
\r
2304 typedef struct stc_intreq_irq30mon_field
\r
2306 __IO uint32_t OCU0INT0 : 1;
\r
2307 __IO uint32_t OCU0INT1 : 1;
\r
2308 __IO uint32_t OCU0INT2 : 1;
\r
2309 __IO uint32_t OCU0INT3 : 1;
\r
2310 __IO uint32_t OCU0INT4 : 1;
\r
2311 __IO uint32_t OCU0INT5 : 1;
\r
2312 __IO uint32_t OCU1INT0 : 1;
\r
2313 __IO uint32_t OCU1INT1 : 1;
\r
2314 __IO uint32_t OCU1INT2 : 1;
\r
2315 __IO uint32_t OCU1INT3 : 1;
\r
2316 __IO uint32_t OCU1INT4 : 1;
\r
2317 __IO uint32_t OCU1INT5 : 1;
\r
2318 } stc_intreq_irq30mon_field_t;
\r
2320 typedef struct stc_intreq_irq31mon_field
\r
2322 __IO uint32_t BTINT0 : 1;
\r
2323 __IO uint32_t BTINT1 : 1;
\r
2324 __IO uint32_t BTINT2 : 1;
\r
2325 __IO uint32_t BTINT3 : 1;
\r
2326 __IO uint32_t BTINT4 : 1;
\r
2327 __IO uint32_t BTINT5 : 1;
\r
2328 __IO uint32_t BTINT6 : 1;
\r
2329 __IO uint32_t BTINT7 : 1;
\r
2330 __IO uint32_t BTINT8 : 1;
\r
2331 __IO uint32_t BTINT9 : 1;
\r
2332 __IO uint32_t BTINT10 : 1;
\r
2333 __IO uint32_t BTINT11 : 1;
\r
2334 __IO uint32_t BTINT12 : 1;
\r
2335 __IO uint32_t BTINT13 : 1;
\r
2336 __IO uint32_t BTINT14 : 1;
\r
2337 __IO uint32_t BTINT15 : 1;
\r
2338 } stc_intreq_irq31mon_field_t;
\r
2340 typedef struct stc_intreq_irq34mon_field
\r
2342 __IO uint32_t USB0INT0 : 1;
\r
2343 __IO uint32_t USB0INT1 : 1;
\r
2344 __IO uint32_t USB0INT2 : 1;
\r
2345 __IO uint32_t USB0INT3 : 1;
\r
2346 __IO uint32_t USB0INT4 : 1;
\r
2347 } stc_intreq_irq34mon_field_t;
\r
2349 typedef struct stc_intreq_irq35mon_field
\r
2351 __IO uint32_t USB0INT0 : 1;
\r
2352 __IO uint32_t USB0INT1 : 1;
\r
2353 __IO uint32_t USB0INT2 : 1;
\r
2354 __IO uint32_t USB0INT3 : 1;
\r
2355 __IO uint32_t USB0INT4 : 1;
\r
2356 __IO uint32_t USB0INT5 : 1;
\r
2357 } stc_intreq_irq35mon_field_t;
\r
2359 typedef struct stc_intreq_irq38mon_field
\r
2361 __IO uint32_t DMAINT : 1;
\r
2362 } stc_intreq_irq38mon_field_t;
\r
2364 typedef struct stc_intreq_irq39mon_field
\r
2366 __IO uint32_t DMAINT : 1;
\r
2367 } stc_intreq_irq39mon_field_t;
\r
2369 typedef struct stc_intreq_irq40mon_field
\r
2371 __IO uint32_t DMAINT : 1;
\r
2372 } stc_intreq_irq40mon_field_t;
\r
2374 typedef struct stc_intreq_irq41mon_field
\r
2376 __IO uint32_t DMAINT : 1;
\r
2377 } stc_intreq_irq41mon_field_t;
\r
2379 typedef struct stc_intreq_irq42mon_field
\r
2381 __IO uint32_t DMAINT : 1;
\r
2382 } stc_intreq_irq42mon_field_t;
\r
2384 typedef struct stc_intreq_irq43mon_field
\r
2386 __IO uint32_t DMAINT : 1;
\r
2387 } stc_intreq_irq43mon_field_t;
\r
2389 typedef struct stc_intreq_irq44mon_field
\r
2391 __IO uint32_t DMAINT : 1;
\r
2392 } stc_intreq_irq44mon_field_t;
\r
2394 typedef struct stc_intreq_irq45mon_field
\r
2396 __IO uint32_t DMAINT : 1;
\r
2397 } stc_intreq_irq45mon_field_t;
\r
2399 /******************************************************************************
\r
2401 ******************************************************************************/
\r
2402 /* GPIO_MODULE register bit fields */
\r
2403 typedef struct stc_gpio_pfr0_field
\r
2405 __IO uint32_t P0 : 1;
\r
2406 __IO uint32_t P1 : 1;
\r
2407 __IO uint32_t P2 : 1;
\r
2408 __IO uint32_t P3 : 1;
\r
2409 __IO uint32_t P4 : 1;
\r
2410 uint32_t RESERVED1 : 5;
\r
2411 __IO uint32_t PA : 1;
\r
2412 __IO uint32_t PB : 1;
\r
2413 __IO uint32_t PC : 1;
\r
2414 uint32_t RESERVED2 : 2;
\r
2415 __IO uint32_t PF : 1;
\r
2416 } stc_gpio_pfr0_field_t;
\r
2418 typedef struct stc_gpio_pfr1_field
\r
2420 __IO uint32_t P0 : 1;
\r
2421 __IO uint32_t P1 : 1;
\r
2422 __IO uint32_t P2 : 1;
\r
2423 __IO uint32_t P3 : 1;
\r
2424 __IO uint32_t P4 : 1;
\r
2425 __IO uint32_t P5 : 1;
\r
2426 uint32_t RESERVED1 : 1;
\r
2427 __IO uint32_t P7 : 1;
\r
2428 __IO uint32_t P8 : 1;
\r
2429 __IO uint32_t P9 : 1;
\r
2430 } stc_gpio_pfr1_field_t;
\r
2432 typedef struct stc_gpio_pfr2_field
\r
2434 uint32_t RESERVED1 : 1;
\r
2435 __IO uint32_t P1 : 1;
\r
2436 __IO uint32_t P2 : 1;
\r
2437 __IO uint32_t P3 : 1;
\r
2438 } stc_gpio_pfr2_field_t;
\r
2440 typedef struct stc_gpio_pfr3_field
\r
2442 __IO uint32_t P0 : 1;
\r
2443 __IO uint32_t P1 : 1;
\r
2444 __IO uint32_t P2 : 1;
\r
2445 __IO uint32_t P3 : 1;
\r
2446 uint32_t RESERVED1 : 5;
\r
2447 __IO uint32_t P9 : 1;
\r
2448 __IO uint32_t PA : 1;
\r
2449 __IO uint32_t PB : 1;
\r
2450 __IO uint32_t PC : 1;
\r
2451 __IO uint32_t PD : 1;
\r
2452 __IO uint32_t PE : 1;
\r
2453 __IO uint32_t PF : 1;
\r
2454 } stc_gpio_pfr3_field_t;
\r
2456 typedef struct stc_gpio_pfr4_field
\r
2458 uint32_t RESERVED1 : 6;
\r
2459 __IO uint32_t P6 : 1;
\r
2460 __IO uint32_t P7 : 1;
\r
2461 uint32_t RESERVED2 : 1;
\r
2462 __IO uint32_t P9 : 1;
\r
2463 __IO uint32_t PA : 1;
\r
2464 __IO uint32_t PB : 1;
\r
2465 __IO uint32_t PC : 1;
\r
2466 __IO uint32_t PD : 1;
\r
2467 __IO uint32_t PE : 1;
\r
2468 } stc_gpio_pfr4_field_t;
\r
2470 typedef struct stc_gpio_pfr5_field
\r
2472 __IO uint32_t P0 : 1;
\r
2473 __IO uint32_t P1 : 1;
\r
2474 __IO uint32_t P2 : 1;
\r
2475 } stc_gpio_pfr5_field_t;
\r
2477 typedef struct stc_gpio_pfr6_field
\r
2479 __IO uint32_t P0 : 1;
\r
2480 __IO uint32_t P1 : 1;
\r
2481 __IO uint32_t P2 : 1;
\r
2482 } stc_gpio_pfr6_field_t;
\r
2484 typedef struct stc_gpio_pfr8_field
\r
2486 __IO uint32_t P0 : 1;
\r
2487 __IO uint32_t P1 : 1;
\r
2488 } stc_gpio_pfr8_field_t;
\r
2490 typedef struct stc_gpio_pfre_field
\r
2492 __IO uint32_t P0 : 1;
\r
2493 uint32_t RESERVED1 : 1;
\r
2494 __IO uint32_t P2 : 1;
\r
2495 __IO uint32_t P3 : 1;
\r
2496 } stc_gpio_pfre_field_t;
\r
2498 typedef struct stc_gpio_pcr0_field
\r
2500 __IO uint32_t P0 : 1;
\r
2501 __IO uint32_t P1 : 1;
\r
2502 __IO uint32_t P2 : 1;
\r
2503 __IO uint32_t P3 : 1;
\r
2504 __IO uint32_t P4 : 1;
\r
2505 uint32_t RESERVED1 : 5;
\r
2506 __IO uint32_t PA : 1;
\r
2507 __IO uint32_t PB : 1;
\r
2508 __IO uint32_t PC : 1;
\r
2509 uint32_t RESERVED2 : 2;
\r
2510 __IO uint32_t PF : 1;
\r
2511 } stc_gpio_pcr0_field_t;
\r
2513 typedef struct stc_gpio_pcr1_field
\r
2515 __IO uint32_t P0 : 1;
\r
2516 __IO uint32_t P1 : 1;
\r
2517 __IO uint32_t P2 : 1;
\r
2518 __IO uint32_t P3 : 1;
\r
2519 __IO uint32_t P4 : 1;
\r
2520 __IO uint32_t P5 : 1;
\r
2521 uint32_t RESERVED1 : 1;
\r
2522 __IO uint32_t P7 : 1;
\r
2523 __IO uint32_t P8 : 1;
\r
2524 __IO uint32_t P9 : 1;
\r
2525 } stc_gpio_pcr1_field_t;
\r
2527 typedef struct stc_gpio_pcr2_field
\r
2529 uint32_t RESERVED1 : 1;
\r
2530 __IO uint32_t P1 : 1;
\r
2531 __IO uint32_t P2 : 1;
\r
2532 __IO uint32_t P3 : 1;
\r
2533 } stc_gpio_pcr2_field_t;
\r
2535 typedef struct stc_gpio_pcr3_field
\r
2537 __IO uint32_t P0 : 1;
\r
2538 __IO uint32_t P1 : 1;
\r
2539 __IO uint32_t P2 : 1;
\r
2540 __IO uint32_t P3 : 1;
\r
2541 uint32_t RESERVED1 : 5;
\r
2542 __IO uint32_t P9 : 1;
\r
2543 __IO uint32_t PA : 1;
\r
2544 __IO uint32_t PB : 1;
\r
2545 __IO uint32_t PC : 1;
\r
2546 __IO uint32_t PD : 1;
\r
2547 __IO uint32_t PE : 1;
\r
2548 __IO uint32_t PF : 1;
\r
2549 } stc_gpio_pcr3_field_t;
\r
2551 typedef struct stc_gpio_pcr4_field
\r
2553 uint32_t RESERVED1 : 6;
\r
2554 __IO uint32_t P6 : 1;
\r
2555 __IO uint32_t P7 : 1;
\r
2556 uint32_t RESERVED2 : 1;
\r
2557 __IO uint32_t P9 : 1;
\r
2558 __IO uint32_t PA : 1;
\r
2559 __IO uint32_t PB : 1;
\r
2560 __IO uint32_t PC : 1;
\r
2561 __IO uint32_t PD : 1;
\r
2562 __IO uint32_t PE : 1;
\r
2563 } stc_gpio_pcr4_field_t;
\r
2565 typedef struct stc_gpio_pcr5_field
\r
2567 __IO uint32_t P0 : 1;
\r
2568 __IO uint32_t P1 : 1;
\r
2569 __IO uint32_t P2 : 1;
\r
2570 } stc_gpio_pcr5_field_t;
\r
2572 typedef struct stc_gpio_pcr6_field
\r
2574 __IO uint32_t P0 : 1;
\r
2575 __IO uint32_t P1 : 1;
\r
2576 __IO uint32_t P2 : 1;
\r
2577 } stc_gpio_pcr6_field_t;
\r
2579 typedef struct stc_gpio_pcre_field
\r
2581 __IO uint32_t P0 : 1;
\r
2582 uint32_t RESERVED1 : 1;
\r
2583 __IO uint32_t P2 : 1;
\r
2584 __IO uint32_t P3 : 1;
\r
2585 } stc_gpio_pcre_field_t;
\r
2587 typedef struct stc_gpio_ddr0_field
\r
2589 __IO uint32_t P0 : 1;
\r
2590 __IO uint32_t P1 : 1;
\r
2591 __IO uint32_t P2 : 1;
\r
2592 __IO uint32_t P3 : 1;
\r
2593 __IO uint32_t P4 : 1;
\r
2594 uint32_t RESERVED1 : 5;
\r
2595 __IO uint32_t PA : 1;
\r
2596 __IO uint32_t PB : 1;
\r
2597 __IO uint32_t PC : 1;
\r
2598 uint32_t RESERVED2 : 2;
\r
2599 __IO uint32_t PF : 1;
\r
2600 } stc_gpio_ddr0_field_t;
\r
2602 typedef struct stc_gpio_ddr1_field
\r
2604 __IO uint32_t P0 : 1;
\r
2605 __IO uint32_t P1 : 1;
\r
2606 __IO uint32_t P2 : 1;
\r
2607 __IO uint32_t P3 : 1;
\r
2608 __IO uint32_t P4 : 1;
\r
2609 __IO uint32_t P5 : 1;
\r
2610 uint32_t RESERVED1 : 1;
\r
2611 __IO uint32_t P7 : 1;
\r
2612 __IO uint32_t P8 : 1;
\r
2613 __IO uint32_t P9 : 1;
\r
2614 } stc_gpio_ddr1_field_t;
\r
2616 typedef struct stc_gpio_ddr2_field
\r
2618 uint32_t RESERVED1 : 1;
\r
2619 __IO uint32_t P1 : 1;
\r
2620 __IO uint32_t P2 : 1;
\r
2621 __IO uint32_t P3 : 1;
\r
2622 } stc_gpio_ddr2_field_t;
\r
2624 typedef struct stc_gpio_ddr3_field
\r
2626 __IO uint32_t P0 : 1;
\r
2627 __IO uint32_t P1 : 1;
\r
2628 __IO uint32_t P2 : 1;
\r
2629 __IO uint32_t P3 : 1;
\r
2630 uint32_t RESERVED1 : 5;
\r
2631 __IO uint32_t P9 : 1;
\r
2632 __IO uint32_t PA : 1;
\r
2633 __IO uint32_t PB : 1;
\r
2634 __IO uint32_t PC : 1;
\r
2635 __IO uint32_t PD : 1;
\r
2636 __IO uint32_t PE : 1;
\r
2637 __IO uint32_t PF : 1;
\r
2638 } stc_gpio_ddr3_field_t;
\r
2640 typedef struct stc_gpio_ddr4_field
\r
2642 uint32_t RESERVED1 : 6;
\r
2643 __IO uint32_t P6 : 1;
\r
2644 __IO uint32_t P7 : 1;
\r
2645 uint32_t RESERVED2 : 1;
\r
2646 __IO uint32_t P9 : 1;
\r
2647 __IO uint32_t PA : 1;
\r
2648 __IO uint32_t PB : 1;
\r
2649 __IO uint32_t PC : 1;
\r
2650 __IO uint32_t PD : 1;
\r
2651 __IO uint32_t PE : 1;
\r
2652 } stc_gpio_ddr4_field_t;
\r
2654 typedef struct stc_gpio_ddr5_field
\r
2656 __IO uint32_t P0 : 1;
\r
2657 __IO uint32_t P1 : 1;
\r
2658 __IO uint32_t P2 : 1;
\r
2659 } stc_gpio_ddr5_field_t;
\r
2661 typedef struct stc_gpio_ddr6_field
\r
2663 __IO uint32_t P0 : 1;
\r
2664 __IO uint32_t P1 : 1;
\r
2665 __IO uint32_t P2 : 1;
\r
2666 } stc_gpio_ddr6_field_t;
\r
2668 typedef struct stc_gpio_ddr8_field
\r
2670 __IO uint32_t P0 : 1;
\r
2671 __IO uint32_t P1 : 1;
\r
2672 } stc_gpio_ddr8_field_t;
\r
2674 typedef struct stc_gpio_ddre_field
\r
2676 __IO uint32_t P0 : 1;
\r
2677 uint32_t RESERVED1 : 1;
\r
2678 __IO uint32_t P2 : 1;
\r
2679 __IO uint32_t P3 : 1;
\r
2680 } stc_gpio_ddre_field_t;
\r
2682 typedef struct stc_gpio_pdir0_field
\r
2684 __IO uint32_t P0 : 1;
\r
2685 __IO uint32_t P1 : 1;
\r
2686 __IO uint32_t P2 : 1;
\r
2687 __IO uint32_t P3 : 1;
\r
2688 __IO uint32_t P4 : 1;
\r
2689 uint32_t RESERVED1 : 5;
\r
2690 __IO uint32_t PA : 1;
\r
2691 __IO uint32_t PB : 1;
\r
2692 __IO uint32_t PC : 1;
\r
2693 uint32_t RESERVED2 : 2;
\r
2694 __IO uint32_t PF : 1;
\r
2695 } stc_gpio_pdir0_field_t;
\r
2697 typedef struct stc_gpio_pdir1_field
\r
2699 __IO uint32_t P0 : 1;
\r
2700 __IO uint32_t P1 : 1;
\r
2701 __IO uint32_t P2 : 1;
\r
2702 __IO uint32_t P3 : 1;
\r
2703 __IO uint32_t P4 : 1;
\r
2704 __IO uint32_t P5 : 1;
\r
2705 uint32_t RESERVED1 : 1;
\r
2706 __IO uint32_t P7 : 1;
\r
2707 __IO uint32_t P8 : 1;
\r
2708 __IO uint32_t P9 : 1;
\r
2709 } stc_gpio_pdir1_field_t;
\r
2711 typedef struct stc_gpio_pdir2_field
\r
2713 uint32_t RESERVED1 : 1;
\r
2714 __IO uint32_t P1 : 1;
\r
2715 __IO uint32_t P2 : 1;
\r
2716 __IO uint32_t P3 : 1;
\r
2717 } stc_gpio_pdir2_field_t;
\r
2719 typedef struct stc_gpio_pdir3_field
\r
2721 __IO uint32_t P0 : 1;
\r
2722 __IO uint32_t P1 : 1;
\r
2723 __IO uint32_t P2 : 1;
\r
2724 __IO uint32_t P3 : 1;
\r
2725 uint32_t RESERVED1 : 5;
\r
2726 __IO uint32_t P9 : 1;
\r
2727 __IO uint32_t PA : 1;
\r
2728 __IO uint32_t PB : 1;
\r
2729 __IO uint32_t PC : 1;
\r
2730 __IO uint32_t PD : 1;
\r
2731 __IO uint32_t PE : 1;
\r
2732 __IO uint32_t PF : 1;
\r
2733 } stc_gpio_pdir3_field_t;
\r
2735 typedef struct stc_gpio_pdir4_field
\r
2737 uint32_t RESERVED1 : 6;
\r
2738 __IO uint32_t P6 : 1;
\r
2739 __IO uint32_t P7 : 1;
\r
2740 uint32_t RESERVED2 : 1;
\r
2741 __IO uint32_t P9 : 1;
\r
2742 __IO uint32_t PA : 1;
\r
2743 __IO uint32_t PB : 1;
\r
2744 __IO uint32_t PC : 1;
\r
2745 __IO uint32_t PD : 1;
\r
2746 __IO uint32_t PE : 1;
\r
2747 } stc_gpio_pdir4_field_t;
\r
2749 typedef struct stc_gpio_pdir5_field
\r
2751 __IO uint32_t P0 : 1;
\r
2752 __IO uint32_t P1 : 1;
\r
2753 __IO uint32_t P2 : 1;
\r
2754 } stc_gpio_pdir5_field_t;
\r
2756 typedef struct stc_gpio_pdir6_field
\r
2758 __IO uint32_t P0 : 1;
\r
2759 __IO uint32_t P1 : 1;
\r
2760 __IO uint32_t P2 : 1;
\r
2761 } stc_gpio_pdir6_field_t;
\r
2763 typedef struct stc_gpio_pdir8_field
\r
2765 __IO uint32_t P0 : 1;
\r
2766 __IO uint32_t P1 : 1;
\r
2767 } stc_gpio_pdir8_field_t;
\r
2769 typedef struct stc_gpio_pdire_field
\r
2771 __IO uint32_t P0 : 1;
\r
2772 uint32_t RESERVED1 : 1;
\r
2773 __IO uint32_t P2 : 1;
\r
2774 __IO uint32_t P3 : 1;
\r
2775 } stc_gpio_pdire_field_t;
\r
2777 typedef struct stc_gpio_pdor0_field
\r
2779 __IO uint32_t P0 : 1;
\r
2780 __IO uint32_t P1 : 1;
\r
2781 __IO uint32_t P2 : 1;
\r
2782 __IO uint32_t P3 : 1;
\r
2783 __IO uint32_t P4 : 1;
\r
2784 uint32_t RESERVED1 : 5;
\r
2785 __IO uint32_t PA : 1;
\r
2786 __IO uint32_t PB : 1;
\r
2787 __IO uint32_t PC : 1;
\r
2788 uint32_t RESERVED2 : 2;
\r
2789 __IO uint32_t PF : 1;
\r
2790 } stc_gpio_pdor0_field_t;
\r
2792 typedef struct stc_gpio_pdor1_field
\r
2794 __IO uint32_t P0 : 1;
\r
2795 __IO uint32_t P1 : 1;
\r
2796 __IO uint32_t P2 : 1;
\r
2797 __IO uint32_t P3 : 1;
\r
2798 __IO uint32_t P4 : 1;
\r
2799 __IO uint32_t P5 : 1;
\r
2800 uint32_t RESERVED1 : 1;
\r
2801 __IO uint32_t P7 : 1;
\r
2802 __IO uint32_t P8 : 1;
\r
2803 __IO uint32_t P9 : 1;
\r
2804 } stc_gpio_pdor1_field_t;
\r
2806 typedef struct stc_gpio_pdor2_field
\r
2808 uint32_t RESERVED1 : 1;
\r
2809 __IO uint32_t P1 : 1;
\r
2810 __IO uint32_t P2 : 1;
\r
2811 __IO uint32_t P3 : 1;
\r
2812 } stc_gpio_pdor2_field_t;
\r
2814 typedef struct stc_gpio_pdor3_field
\r
2816 __IO uint32_t P0 : 1;
\r
2817 __IO uint32_t P1 : 1;
\r
2818 __IO uint32_t P2 : 1;
\r
2819 __IO uint32_t P3 : 1;
\r
2820 uint32_t RESERVED1 : 5;
\r
2821 __IO uint32_t P9 : 1;
\r
2822 __IO uint32_t PA : 1;
\r
2823 __IO uint32_t PB : 1;
\r
2824 __IO uint32_t PC : 1;
\r
2825 __IO uint32_t PD : 1;
\r
2826 __IO uint32_t PE : 1;
\r
2827 __IO uint32_t PF : 1;
\r
2828 } stc_gpio_pdor3_field_t;
\r
2830 typedef struct stc_gpio_pdor4_field
\r
2832 uint32_t RESERVED1 : 6;
\r
2833 __IO uint32_t P6 : 1;
\r
2834 __IO uint32_t P7 : 1;
\r
2835 uint32_t RESERVED2 : 1;
\r
2836 __IO uint32_t P9 : 1;
\r
2837 __IO uint32_t PA : 1;
\r
2838 __IO uint32_t PB : 1;
\r
2839 __IO uint32_t PC : 1;
\r
2840 __IO uint32_t PD : 1;
\r
2841 __IO uint32_t PE : 1;
\r
2842 } stc_gpio_pdor4_field_t;
\r
2844 typedef struct stc_gpio_pdor5_field
\r
2846 __IO uint32_t P0 : 1;
\r
2847 __IO uint32_t P1 : 1;
\r
2848 __IO uint32_t P2 : 1;
\r
2849 } stc_gpio_pdor5_field_t;
\r
2851 typedef struct stc_gpio_pdor6_field
\r
2853 __IO uint32_t P0 : 1;
\r
2854 __IO uint32_t P1 : 1;
\r
2855 __IO uint32_t P2 : 1;
\r
2856 } stc_gpio_pdor6_field_t;
\r
2858 typedef struct stc_gpio_pdor8_field
\r
2860 __IO uint32_t P0 : 1;
\r
2861 __IO uint32_t P1 : 1;
\r
2862 } stc_gpio_pdor8_field_t;
\r
2864 typedef struct stc_gpio_pdore_field
\r
2866 __IO uint32_t P0 : 1;
\r
2867 uint32_t RESERVED1 : 1;
\r
2868 __IO uint32_t P2 : 1;
\r
2869 __IO uint32_t P3 : 1;
\r
2870 } stc_gpio_pdore_field_t;
\r
2872 typedef struct stc_gpio_ade_field
\r
2874 __IO uint32_t AN0 : 1;
\r
2875 __IO uint32_t AN1 : 1;
\r
2876 __IO uint32_t AN2 : 1;
\r
2877 __IO uint32_t AN3 : 1;
\r
2878 __IO uint32_t AN4 : 1;
\r
2879 __IO uint32_t AN5 : 1;
\r
2880 uint32_t RESERVED1 : 1;
\r
2881 __IO uint32_t AN7 : 1;
\r
2882 __IO uint32_t AN8 : 1;
\r
2883 __IO uint32_t AN9 : 1;
\r
2884 } stc_gpio_ade_field_t;
\r
2886 typedef struct stc_gpio_spsr_field
\r
2888 __IO uint32_t SUBXC : 1;
\r
2889 uint32_t RESERVED1 : 1;
\r
2890 __IO uint32_t MAINXC : 1;
\r
2891 uint32_t RESERVED2 : 1;
\r
2892 __IO uint32_t USB0C : 1;
\r
2893 } stc_gpio_spsr_field_t;
\r
2895 typedef struct stc_gpio_epfr00_field
\r
2897 __IO uint32_t NMIS : 1;
\r
2898 __IO uint32_t CROUTE0 : 1;
\r
2899 __IO uint32_t CROUTE1 : 1;
\r
2900 uint32_t RESERVED1 : 6;
\r
2901 __IO uint32_t USB0PE : 1;
\r
2902 uint32_t RESERVED2 : 6;
\r
2903 __IO uint32_t JTAGEN0B : 1;
\r
2904 __IO uint32_t JTAGEN1S : 1;
\r
2905 } stc_gpio_epfr00_field_t;
\r
2907 typedef struct stc_gpio_epfr01_field
\r
2909 __IO uint32_t RTO00E0 : 1;
\r
2910 __IO uint32_t RTO00E1 : 1;
\r
2911 __IO uint32_t RTO01E0 : 1;
\r
2912 __IO uint32_t RTO01E1 : 1;
\r
2913 __IO uint32_t RTO02E0 : 1;
\r
2914 __IO uint32_t RTO02E1 : 1;
\r
2915 __IO uint32_t RTO03E0 : 1;
\r
2916 __IO uint32_t RTO03E1 : 1;
\r
2917 __IO uint32_t RTO04E0 : 1;
\r
2918 __IO uint32_t RTO04E1 : 1;
\r
2919 __IO uint32_t RTO05E0 : 1;
\r
2920 __IO uint32_t RTO05E1 : 1;
\r
2921 __IO uint32_t DTTI0C : 1;
\r
2922 uint32_t RESERVED1 : 3;
\r
2923 __IO uint32_t DTTI0S0 : 1;
\r
2924 __IO uint32_t DTTI0S1 : 1;
\r
2925 __IO uint32_t FRCK0S0 : 1;
\r
2926 __IO uint32_t FRCK0S1 : 1;
\r
2927 __IO uint32_t IC00S0 : 1;
\r
2928 __IO uint32_t IC00S1 : 1;
\r
2929 __IO uint32_t IC00S2 : 1;
\r
2930 __IO uint32_t IC01S0 : 1;
\r
2931 __IO uint32_t IC01S1 : 1;
\r
2932 __IO uint32_t IC01S2 : 1;
\r
2933 __IO uint32_t IC02S0 : 1;
\r
2934 __IO uint32_t IC02S1 : 1;
\r
2935 __IO uint32_t IC02S2 : 1;
\r
2936 __IO uint32_t IC03S0 : 1;
\r
2937 __IO uint32_t IC03S1 : 1;
\r
2938 __IO uint32_t IC03S2 : 1;
\r
2939 } stc_gpio_epfr01_field_t;
\r
2941 typedef struct stc_gpio_epfr04_field
\r
2943 uint32_t RESERVED1 : 2;
\r
2944 __IO uint32_t TIOA0E0 : 1;
\r
2945 __IO uint32_t TIOA0E1 : 1;
\r
2946 __IO uint32_t TIOB0S0 : 1;
\r
2947 __IO uint32_t TIOB0S1 : 1;
\r
2948 uint32_t RESERVED2 : 2;
\r
2949 __IO uint32_t TIOA1S0 : 1;
\r
2950 __IO uint32_t TIOA1S1 : 1;
\r
2951 __IO uint32_t TIOA1E0 : 1;
\r
2952 __IO uint32_t TIOA1E1 : 1;
\r
2953 __IO uint32_t TIOB1S0 : 1;
\r
2954 __IO uint32_t TIOB1S1 : 1;
\r
2955 uint32_t RESERVED3 : 4;
\r
2956 __IO uint32_t TIOA2E0 : 1;
\r
2957 __IO uint32_t TIOA2E1 : 1;
\r
2958 __IO uint32_t TIOB2S0 : 1;
\r
2959 __IO uint32_t TIOB2S1 : 1;
\r
2960 uint32_t RESERVED4 : 2;
\r
2961 __IO uint32_t TIOA3S0 : 1;
\r
2962 __IO uint32_t TIOA3S1 : 1;
\r
2963 __IO uint32_t TIOA3E0 : 1;
\r
2964 __IO uint32_t TIOA3E1 : 1;
\r
2965 __IO uint32_t TIOB3S0 : 1;
\r
2966 __IO uint32_t TIOB3S1 : 1;
\r
2967 } stc_gpio_epfr04_field_t;
\r
2969 typedef struct stc_gpio_epfr05_field
\r
2971 uint32_t RESERVED1 : 2;
\r
2972 __IO uint32_t TIOA4E0 : 1;
\r
2973 __IO uint32_t TIOA4E1 : 1;
\r
2974 __IO uint32_t TIOB4S0 : 1;
\r
2975 __IO uint32_t TIOB4S1 : 1;
\r
2976 uint32_t RESERVED2 : 2;
\r
2977 __IO uint32_t TIOA5S0 : 1;
\r
2978 __IO uint32_t TIOA5S1 : 1;
\r
2979 __IO uint32_t TIOA5E0 : 1;
\r
2980 __IO uint32_t TIOA5E1 : 1;
\r
2981 __IO uint32_t TIOB5S0 : 1;
\r
2982 __IO uint32_t TIOB5S1 : 1;
\r
2983 uint32_t RESERVED3 : 4;
\r
2984 __IO uint32_t TIOA6E0 : 1;
\r
2985 __IO uint32_t TIOA6E1 : 1;
\r
2986 __IO uint32_t TIOB6S0 : 1;
\r
2987 __IO uint32_t TIOB6S1 : 1;
\r
2988 uint32_t RESERVED4 : 2;
\r
2989 __IO uint32_t TIOA7S0 : 1;
\r
2990 __IO uint32_t TIOA7S1 : 1;
\r
2991 __IO uint32_t TIOA7E0 : 1;
\r
2992 __IO uint32_t TIOA7E1 : 1;
\r
2993 __IO uint32_t TIOB7S0 : 1;
\r
2994 __IO uint32_t TIOB7S1 : 1;
\r
2995 } stc_gpio_epfr05_field_t;
\r
2997 typedef struct stc_gpio_epfr06_field
\r
2999 __IO uint32_t EINT00S0 : 1;
\r
3000 __IO uint32_t EINT00S1 : 1;
\r
3001 __IO uint32_t EINT01S0 : 1;
\r
3002 __IO uint32_t EINT01S1 : 1;
\r
3003 __IO uint32_t EINT02S0 : 1;
\r
3004 __IO uint32_t EINT02S1 : 1;
\r
3005 __IO uint32_t EINT03S0 : 1;
\r
3006 __IO uint32_t EINT03S1 : 1;
\r
3007 __IO uint32_t EINT04S0 : 1;
\r
3008 __IO uint32_t EINT04S1 : 1;
\r
3009 __IO uint32_t EINT05S0 : 1;
\r
3010 __IO uint32_t EINT05S1 : 1;
\r
3011 __IO uint32_t EINT06S0 : 1;
\r
3012 __IO uint32_t EINT06S1 : 1;
\r
3013 uint32_t RESERVED1 : 16;
\r
3014 __IO uint32_t EINT15S0 : 1;
\r
3015 __IO uint32_t EINT15S1 : 1;
\r
3016 } stc_gpio_epfr06_field_t;
\r
3018 typedef struct stc_gpio_epfr07_field
\r
3020 uint32_t RESERVED1 : 4;
\r
3021 __IO uint32_t SIN0S0 : 1;
\r
3022 __IO uint32_t SIN0S1 : 1;
\r
3023 __IO uint32_t SOT0B0 : 1;
\r
3024 __IO uint32_t SOT0B1 : 1;
\r
3025 __IO uint32_t SCK0B0 : 1;
\r
3026 __IO uint32_t SCK0B1 : 1;
\r
3027 __IO uint32_t SIN1S0 : 1;
\r
3028 __IO uint32_t SIN1S1 : 1;
\r
3029 __IO uint32_t SOT1B0 : 1;
\r
3030 __IO uint32_t SOT1B1 : 1;
\r
3031 __IO uint32_t SCK1B0 : 1;
\r
3032 __IO uint32_t SCK1B1 : 1;
\r
3033 __IO uint32_t SIN2S0 : 1;
\r
3034 __IO uint32_t SIN2S1 : 1;
\r
3035 __IO uint32_t SOT2B0 : 1;
\r
3036 __IO uint32_t SOT2B1 : 1;
\r
3037 __IO uint32_t SCK2B0 : 1;
\r
3038 __IO uint32_t SCK2B1 : 1;
\r
3039 __IO uint32_t SIN3S0 : 1;
\r
3040 __IO uint32_t SIN3S1 : 1;
\r
3041 __IO uint32_t SOT3B0 : 1;
\r
3042 __IO uint32_t SOT3B1 : 1;
\r
3043 __IO uint32_t SCK3B0 : 1;
\r
3044 __IO uint32_t SCK3B1 : 1;
\r
3045 } stc_gpio_epfr07_field_t;
\r
3047 typedef struct stc_gpio_epfr08_field
\r
3049 uint32_t RESERVED1 : 4;
\r
3050 __IO uint32_t SIN4S0 : 1;
\r
3051 __IO uint32_t SIN4S1 : 1;
\r
3052 __IO uint32_t SOT4B0 : 1;
\r
3053 __IO uint32_t SOT4B1 : 1;
\r
3054 __IO uint32_t SCK4B0 : 1;
\r
3055 __IO uint32_t SCK4B1 : 1;
\r
3056 __IO uint32_t SIN5S0 : 1;
\r
3057 __IO uint32_t SIN5S1 : 1;
\r
3058 __IO uint32_t SOT5B0 : 1;
\r
3059 __IO uint32_t SOT5B1 : 1;
\r
3060 __IO uint32_t SCK5B0 : 1;
\r
3061 __IO uint32_t SCK5B1 : 1;
\r
3062 __IO uint32_t SIN6S0 : 1;
\r
3063 __IO uint32_t SIN6S1 : 1;
\r
3064 __IO uint32_t SOT6B0 : 1;
\r
3065 __IO uint32_t SOT6B1 : 1;
\r
3066 __IO uint32_t SCK6B0 : 1;
\r
3067 __IO uint32_t SCK6B1 : 1;
\r
3068 __IO uint32_t SIN7S0 : 1;
\r
3069 __IO uint32_t SIN7S1 : 1;
\r
3070 __IO uint32_t SOT7B0 : 1;
\r
3071 __IO uint32_t SOT7B1 : 1;
\r
3072 __IO uint32_t SCK7B0 : 1;
\r
3073 __IO uint32_t SCK7B1 : 1;
\r
3074 } stc_gpio_epfr08_field_t;
\r
3076 typedef struct stc_gpio_epfr09_field
\r
3078 __IO uint32_t QAIN0S0 : 1;
\r
3079 __IO uint32_t QAIN0S1 : 1;
\r
3080 __IO uint32_t QBIN0S0 : 1;
\r
3081 __IO uint32_t QBIN0S1 : 1;
\r
3082 __IO uint32_t QZIN0S0 : 1;
\r
3083 __IO uint32_t QZIN0S1 : 1;
\r
3084 __IO uint32_t QAIN1S0 : 1;
\r
3085 __IO uint32_t QAIN1S1 : 1;
\r
3086 __IO uint32_t QBIN1S0 : 1;
\r
3087 __IO uint32_t QBIN1S1 : 1;
\r
3088 __IO uint32_t QZIN1S0 : 1;
\r
3089 __IO uint32_t QZIN1S1 : 1;
\r
3090 __IO uint32_t ADTRG0S0 : 1;
\r
3091 __IO uint32_t ADTRG0S1 : 1;
\r
3092 __IO uint32_t ADTRG0S2 : 1;
\r
3093 __IO uint32_t ADTRG0S3 : 1;
\r
3094 __IO uint32_t ADTRG1S0 : 1;
\r
3095 __IO uint32_t ADTRG1S1 : 1;
\r
3096 __IO uint32_t ADTRG1S2 : 1;
\r
3097 __IO uint32_t ADTRG1S3 : 1;
\r
3098 } stc_gpio_epfr09_field_t;
\r
3100 /******************************************************************************
\r
3102 ******************************************************************************/
\r
3103 /* LVD_MODULE register bit fields */
\r
3104 typedef struct stc_lvd_lvd_ctl_field
\r
3106 uint8_t RESERVED1 : 2;
\r
3107 __IO uint8_t SVHI0 : 1;
\r
3108 __IO uint8_t SVHI1 : 1;
\r
3109 __IO uint8_t SVHI2 : 1;
\r
3110 __IO uint8_t SVHI3 : 1;
\r
3111 uint8_t RESERVED2 : 1;
\r
3112 __IO uint8_t LVDIE : 1;
\r
3113 } stc_lvd_lvd_ctl_field_t;
\r
3115 typedef struct stc_lvd_lvd_str_field
\r
3117 uint8_t RESERVED1 : 7;
\r
3118 __IO uint8_t LVDIR : 1;
\r
3119 } stc_lvd_lvd_str_field_t;
\r
3121 typedef struct stc_lvd_lvd_clr_field
\r
3123 uint8_t RESERVED1 : 7;
\r
3124 __IO uint8_t LVDCL : 1;
\r
3125 } stc_lvd_lvd_clr_field_t;
\r
3127 typedef struct stc_lvd_lvd_str2_field
\r
3129 uint8_t RESERVED1 : 7;
\r
3130 __IO uint8_t LVDIRDY : 1;
\r
3131 } stc_lvd_lvd_str2_field_t;
\r
3133 /******************************************************************************
\r
3135 ******************************************************************************/
\r
3136 /* USBCLK register bit fields */
\r
3137 typedef struct stc_usbclk_uccr_field
\r
3139 __IO uint8_t UCEN : 1;
\r
3140 __IO uint8_t UCSEL : 1;
\r
3141 } stc_usbclk_uccr_field_t;
\r
3143 typedef struct stc_usbclk_upcr1_field
\r
3145 __IO uint8_t UPLLEN : 1;
\r
3146 __IO uint8_t UPINC : 1;
\r
3147 } stc_usbclk_upcr1_field_t;
\r
3149 typedef struct stc_usbclk_upcr2_field
\r
3151 __IO uint8_t UPOWT0 : 1;
\r
3152 __IO uint8_t UPOWT1 : 1;
\r
3153 __IO uint8_t UPOWT2 : 1;
\r
3154 } stc_usbclk_upcr2_field_t;
\r
3156 typedef struct stc_usbclk_upcr3_field
\r
3158 __IO uint8_t UPLLK0 : 1;
\r
3159 __IO uint8_t UPLLK1 : 1;
\r
3160 __IO uint8_t UPLLK2 : 1;
\r
3161 __IO uint8_t UPLLK3 : 1;
\r
3162 __IO uint8_t UPLLK4 : 1;
\r
3163 } stc_usbclk_upcr3_field_t;
\r
3165 typedef struct stc_usbclk_upcr4_field
\r
3167 __IO uint8_t UPLLN0 : 1;
\r
3168 __IO uint8_t UPLLN1 : 1;
\r
3169 __IO uint8_t UPLLN2 : 1;
\r
3170 __IO uint8_t UPLLN3 : 1;
\r
3171 __IO uint8_t UPLLN4 : 1;
\r
3172 __IO uint8_t UPLLN5 : 1;
\r
3173 __IO uint8_t UPLLN6 : 1;
\r
3174 } stc_usbclk_upcr4_field_t;
\r
3176 typedef struct stc_usbclk_up_str_field
\r
3178 __IO uint8_t UPRDY : 1;
\r
3179 } stc_usbclk_up_str_field_t;
\r
3181 typedef struct stc_usbclk_upint_enr_field
\r
3183 __IO uint8_t UPCSE : 1;
\r
3184 } stc_usbclk_upint_enr_field_t;
\r
3186 typedef struct stc_usbclk_upint_clr_field
\r
3188 __IO uint8_t UPCSC : 1;
\r
3189 } stc_usbclk_upint_clr_field_t;
\r
3191 typedef struct stc_usbclk_upint_str_field
\r
3193 __IO uint8_t UPCSI : 1;
\r
3194 } stc_usbclk_upint_str_field_t;
\r
3196 typedef struct stc_usbclk_upcr5_field
\r
3198 __IO uint8_t UPLLM0 : 1;
\r
3199 __IO uint8_t UPLLM1 : 1;
\r
3200 __IO uint8_t UPLLM2 : 1;
\r
3201 __IO uint8_t UPLLM3 : 1;
\r
3202 } stc_usbclk_upcr5_field_t;
\r
3204 typedef struct stc_usbclk_usben_field
\r
3206 __IO uint8_t USBEN : 1;
\r
3207 } stc_usbclk_usben_field_t;
\r
3209 /******************************************************************************
\r
3210 * MFS03_UART_MODULE
\r
3211 ******************************************************************************/
\r
3212 /* MFS03_UART_MODULE register bit fields */
\r
3213 typedef struct stc_mfs03_uart_smr_field
\r
3215 __IO uint8_t SOE : 1;
\r
3216 uint8_t RESERVED1 : 1;
\r
3217 __IO uint8_t BDS : 1;
\r
3218 __IO uint8_t SBL : 1;
\r
3219 __IO uint8_t WUCR : 1;
\r
3220 __IO uint8_t MD0 : 1;
\r
3221 __IO uint8_t MD1 : 1;
\r
3222 __IO uint8_t MD2 : 1;
\r
3223 } stc_mfs03_uart_smr_field_t;
\r
3225 typedef struct stc_mfs03_uart_scr_field
\r
3227 __IO uint8_t TXE : 1;
\r
3228 __IO uint8_t RXE : 1;
\r
3229 __IO uint8_t TBIE : 1;
\r
3230 __IO uint8_t TIE : 1;
\r
3231 __IO uint8_t RIE : 1;
\r
3232 uint8_t RESERVED1 : 2;
\r
3233 __IO uint8_t UPCL : 1;
\r
3234 } stc_mfs03_uart_scr_field_t;
\r
3236 typedef struct stc_mfs03_uart_escr_field
\r
3238 __IO uint8_t L0 : 1;
\r
3239 __IO uint8_t L1 : 1;
\r
3240 __IO uint8_t L2 : 1;
\r
3241 __IO uint8_t P : 1;
\r
3242 __IO uint8_t PEN : 1;
\r
3243 __IO uint8_t INV : 1;
\r
3244 __IO uint8_t ESBL : 1;
\r
3245 __IO uint8_t FLWEN : 1;
\r
3246 } stc_mfs03_uart_escr_field_t;
\r
3248 typedef struct stc_mfs03_uart_ssr_field
\r
3250 __IO uint8_t TBI : 1;
\r
3251 __IO uint8_t TDRE : 1;
\r
3252 __IO uint8_t RDRF : 1;
\r
3253 __IO uint8_t ORE : 1;
\r
3254 __IO uint8_t FRE : 1;
\r
3255 __IO uint8_t PE : 1;
\r
3256 uint8_t RESERVED1 : 1;
\r
3257 __IO uint8_t REC : 1;
\r
3258 } stc_mfs03_uart_ssr_field_t;
\r
3260 typedef struct stc_mfs03_uart_rdr_field
\r
3262 uint16_t RESERVED1 : 8;
\r
3263 __IO uint16_t AD : 1;
\r
3264 } stc_mfs03_uart_rdr_field_t;
\r
3266 typedef struct stc_mfs03_uart_tdr_field
\r
3268 uint16_t RESERVED1 : 8;
\r
3269 __IO uint16_t AD : 1;
\r
3270 } stc_mfs03_uart_tdr_field_t;
\r
3272 typedef struct stc_mfs03_uart_bgr_field
\r
3274 uint16_t RESERVED1 : 15;
\r
3275 __IO uint16_t EXT : 1;
\r
3276 } stc_mfs03_uart_bgr_field_t;
\r
3278 typedef struct stc_mfs03_uart_bgr1_field
\r
3280 uint8_t RESERVED1 : 7;
\r
3281 __IO uint8_t EXT : 1;
\r
3282 } stc_mfs03_uart_bgr1_field_t;
\r
3284 /******************************************************************************
\r
3285 * MFS03_CSIO_MODULE
\r
3286 ******************************************************************************/
\r
3287 /* MFS03_CSIO_MODULE register bit fields */
\r
3288 typedef struct stc_mfs03_csio_smr_field
\r
3290 __IO uint8_t SOE : 1;
\r
3291 __IO uint8_t SCKE : 1;
\r
3292 __IO uint8_t BDS : 1;
\r
3293 __IO uint8_t SCINV : 1;
\r
3294 __IO uint8_t WUCR : 1;
\r
3295 __IO uint8_t MD0 : 1;
\r
3296 __IO uint8_t MD1 : 1;
\r
3297 __IO uint8_t MD2 : 1;
\r
3298 } stc_mfs03_csio_smr_field_t;
\r
3300 typedef struct stc_mfs03_csio_scr_field
\r
3302 __IO uint8_t TXE : 1;
\r
3303 __IO uint8_t RXE : 1;
\r
3304 __IO uint8_t TBIE : 1;
\r
3305 __IO uint8_t TIE : 1;
\r
3306 __IO uint8_t RIE : 1;
\r
3307 __IO uint8_t SPI : 1;
\r
3308 __IO uint8_t MS : 1;
\r
3309 __IO uint8_t UPCL : 1;
\r
3310 } stc_mfs03_csio_scr_field_t;
\r
3312 typedef struct stc_mfs03_csio_escr_field
\r
3314 __IO uint8_t L0 : 1;
\r
3315 __IO uint8_t L1 : 1;
\r
3316 __IO uint8_t L2 : 1;
\r
3317 __IO uint8_t WT0 : 1;
\r
3318 __IO uint8_t WT1 : 1;
\r
3319 uint8_t RESERVED1 : 2;
\r
3320 __IO uint8_t SOP : 1;
\r
3321 } stc_mfs03_csio_escr_field_t;
\r
3323 typedef struct stc_mfs03_csio_ssr_field
\r
3325 __IO uint8_t TBI : 1;
\r
3326 __IO uint8_t TDRE : 1;
\r
3327 __IO uint8_t RDRF : 1;
\r
3328 __IO uint8_t ORE : 1;
\r
3329 uint8_t RESERVED1 : 3;
\r
3330 __IO uint8_t REC : 1;
\r
3331 } stc_mfs03_csio_ssr_field_t;
\r
3333 /******************************************************************************
\r
3334 * MFS03_LIN_MODULE
\r
3335 ******************************************************************************/
\r
3336 /* MFS03_LIN_MODULE register bit fields */
\r
3337 typedef struct stc_mfs03_lin_smr_field
\r
3339 __IO uint8_t SOE : 1;
\r
3340 uint8_t RESERVED1 : 2;
\r
3341 __IO uint8_t SBL : 1;
\r
3342 __IO uint8_t WUCR : 1;
\r
3343 __IO uint8_t MD0 : 1;
\r
3344 __IO uint8_t MD1 : 1;
\r
3345 __IO uint8_t MD2 : 1;
\r
3346 } stc_mfs03_lin_smr_field_t;
\r
3348 typedef struct stc_mfs03_lin_scr_field
\r
3350 __IO uint8_t TXE : 1;
\r
3351 __IO uint8_t RXE : 1;
\r
3352 __IO uint8_t TBIE : 1;
\r
3353 __IO uint8_t TIE : 1;
\r
3354 __IO uint8_t RIE : 1;
\r
3355 __IO uint8_t LBR : 1;
\r
3356 __IO uint8_t MS : 1;
\r
3357 __IO uint8_t UPCL : 1;
\r
3358 } stc_mfs03_lin_scr_field_t;
\r
3360 typedef struct stc_mfs03_lin_escr_field
\r
3362 __IO uint8_t DEL0 : 1;
\r
3363 __IO uint8_t DEL1 : 1;
\r
3364 __IO uint8_t LBL0 : 1;
\r
3365 __IO uint8_t LBL1 : 1;
\r
3366 __IO uint8_t LBIE : 1;
\r
3367 uint8_t RESERVED1 : 1;
\r
3368 __IO uint8_t ESBL : 1;
\r
3369 } stc_mfs03_lin_escr_field_t;
\r
3371 typedef struct stc_mfs03_lin_ssr_field
\r
3373 __IO uint8_t TBI : 1;
\r
3374 __IO uint8_t TDRE : 1;
\r
3375 __IO uint8_t RDRF : 1;
\r
3376 __IO uint8_t ORE : 1;
\r
3377 __IO uint8_t FRE : 1;
\r
3378 __IO uint8_t LBD : 1;
\r
3379 uint8_t RESERVED1 : 1;
\r
3380 __IO uint8_t REC : 1;
\r
3381 } stc_mfs03_lin_ssr_field_t;
\r
3383 typedef struct stc_mfs03_lin_bgr_field
\r
3385 uint16_t RESERVED1 : 15;
\r
3386 __IO uint16_t EXT : 1;
\r
3387 } stc_mfs03_lin_bgr_field_t;
\r
3389 typedef struct stc_mfs03_lin_bgr1_field
\r
3391 uint8_t RESERVED1 : 7;
\r
3392 __IO uint8_t EXT : 1;
\r
3393 } stc_mfs03_lin_bgr1_field_t;
\r
3395 /******************************************************************************
\r
3396 * MFS03_I2C_MODULE
\r
3397 ******************************************************************************/
\r
3398 /* MFS03_I2C_MODULE register bit fields */
\r
3399 typedef struct stc_mfs03_i2c_smr_field
\r
3401 __IO uint8_t ITST0 : 1;
\r
3402 __IO uint8_t ITST1 : 1;
\r
3403 __IO uint8_t TIE : 1;
\r
3404 __IO uint8_t RIE : 1;
\r
3405 __IO uint8_t WUCR : 1;
\r
3406 __IO uint8_t MD0 : 1;
\r
3407 __IO uint8_t MD1 : 1;
\r
3408 __IO uint8_t MD2 : 1;
\r
3409 } stc_mfs03_i2c_smr_field_t;
\r
3411 typedef struct stc_mfs03_i2c_ibcr_field
\r
3413 __IO uint8_t INT : 1;
\r
3414 __IO uint8_t BER : 1;
\r
3415 __IO uint8_t INTE : 1;
\r
3416 __IO uint8_t CNDE : 1;
\r
3417 __IO uint8_t WSEL : 1;
\r
3418 __IO uint8_t ACKE : 1;
\r
3419 __IO uint8_t SCC : 1;
\r
3420 __IO uint8_t MSS : 1;
\r
3421 } stc_mfs03_i2c_ibcr_field_t;
\r
3423 typedef struct stc_mfs03_i2c_ibsr_field
\r
3425 __IO uint8_t BB : 1;
\r
3426 __IO uint8_t SPC : 1;
\r
3427 __IO uint8_t RSC : 1;
\r
3428 __IO uint8_t AL : 1;
\r
3429 __IO uint8_t TRX : 1;
\r
3430 __IO uint8_t RSA : 1;
\r
3431 __IO uint8_t RACK : 1;
\r
3432 __IO uint8_t FBT : 1;
\r
3433 } stc_mfs03_i2c_ibsr_field_t;
\r
3435 typedef struct stc_mfs03_i2c_ssr_field
\r
3437 __IO uint8_t TBI : 1;
\r
3438 __IO uint8_t TDRE : 1;
\r
3439 __IO uint8_t RDRF : 1;
\r
3440 __IO uint8_t ORE : 1;
\r
3441 __IO uint8_t TBIE : 1;
\r
3442 __IO uint8_t DMA : 1;
\r
3443 __IO uint8_t TSET : 1;
\r
3444 __IO uint8_t REC : 1;
\r
3445 } stc_mfs03_i2c_ssr_field_t;
\r
3447 typedef struct stc_mfs03_i2c_isba_field
\r
3449 __IO uint8_t SA0 : 1;
\r
3450 __IO uint8_t SA1 : 1;
\r
3451 __IO uint8_t SA2 : 1;
\r
3452 __IO uint8_t SA3 : 1;
\r
3453 __IO uint8_t SA4 : 1;
\r
3454 __IO uint8_t SA5 : 1;
\r
3455 __IO uint8_t SA6 : 1;
\r
3456 __IO uint8_t SAEN : 1;
\r
3457 } stc_mfs03_i2c_isba_field_t;
\r
3459 typedef struct stc_mfs03_i2c_ismk_field
\r
3461 __IO uint8_t SM0 : 1;
\r
3462 __IO uint8_t SM1 : 1;
\r
3463 __IO uint8_t SM2 : 1;
\r
3464 __IO uint8_t SM3 : 1;
\r
3465 __IO uint8_t SM4 : 1;
\r
3466 __IO uint8_t SM5 : 1;
\r
3467 __IO uint8_t SM6 : 1;
\r
3468 __IO uint8_t EN : 1;
\r
3469 } stc_mfs03_i2c_ismk_field_t;
\r
3471 /******************************************************************************
\r
3472 * MFS47_UART_MODULE
\r
3473 ******************************************************************************/
\r
3474 /* MFS47_UART_MODULE register bit fields */
\r
3475 typedef struct stc_mfs47_uart_smr_field
\r
3477 __IO uint8_t SOE : 1;
\r
3478 uint8_t RESERVED1 : 1;
\r
3479 __IO uint8_t BDS : 1;
\r
3480 __IO uint8_t SBL : 1;
\r
3481 __IO uint8_t WUCR : 1;
\r
3482 __IO uint8_t MD0 : 1;
\r
3483 __IO uint8_t MD1 : 1;
\r
3484 __IO uint8_t MD2 : 1;
\r
3485 } stc_mfs47_uart_smr_field_t;
\r
3487 typedef struct stc_mfs47_uart_scr_field
\r
3489 __IO uint8_t TXE : 1;
\r
3490 __IO uint8_t RXE : 1;
\r
3491 __IO uint8_t TBIE : 1;
\r
3492 __IO uint8_t TIE : 1;
\r
3493 __IO uint8_t RIE : 1;
\r
3494 uint8_t RESERVED1 : 2;
\r
3495 __IO uint8_t UPCL : 1;
\r
3496 } stc_mfs47_uart_scr_field_t;
\r
3498 typedef struct stc_mfs47_uart_escr_field
\r
3500 __IO uint8_t L0 : 1;
\r
3501 __IO uint8_t L1 : 1;
\r
3502 __IO uint8_t L2 : 1;
\r
3503 __IO uint8_t P : 1;
\r
3504 __IO uint8_t PEN : 1;
\r
3505 __IO uint8_t INV : 1;
\r
3506 __IO uint8_t ESBL : 1;
\r
3507 __IO uint8_t FLWEN : 1;
\r
3508 } stc_mfs47_uart_escr_field_t;
\r
3510 typedef struct stc_mfs47_uart_ssr_field
\r
3512 __IO uint8_t TBI : 1;
\r
3513 __IO uint8_t TDRE : 1;
\r
3514 __IO uint8_t RDRF : 1;
\r
3515 __IO uint8_t ORE : 1;
\r
3516 __IO uint8_t FRE : 1;
\r
3517 __IO uint8_t PE : 1;
\r
3518 uint8_t RESERVED1 : 1;
\r
3519 __IO uint8_t REC : 1;
\r
3520 } stc_mfs47_uart_ssr_field_t;
\r
3522 typedef struct stc_mfs47_uart_rdr_field
\r
3524 uint16_t RESERVED1 : 8;
\r
3525 __IO uint16_t AD : 1;
\r
3526 } stc_mfs47_uart_rdr_field_t;
\r
3528 typedef struct stc_mfs47_uart_tdr_field
\r
3530 uint16_t RESERVED1 : 8;
\r
3531 __IO uint16_t AD : 1;
\r
3532 } stc_mfs47_uart_tdr_field_t;
\r
3534 typedef struct stc_mfs47_uart_bgr_field
\r
3536 uint16_t RESERVED1 : 15;
\r
3537 __IO uint16_t EXT : 1;
\r
3538 } stc_mfs47_uart_bgr_field_t;
\r
3540 typedef struct stc_mfs47_uart_bgr1_field
\r
3542 uint8_t RESERVED1 : 7;
\r
3543 __IO uint8_t EXT : 1;
\r
3544 } stc_mfs47_uart_bgr1_field_t;
\r
3546 typedef struct stc_mfs47_uart_fcr_field
\r
3548 __IO uint16_t FE1 : 1;
\r
3549 __IO uint16_t FE2 : 1;
\r
3550 __IO uint16_t FCL1 : 1;
\r
3551 __IO uint16_t FCL2 : 1;
\r
3552 __IO uint16_t FSET : 1;
\r
3553 __IO uint16_t FLD : 1;
\r
3554 __IO uint16_t FLST : 1;
\r
3555 uint16_t RESERVED1 : 1;
\r
3556 __IO uint16_t FSEL : 1;
\r
3557 __IO uint16_t FTIE : 1;
\r
3558 __IO uint16_t FDRQ : 1;
\r
3559 __IO uint16_t FRIE : 1;
\r
3560 __IO uint16_t FLSTE : 1;
\r
3561 uint16_t RESERVED2 : 1;
\r
3562 __IO uint16_t FTST0 : 1;
\r
3563 __IO uint16_t FTST1 : 1;
\r
3564 } stc_mfs47_uart_fcr_field_t;
\r
3566 typedef struct stc_mfs47_uart_fcr0_field
\r
3568 __IO uint8_t FE1 : 1;
\r
3569 __IO uint8_t FE2 : 1;
\r
3570 __IO uint8_t FCL1 : 1;
\r
3571 __IO uint8_t FCL2 : 1;
\r
3572 __IO uint8_t FSET : 1;
\r
3573 __IO uint8_t FLD : 1;
\r
3574 __IO uint8_t FLST : 1;
\r
3575 } stc_mfs47_uart_fcr0_field_t;
\r
3577 typedef struct stc_mfs47_uart_fcr1_field
\r
3579 __IO uint8_t FSEL : 1;
\r
3580 __IO uint8_t FTIE : 1;
\r
3581 __IO uint8_t FDRQ : 1;
\r
3582 __IO uint8_t FRIE : 1;
\r
3583 __IO uint8_t FLSTE : 1;
\r
3584 uint8_t RESERVED1 : 1;
\r
3585 __IO uint8_t FTST0 : 1;
\r
3586 __IO uint8_t FTST1 : 1;
\r
3587 } stc_mfs47_uart_fcr1_field_t;
\r
3589 typedef struct stc_mfs47_uart_fbyte_field
\r
3591 __IO uint16_t FD0 : 1;
\r
3592 __IO uint16_t FD1 : 1;
\r
3593 __IO uint16_t FD2 : 1;
\r
3594 __IO uint16_t FD3 : 1;
\r
3595 __IO uint16_t FD4 : 1;
\r
3596 __IO uint16_t FD5 : 1;
\r
3597 __IO uint16_t FD6 : 1;
\r
3598 __IO uint16_t FD7 : 1;
\r
3599 __IO uint16_t FD8 : 1;
\r
3600 __IO uint16_t FD9 : 1;
\r
3601 __IO uint16_t FD10 : 1;
\r
3602 __IO uint16_t FD11 : 1;
\r
3603 __IO uint16_t FD12 : 1;
\r
3604 __IO uint16_t FD13 : 1;
\r
3605 __IO uint16_t FD14 : 1;
\r
3606 __IO uint16_t FD15 : 1;
\r
3607 } stc_mfs47_uart_fbyte_field_t;
\r
3609 typedef struct stc_mfs47_uart_fbyte1_field
\r
3611 __IO uint8_t FD0 : 1;
\r
3612 __IO uint8_t FD1 : 1;
\r
3613 __IO uint8_t FD2 : 1;
\r
3614 __IO uint8_t FD3 : 1;
\r
3615 __IO uint8_t FD4 : 1;
\r
3616 __IO uint8_t FD5 : 1;
\r
3617 __IO uint8_t FD6 : 1;
\r
3618 __IO uint8_t FD7 : 1;
\r
3619 } stc_mfs47_uart_fbyte1_field_t;
\r
3621 typedef struct stc_mfs47_uart_fbyte2_field
\r
3623 __IO uint8_t FD8 : 1;
\r
3624 __IO uint8_t FD9 : 1;
\r
3625 __IO uint8_t FD10 : 1;
\r
3626 __IO uint8_t FD11 : 1;
\r
3627 __IO uint8_t FD12 : 1;
\r
3628 __IO uint8_t FD13 : 1;
\r
3629 __IO uint8_t FD14 : 1;
\r
3630 __IO uint8_t FD15 : 1;
\r
3631 } stc_mfs47_uart_fbyte2_field_t;
\r
3633 /******************************************************************************
\r
3634 * MFS47_CSIO_MODULE
\r
3635 ******************************************************************************/
\r
3636 /* MFS47_CSIO_MODULE register bit fields */
\r
3637 typedef struct stc_mfs47_csio_smr_field
\r
3639 __IO uint8_t SOE : 1;
\r
3640 __IO uint8_t SCKE : 1;
\r
3641 __IO uint8_t BDS : 1;
\r
3642 __IO uint8_t SCINV : 1;
\r
3643 __IO uint8_t WUCR : 1;
\r
3644 __IO uint8_t MD0 : 1;
\r
3645 __IO uint8_t MD1 : 1;
\r
3646 __IO uint8_t MD2 : 1;
\r
3647 } stc_mfs47_csio_smr_field_t;
\r
3649 typedef struct stc_mfs47_csio_scr_field
\r
3651 __IO uint8_t TXE : 1;
\r
3652 __IO uint8_t RXE : 1;
\r
3653 __IO uint8_t TBIE : 1;
\r
3654 __IO uint8_t TIE : 1;
\r
3655 __IO uint8_t RIE : 1;
\r
3656 __IO uint8_t SPI : 1;
\r
3657 __IO uint8_t MS : 1;
\r
3658 __IO uint8_t UPCL : 1;
\r
3659 } stc_mfs47_csio_scr_field_t;
\r
3661 typedef struct stc_mfs47_csio_escr_field
\r
3663 __IO uint8_t L0 : 1;
\r
3664 __IO uint8_t L1 : 1;
\r
3665 __IO uint8_t L2 : 1;
\r
3666 __IO uint8_t WT0 : 1;
\r
3667 __IO uint8_t WT1 : 1;
\r
3668 uint8_t RESERVED1 : 2;
\r
3669 __IO uint8_t SOP : 1;
\r
3670 } stc_mfs47_csio_escr_field_t;
\r
3672 typedef struct stc_mfs47_csio_ssr_field
\r
3674 __IO uint8_t TBI : 1;
\r
3675 __IO uint8_t TDRE : 1;
\r
3676 __IO uint8_t RDRF : 1;
\r
3677 __IO uint8_t ORE : 1;
\r
3678 uint8_t RESERVED1 : 3;
\r
3679 __IO uint8_t REC : 1;
\r
3680 } stc_mfs47_csio_ssr_field_t;
\r
3682 typedef struct stc_mfs47_csio_fcr_field
\r
3684 __IO uint16_t FE1 : 1;
\r
3685 __IO uint16_t FE2 : 1;
\r
3686 __IO uint16_t FCL1 : 1;
\r
3687 __IO uint16_t FCL2 : 1;
\r
3688 __IO uint16_t FSET : 1;
\r
3689 __IO uint16_t FLD : 1;
\r
3690 __IO uint16_t FLST : 1;
\r
3691 uint16_t RESERVED1 : 1;
\r
3692 __IO uint16_t FSEL : 1;
\r
3693 __IO uint16_t FTIE : 1;
\r
3694 __IO uint16_t FDRQ : 1;
\r
3695 __IO uint16_t FRIE : 1;
\r
3696 __IO uint16_t FLSTE : 1;
\r
3697 uint16_t RESERVED2 : 1;
\r
3698 __IO uint16_t FTST0 : 1;
\r
3699 __IO uint16_t FTST1 : 1;
\r
3700 } stc_mfs47_csio_fcr_field_t;
\r
3702 typedef struct stc_mfs47_csio_fcr0_field
\r
3704 __IO uint8_t FE1 : 1;
\r
3705 __IO uint8_t FE2 : 1;
\r
3706 __IO uint8_t FCL1 : 1;
\r
3707 __IO uint8_t FCL2 : 1;
\r
3708 __IO uint8_t FSET : 1;
\r
3709 __IO uint8_t FLD : 1;
\r
3710 __IO uint8_t FLST : 1;
\r
3711 } stc_mfs47_csio_fcr0_field_t;
\r
3713 typedef struct stc_mfs47_csio_fcr1_field
\r
3715 __IO uint8_t FSEL : 1;
\r
3716 __IO uint8_t FTIE : 1;
\r
3717 __IO uint8_t FDRQ : 1;
\r
3718 __IO uint8_t FRIE : 1;
\r
3719 __IO uint8_t FLSTE : 1;
\r
3720 uint8_t RESERVED1 : 1;
\r
3721 __IO uint8_t FTST0 : 1;
\r
3722 __IO uint8_t FTST1 : 1;
\r
3723 } stc_mfs47_csio_fcr1_field_t;
\r
3725 typedef struct stc_mfs47_csio_fbyte_field
\r
3727 __IO uint16_t FD0 : 1;
\r
3728 __IO uint16_t FD1 : 1;
\r
3729 __IO uint16_t FD2 : 1;
\r
3730 __IO uint16_t FD3 : 1;
\r
3731 __IO uint16_t FD4 : 1;
\r
3732 __IO uint16_t FD5 : 1;
\r
3733 __IO uint16_t FD6 : 1;
\r
3734 __IO uint16_t FD7 : 1;
\r
3735 __IO uint16_t FD8 : 1;
\r
3736 __IO uint16_t FD9 : 1;
\r
3737 __IO uint16_t FD10 : 1;
\r
3738 __IO uint16_t FD11 : 1;
\r
3739 __IO uint16_t FD12 : 1;
\r
3740 __IO uint16_t FD13 : 1;
\r
3741 __IO uint16_t FD14 : 1;
\r
3742 __IO uint16_t FD15 : 1;
\r
3743 } stc_mfs47_csio_fbyte_field_t;
\r
3745 typedef struct stc_mfs47_csio_fbyte1_field
\r
3747 __IO uint8_t FD0 : 1;
\r
3748 __IO uint8_t FD1 : 1;
\r
3749 __IO uint8_t FD2 : 1;
\r
3750 __IO uint8_t FD3 : 1;
\r
3751 __IO uint8_t FD4 : 1;
\r
3752 __IO uint8_t FD5 : 1;
\r
3753 __IO uint8_t FD6 : 1;
\r
3754 __IO uint8_t FD7 : 1;
\r
3755 } stc_mfs47_csio_fbyte1_field_t;
\r
3757 typedef struct stc_mfs47_csio_fbyte2_field
\r
3759 __IO uint8_t FD8 : 1;
\r
3760 __IO uint8_t FD9 : 1;
\r
3761 __IO uint8_t FD10 : 1;
\r
3762 __IO uint8_t FD11 : 1;
\r
3763 __IO uint8_t FD12 : 1;
\r
3764 __IO uint8_t FD13 : 1;
\r
3765 __IO uint8_t FD14 : 1;
\r
3766 __IO uint8_t FD15 : 1;
\r
3767 } stc_mfs47_csio_fbyte2_field_t;
\r
3769 /******************************************************************************
\r
3770 * MFS47_LIN_MODULE
\r
3771 ******************************************************************************/
\r
3772 /* MFS47_LIN_MODULE register bit fields */
\r
3773 typedef struct stc_mfs47_lin_smr_field
\r
3775 __IO uint8_t SOE : 1;
\r
3776 uint8_t RESERVED1 : 2;
\r
3777 __IO uint8_t SBL : 1;
\r
3778 __IO uint8_t WUCR : 1;
\r
3779 __IO uint8_t MD0 : 1;
\r
3780 __IO uint8_t MD1 : 1;
\r
3781 __IO uint8_t MD2 : 1;
\r
3782 } stc_mfs47_lin_smr_field_t;
\r
3784 typedef struct stc_mfs47_lin_scr_field
\r
3786 __IO uint8_t TXE : 1;
\r
3787 __IO uint8_t RXE : 1;
\r
3788 __IO uint8_t TBIE : 1;
\r
3789 __IO uint8_t TIE : 1;
\r
3790 __IO uint8_t RIE : 1;
\r
3791 __IO uint8_t LBR : 1;
\r
3792 __IO uint8_t MS : 1;
\r
3793 __IO uint8_t UPCL : 1;
\r
3794 } stc_mfs47_lin_scr_field_t;
\r
3796 typedef struct stc_mfs47_lin_escr_field
\r
3798 __IO uint8_t DEL0 : 1;
\r
3799 __IO uint8_t DEL1 : 1;
\r
3800 __IO uint8_t LBL0 : 1;
\r
3801 __IO uint8_t LBL1 : 1;
\r
3802 __IO uint8_t LBIE : 1;
\r
3803 uint8_t RESERVED1 : 1;
\r
3804 __IO uint8_t ESBL : 1;
\r
3805 } stc_mfs47_lin_escr_field_t;
\r
3807 typedef struct stc_mfs47_lin_ssr_field
\r
3809 __IO uint8_t TBI : 1;
\r
3810 __IO uint8_t TDRE : 1;
\r
3811 __IO uint8_t RDRF : 1;
\r
3812 __IO uint8_t ORE : 1;
\r
3813 __IO uint8_t FRE : 1;
\r
3814 __IO uint8_t LBD : 1;
\r
3815 uint8_t RESERVED1 : 1;
\r
3816 __IO uint8_t REC : 1;
\r
3817 } stc_mfs47_lin_ssr_field_t;
\r
3819 typedef struct stc_mfs47_lin_bgr_field
\r
3821 uint16_t RESERVED1 : 15;
\r
3822 __IO uint16_t EXT : 1;
\r
3823 } stc_mfs47_lin_bgr_field_t;
\r
3825 typedef struct stc_mfs47_lin_bgr1_field
\r
3827 uint8_t RESERVED1 : 7;
\r
3828 __IO uint8_t EXT : 1;
\r
3829 } stc_mfs47_lin_bgr1_field_t;
\r
3831 typedef struct stc_mfs47_lin_fcr_field
\r
3833 __IO uint16_t FE1 : 1;
\r
3834 __IO uint16_t FE2 : 1;
\r
3835 __IO uint16_t FCL1 : 1;
\r
3836 __IO uint16_t FCL2 : 1;
\r
3837 __IO uint16_t FSET : 1;
\r
3838 __IO uint16_t FLD : 1;
\r
3839 __IO uint16_t FLST : 1;
\r
3840 uint16_t RESERVED1 : 1;
\r
3841 __IO uint16_t FSEL : 1;
\r
3842 __IO uint16_t FTIE : 1;
\r
3843 __IO uint16_t FDRQ : 1;
\r
3844 __IO uint16_t FRIE : 1;
\r
3845 __IO uint16_t FLSTE : 1;
\r
3846 uint16_t RESERVED2 : 1;
\r
3847 __IO uint16_t FTST0 : 1;
\r
3848 __IO uint16_t FTST1 : 1;
\r
3849 } stc_mfs47_lin_fcr_field_t;
\r
3851 typedef struct stc_mfs47_lin_fcr0_field
\r
3853 __IO uint8_t FE1 : 1;
\r
3854 __IO uint8_t FE2 : 1;
\r
3855 __IO uint8_t FCL1 : 1;
\r
3856 __IO uint8_t FCL2 : 1;
\r
3857 __IO uint8_t FSET : 1;
\r
3858 __IO uint8_t FLD : 1;
\r
3859 __IO uint8_t FLST : 1;
\r
3860 } stc_mfs47_lin_fcr0_field_t;
\r
3862 typedef struct stc_mfs47_lin_fcr1_field
\r
3864 __IO uint8_t FSEL : 1;
\r
3865 __IO uint8_t FTIE : 1;
\r
3866 __IO uint8_t FDRQ : 1;
\r
3867 __IO uint8_t FRIE : 1;
\r
3868 __IO uint8_t FLSTE : 1;
\r
3869 uint8_t RESERVED1 : 1;
\r
3870 __IO uint8_t FTST0 : 1;
\r
3871 __IO uint8_t FTST1 : 1;
\r
3872 } stc_mfs47_lin_fcr1_field_t;
\r
3874 typedef struct stc_mfs47_lin_fbyte_field
\r
3876 __IO uint16_t FD0 : 1;
\r
3877 __IO uint16_t FD1 : 1;
\r
3878 __IO uint16_t FD2 : 1;
\r
3879 __IO uint16_t FD3 : 1;
\r
3880 __IO uint16_t FD4 : 1;
\r
3881 __IO uint16_t FD5 : 1;
\r
3882 __IO uint16_t FD6 : 1;
\r
3883 __IO uint16_t FD7 : 1;
\r
3884 __IO uint16_t FD8 : 1;
\r
3885 __IO uint16_t FD9 : 1;
\r
3886 __IO uint16_t FD10 : 1;
\r
3887 __IO uint16_t FD11 : 1;
\r
3888 __IO uint16_t FD12 : 1;
\r
3889 __IO uint16_t FD13 : 1;
\r
3890 __IO uint16_t FD14 : 1;
\r
3891 __IO uint16_t FD15 : 1;
\r
3892 } stc_mfs47_lin_fbyte_field_t;
\r
3894 typedef struct stc_mfs47_lin_fbyte1_field
\r
3896 __IO uint8_t FD0 : 1;
\r
3897 __IO uint8_t FD1 : 1;
\r
3898 __IO uint8_t FD2 : 1;
\r
3899 __IO uint8_t FD3 : 1;
\r
3900 __IO uint8_t FD4 : 1;
\r
3901 __IO uint8_t FD5 : 1;
\r
3902 __IO uint8_t FD6 : 1;
\r
3903 __IO uint8_t FD7 : 1;
\r
3904 } stc_mfs47_lin_fbyte1_field_t;
\r
3906 typedef struct stc_mfs47_lin_fbyte2_field
\r
3908 __IO uint8_t FD8 : 1;
\r
3909 __IO uint8_t FD9 : 1;
\r
3910 __IO uint8_t FD10 : 1;
\r
3911 __IO uint8_t FD11 : 1;
\r
3912 __IO uint8_t FD12 : 1;
\r
3913 __IO uint8_t FD13 : 1;
\r
3914 __IO uint8_t FD14 : 1;
\r
3915 __IO uint8_t FD15 : 1;
\r
3916 } stc_mfs47_lin_fbyte2_field_t;
\r
3918 /******************************************************************************
\r
3919 * MFS47_I2C_MODULE
\r
3920 ******************************************************************************/
\r
3921 /* MFS47_I2C_MODULE register bit fields */
\r
3922 typedef struct stc_mfs47_i2c_smr_field
\r
3924 __IO uint8_t ITST0 : 1;
\r
3925 __IO uint8_t ITST1 : 1;
\r
3926 __IO uint8_t TIE : 1;
\r
3927 __IO uint8_t RIE : 1;
\r
3928 __IO uint8_t WUCR : 1;
\r
3929 __IO uint8_t MD0 : 1;
\r
3930 __IO uint8_t MD1 : 1;
\r
3931 __IO uint8_t MD2 : 1;
\r
3932 } stc_mfs47_i2c_smr_field_t;
\r
3934 typedef struct stc_mfs47_i2c_ibcr_field
\r
3936 __IO uint8_t INT : 1;
\r
3937 __IO uint8_t BER : 1;
\r
3938 __IO uint8_t INTE : 1;
\r
3939 __IO uint8_t CNDE : 1;
\r
3940 __IO uint8_t WSEL : 1;
\r
3941 __IO uint8_t ACKE : 1;
\r
3942 __IO uint8_t SCC : 1;
\r
3943 __IO uint8_t MSS : 1;
\r
3944 } stc_mfs47_i2c_ibcr_field_t;
\r
3946 typedef struct stc_mfs47_i2c_ibsr_field
\r
3948 __IO uint8_t BB : 1;
\r
3949 __IO uint8_t SPC : 1;
\r
3950 __IO uint8_t RSC : 1;
\r
3951 __IO uint8_t AL : 1;
\r
3952 __IO uint8_t TRX : 1;
\r
3953 __IO uint8_t RSA : 1;
\r
3954 __IO uint8_t RACK : 1;
\r
3955 __IO uint8_t FBT : 1;
\r
3956 } stc_mfs47_i2c_ibsr_field_t;
\r
3958 typedef struct stc_mfs47_i2c_ssr_field
\r
3960 __IO uint8_t TBI : 1;
\r
3961 __IO uint8_t TDRE : 1;
\r
3962 __IO uint8_t RDRF : 1;
\r
3963 __IO uint8_t ORE : 1;
\r
3964 __IO uint8_t TBIE : 1;
\r
3965 __IO uint8_t DMA : 1;
\r
3966 __IO uint8_t TSET : 1;
\r
3967 __IO uint8_t REC : 1;
\r
3968 } stc_mfs47_i2c_ssr_field_t;
\r
3970 typedef struct stc_mfs47_i2c_isba_field
\r
3972 __IO uint8_t SA0 : 1;
\r
3973 __IO uint8_t SA1 : 1;
\r
3974 __IO uint8_t SA2 : 1;
\r
3975 __IO uint8_t SA3 : 1;
\r
3976 __IO uint8_t SA4 : 1;
\r
3977 __IO uint8_t SA5 : 1;
\r
3978 __IO uint8_t SA6 : 1;
\r
3979 __IO uint8_t SAEN : 1;
\r
3980 } stc_mfs47_i2c_isba_field_t;
\r
3982 typedef struct stc_mfs47_i2c_ismk_field
\r
3984 __IO uint8_t SM0 : 1;
\r
3985 __IO uint8_t SM1 : 1;
\r
3986 __IO uint8_t SM2 : 1;
\r
3987 __IO uint8_t SM3 : 1;
\r
3988 __IO uint8_t SM4 : 1;
\r
3989 __IO uint8_t SM5 : 1;
\r
3990 __IO uint8_t SM6 : 1;
\r
3991 __IO uint8_t EN : 1;
\r
3992 } stc_mfs47_i2c_ismk_field_t;
\r
3994 typedef struct stc_mfs47_i2c_fcr_field
\r
3996 __IO uint16_t FE1 : 1;
\r
3997 __IO uint16_t FE2 : 1;
\r
3998 __IO uint16_t FCL1 : 1;
\r
3999 __IO uint16_t FCL2 : 1;
\r
4000 __IO uint16_t FSET : 1;
\r
4001 __IO uint16_t FLD : 1;
\r
4002 __IO uint16_t FLST : 1;
\r
4003 uint16_t RESERVED1 : 1;
\r
4004 __IO uint16_t FSEL : 1;
\r
4005 __IO uint16_t FTIE : 1;
\r
4006 __IO uint16_t FDRQ : 1;
\r
4007 __IO uint16_t FRIE : 1;
\r
4008 __IO uint16_t FLSTE : 1;
\r
4009 uint16_t RESERVED2 : 1;
\r
4010 __IO uint16_t FTST0 : 1;
\r
4011 __IO uint16_t FTST1 : 1;
\r
4012 } stc_mfs47_i2c_fcr_field_t;
\r
4014 typedef struct stc_mfs47_i2c_fcr0_field
\r
4016 __IO uint8_t FE1 : 1;
\r
4017 __IO uint8_t FE2 : 1;
\r
4018 __IO uint8_t FCL1 : 1;
\r
4019 __IO uint8_t FCL2 : 1;
\r
4020 __IO uint8_t FSET : 1;
\r
4021 __IO uint8_t FLD : 1;
\r
4022 __IO uint8_t FLST : 1;
\r
4023 } stc_mfs47_i2c_fcr0_field_t;
\r
4025 typedef struct stc_mfs47_i2c_fcr1_field
\r
4027 __IO uint8_t FSEL : 1;
\r
4028 __IO uint8_t FTIE : 1;
\r
4029 __IO uint8_t FDRQ : 1;
\r
4030 __IO uint8_t FRIE : 1;
\r
4031 __IO uint8_t FLSTE : 1;
\r
4032 uint8_t RESERVED1 : 1;
\r
4033 __IO uint8_t FTST0 : 1;
\r
4034 __IO uint8_t FTST1 : 1;
\r
4035 } stc_mfs47_i2c_fcr1_field_t;
\r
4037 typedef struct stc_mfs47_i2c_fbyte_field
\r
4039 __IO uint16_t FD0 : 1;
\r
4040 __IO uint16_t FD1 : 1;
\r
4041 __IO uint16_t FD2 : 1;
\r
4042 __IO uint16_t FD3 : 1;
\r
4043 __IO uint16_t FD4 : 1;
\r
4044 __IO uint16_t FD5 : 1;
\r
4045 __IO uint16_t FD6 : 1;
\r
4046 __IO uint16_t FD7 : 1;
\r
4047 __IO uint16_t FD8 : 1;
\r
4048 __IO uint16_t FD9 : 1;
\r
4049 __IO uint16_t FD10 : 1;
\r
4050 __IO uint16_t FD11 : 1;
\r
4051 __IO uint16_t FD12 : 1;
\r
4052 __IO uint16_t FD13 : 1;
\r
4053 __IO uint16_t FD14 : 1;
\r
4054 __IO uint16_t FD15 : 1;
\r
4055 } stc_mfs47_i2c_fbyte_field_t;
\r
4057 typedef struct stc_mfs47_i2c_fbyte1_field
\r
4059 __IO uint8_t FD0 : 1;
\r
4060 __IO uint8_t FD1 : 1;
\r
4061 __IO uint8_t FD2 : 1;
\r
4062 __IO uint8_t FD3 : 1;
\r
4063 __IO uint8_t FD4 : 1;
\r
4064 __IO uint8_t FD5 : 1;
\r
4065 __IO uint8_t FD6 : 1;
\r
4066 __IO uint8_t FD7 : 1;
\r
4067 } stc_mfs47_i2c_fbyte1_field_t;
\r
4069 typedef struct stc_mfs47_i2c_fbyte2_field
\r
4071 __IO uint8_t FD8 : 1;
\r
4072 __IO uint8_t FD9 : 1;
\r
4073 __IO uint8_t FD10 : 1;
\r
4074 __IO uint8_t FD11 : 1;
\r
4075 __IO uint8_t FD12 : 1;
\r
4076 __IO uint8_t FD13 : 1;
\r
4077 __IO uint8_t FD14 : 1;
\r
4078 __IO uint8_t FD15 : 1;
\r
4079 } stc_mfs47_i2c_fbyte2_field_t;
\r
4081 /******************************************************************************
\r
4083 ******************************************************************************/
\r
4084 /* CRC_MODULE register bit fields */
\r
4085 typedef struct stc_crc_crccr_field
\r
4087 __IO uint8_t INIT : 1;
\r
4088 __IO uint8_t CRC32 : 1;
\r
4089 __IO uint8_t LTLEND : 1;
\r
4090 __IO uint8_t LSBFST : 1;
\r
4091 __IO uint8_t CRCLTE : 1;
\r
4092 __IO uint8_t CRCLSF : 1;
\r
4093 __IO uint8_t FXOR : 1;
\r
4094 } stc_crc_crccr_field_t;
\r
4096 /******************************************************************************
\r
4098 ******************************************************************************/
\r
4099 /* WC_MODULE register bit fields */
\r
4100 typedef struct stc_wc_wcrd_field
\r
4102 __IO uint8_t CTR0 : 1;
\r
4103 __IO uint8_t CTR1 : 1;
\r
4104 __IO uint8_t CTR2 : 1;
\r
4105 __IO uint8_t CTR3 : 1;
\r
4106 __IO uint8_t CTR4 : 1;
\r
4107 __IO uint8_t CTR5 : 1;
\r
4108 } stc_wc_wcrd_field_t;
\r
4110 typedef struct stc_wc_wcrl_field
\r
4112 __IO uint8_t RLC0 : 1;
\r
4113 __IO uint8_t RLC1 : 1;
\r
4114 __IO uint8_t RLC2 : 1;
\r
4115 __IO uint8_t RLC3 : 1;
\r
4116 __IO uint8_t RLC4 : 1;
\r
4117 __IO uint8_t RLC5 : 1;
\r
4118 } stc_wc_wcrl_field_t;
\r
4120 typedef struct stc_wc_wccr_field
\r
4122 __IO uint8_t WCIF : 1;
\r
4123 __IO uint8_t WCIE : 1;
\r
4124 __IO uint8_t CS0 : 1;
\r
4125 __IO uint8_t CS1 : 1;
\r
4126 uint8_t RESERVED1 : 2;
\r
4127 __IO uint8_t WCOP : 1;
\r
4128 __IO uint8_t WCEN : 1;
\r
4129 } stc_wc_wccr_field_t;
\r
4131 typedef struct stc_wc_clk_sel_field
\r
4133 __IO uint16_t SEL_IN : 1;
\r
4134 uint16_t RESERVED1 : 7;
\r
4135 __IO uint16_t SEL_OUT : 1;
\r
4136 } stc_wc_clk_sel_field_t;
\r
4138 typedef struct stc_wc_clk_en_field
\r
4140 __IO uint8_t CLK_EN : 1;
\r
4141 __IO uint8_t CLK_EN_R : 1;
\r
4142 } stc_wc_clk_en_field_t;
\r
4144 /******************************************************************************
\r
4146 ******************************************************************************/
\r
4147 /* USB_MODULE register bit fields */
\r
4148 typedef struct stc_usb_hcnt_field
\r
4150 __IO uint16_t HOST : 1;
\r
4151 __IO uint16_t URST : 1;
\r
4152 __IO uint16_t SOFIRE : 1;
\r
4153 __IO uint16_t DIRE : 1;
\r
4154 __IO uint16_t CNNIRE : 1;
\r
4155 __IO uint16_t CMPIRE : 1;
\r
4156 __IO uint16_t URIRE : 1;
\r
4157 __IO uint16_t RWKIRE : 1;
\r
4158 __IO uint16_t RETRY : 1;
\r
4159 __IO uint16_t CANCEL : 1;
\r
4160 __IO uint16_t SOFSTEP : 1;
\r
4161 } stc_usb_hcnt_field_t;
\r
4163 typedef struct stc_usb_hcnt0_field
\r
4165 __IO uint8_t HOST : 1;
\r
4166 __IO uint8_t URST : 1;
\r
4167 __IO uint8_t SOFIRE : 1;
\r
4168 __IO uint8_t DIRE : 1;
\r
4169 __IO uint8_t CNNIRE : 1;
\r
4170 __IO uint8_t CMPIRE : 1;
\r
4171 __IO uint8_t URIRE : 1;
\r
4172 __IO uint8_t RWKIRE : 1;
\r
4173 } stc_usb_hcnt0_field_t;
\r
4175 typedef struct stc_usb_hcnt1_field
\r
4177 __IO uint8_t RETRY : 1;
\r
4178 __IO uint8_t CANCEL : 1;
\r
4179 __IO uint8_t SOFSTEP : 1;
\r
4180 } stc_usb_hcnt1_field_t;
\r
4182 typedef struct stc_usb_hirq_field
\r
4184 __IO uint8_t SOFIRQ : 1;
\r
4185 __IO uint8_t DIRQ : 1;
\r
4186 __IO uint8_t CNNIRQ : 1;
\r
4187 __IO uint8_t CMPIRQ : 1;
\r
4188 __IO uint8_t URIRQ : 1;
\r
4189 __IO uint8_t RWKIRQ : 1;
\r
4190 uint8_t RESERVED1 : 1;
\r
4191 __IO uint8_t TCAN : 1;
\r
4192 } stc_usb_hirq_field_t;
\r
4194 typedef struct stc_usb_herr_field
\r
4196 __IO uint8_t HS0 : 1;
\r
4197 __IO uint8_t HS1 : 1;
\r
4198 __IO uint8_t STUFF : 1;
\r
4199 __IO uint8_t TGERR : 1;
\r
4200 __IO uint8_t CRC : 1;
\r
4201 __IO uint8_t TOUT : 1;
\r
4202 __IO uint8_t RERR : 1;
\r
4203 __IO uint8_t LSTOF : 1;
\r
4204 } stc_usb_herr_field_t;
\r
4206 typedef struct stc_usb_hstate_field
\r
4208 __IO uint8_t CSTAT : 1;
\r
4209 __IO uint8_t TMODE : 1;
\r
4210 __IO uint8_t SUSP : 1;
\r
4211 __IO uint8_t SOFBUSY : 1;
\r
4212 __IO uint8_t CLKSEL : 1;
\r
4213 __IO uint8_t ALIVE : 1;
\r
4214 } stc_usb_hstate_field_t;
\r
4216 typedef struct stc_usb_hfcomp_field
\r
4218 __IO uint8_t FRAMECOMP0 : 1;
\r
4219 __IO uint8_t FRAMECOMP1 : 1;
\r
4220 __IO uint8_t FRAMECOMP2 : 1;
\r
4221 __IO uint8_t FRAMECOMP3 : 1;
\r
4222 __IO uint8_t FRAMECOMP4 : 1;
\r
4223 __IO uint8_t FRAMECOMP5 : 1;
\r
4224 __IO uint8_t FRAMECOMP6 : 1;
\r
4225 __IO uint8_t FRAMECOMP7 : 1;
\r
4226 } stc_usb_hfcomp_field_t;
\r
4228 typedef struct stc_usb_hrtimer_field
\r
4230 __IO uint16_t RTIMER0 : 1;
\r
4231 __IO uint16_t RTIMER1 : 1;
\r
4232 __IO uint16_t RTIMER2 : 1;
\r
4233 __IO uint16_t RTIMER3 : 1;
\r
4234 __IO uint16_t RTIMER4 : 1;
\r
4235 __IO uint16_t RTIMER5 : 1;
\r
4236 __IO uint16_t RTIMER6 : 1;
\r
4237 __IO uint16_t RTIMER7 : 1;
\r
4238 __IO uint16_t RTIMER8 : 1;
\r
4239 __IO uint16_t RTIMER9 : 1;
\r
4240 __IO uint16_t RTIMER10 : 1;
\r
4241 __IO uint16_t RTIMER11 : 1;
\r
4242 __IO uint16_t RTIMER12 : 1;
\r
4243 __IO uint16_t RTIMER13 : 1;
\r
4244 __IO uint16_t RTIMER14 : 1;
\r
4245 __IO uint16_t RTIMER15 : 1;
\r
4246 } stc_usb_hrtimer_field_t;
\r
4248 typedef struct stc_usb_hrtimer0_field
\r
4250 __IO uint8_t RTIMER00 : 1;
\r
4251 __IO uint8_t RTIMER01 : 1;
\r
4252 __IO uint8_t RTIMER02 : 1;
\r
4253 __IO uint8_t RTIMER03 : 1;
\r
4254 __IO uint8_t RTIMER04 : 1;
\r
4255 __IO uint8_t RTIMER05 : 1;
\r
4256 __IO uint8_t RTIMER06 : 1;
\r
4257 __IO uint8_t RTIMER07 : 1;
\r
4258 } stc_usb_hrtimer0_field_t;
\r
4260 typedef struct stc_usb_hrtimer1_field
\r
4262 __IO uint8_t RTIMER10 : 1;
\r
4263 __IO uint8_t RTIMER11 : 1;
\r
4264 __IO uint8_t RTIMER12 : 1;
\r
4265 __IO uint8_t RTIMER13 : 1;
\r
4266 __IO uint8_t RTIMER14 : 1;
\r
4267 __IO uint8_t RTIMER15 : 1;
\r
4268 __IO uint8_t RTIMER16 : 1;
\r
4269 __IO uint8_t RTIMER17 : 1;
\r
4270 } stc_usb_hrtimer1_field_t;
\r
4272 typedef struct stc_usb_hrtimer2_field
\r
4274 __IO uint8_t RTIMER20 : 1;
\r
4275 __IO uint8_t RTIMER21 : 1;
\r
4276 __IO uint8_t RTIMER22 : 1;
\r
4277 } stc_usb_hrtimer2_field_t;
\r
4279 typedef struct stc_usb_hadr_field
\r
4281 __IO uint8_t ADDRESS0 : 1;
\r
4282 __IO uint8_t ADDRESS1 : 1;
\r
4283 __IO uint8_t ADDRESS2 : 1;
\r
4284 __IO uint8_t ADDRESS3 : 1;
\r
4285 __IO uint8_t ADDRESS4 : 1;
\r
4286 __IO uint8_t ADDRESS5 : 1;
\r
4287 __IO uint8_t ADDRESS6 : 1;
\r
4288 } stc_usb_hadr_field_t;
\r
4290 typedef struct stc_usb_heof_field
\r
4292 __IO uint16_t EOF0 : 1;
\r
4293 __IO uint16_t EOF1 : 1;
\r
4294 __IO uint16_t EOF2 : 1;
\r
4295 __IO uint16_t EOF3 : 1;
\r
4296 __IO uint16_t EOF4 : 1;
\r
4297 __IO uint16_t EOF5 : 1;
\r
4298 __IO uint16_t EOF6 : 1;
\r
4299 __IO uint16_t EOF7 : 1;
\r
4300 __IO uint16_t EOF8 : 1;
\r
4301 __IO uint16_t EOF9 : 1;
\r
4302 __IO uint16_t EOF10 : 1;
\r
4303 __IO uint16_t EOF11 : 1;
\r
4304 __IO uint16_t EOF12 : 1;
\r
4305 __IO uint16_t EOF13 : 1;
\r
4306 __IO uint16_t EOF14 : 1;
\r
4307 __IO uint16_t EOF15 : 1;
\r
4308 } stc_usb_heof_field_t;
\r
4310 typedef struct stc_usb_heof0_field
\r
4312 __IO uint8_t EOF00 : 1;
\r
4313 __IO uint8_t EOF01 : 1;
\r
4314 __IO uint8_t EOF02 : 1;
\r
4315 __IO uint8_t EOF03 : 1;
\r
4316 __IO uint8_t EOF04 : 1;
\r
4317 __IO uint8_t EOF05 : 1;
\r
4318 __IO uint8_t EOF06 : 1;
\r
4319 __IO uint8_t EOF07 : 1;
\r
4320 } stc_usb_heof0_field_t;
\r
4322 typedef struct stc_usb_heof1_field
\r
4324 __IO uint8_t EOF10 : 1;
\r
4325 __IO uint8_t EOF11 : 1;
\r
4326 __IO uint8_t EOF12 : 1;
\r
4327 __IO uint8_t EOF13 : 1;
\r
4328 __IO uint8_t EOF14 : 1;
\r
4329 __IO uint8_t EOF15 : 1;
\r
4330 } stc_usb_heof1_field_t;
\r
4332 typedef struct stc_usb_hframe_field
\r
4334 __IO uint16_t FRAME0 : 1;
\r
4335 __IO uint16_t FRAME1 : 1;
\r
4336 __IO uint16_t FRAME2 : 1;
\r
4337 __IO uint16_t FRAME3 : 1;
\r
4338 __IO uint16_t FRAME4 : 1;
\r
4339 __IO uint16_t FRAME5 : 1;
\r
4340 __IO uint16_t FRAME6 : 1;
\r
4341 __IO uint16_t FRAME7 : 1;
\r
4342 __IO uint16_t FRAME8 : 1;
\r
4343 __IO uint16_t FRAME9 : 1;
\r
4344 __IO uint16_t FRAME10 : 1;
\r
4345 } stc_usb_hframe_field_t;
\r
4347 typedef struct stc_usb_hframe0_field
\r
4349 __IO uint8_t FRAME00 : 1;
\r
4350 __IO uint8_t FRAME01 : 1;
\r
4351 __IO uint8_t FRAME02 : 1;
\r
4352 __IO uint8_t FRAME03 : 1;
\r
4353 __IO uint8_t FRAME04 : 1;
\r
4354 __IO uint8_t FRAME05 : 1;
\r
4355 __IO uint8_t FRAME06 : 1;
\r
4356 __IO uint8_t FRAME07 : 1;
\r
4357 } stc_usb_hframe0_field_t;
\r
4359 typedef struct stc_usb_hframe1_field
\r
4361 __IO uint8_t FRAME10 : 1;
\r
4362 __IO uint8_t FRAME11 : 1;
\r
4363 __IO uint8_t FRAME12 : 1;
\r
4364 __IO uint8_t FRAME13 : 1;
\r
4365 } stc_usb_hframe1_field_t;
\r
4367 typedef struct stc_usb_htoken_field
\r
4369 __IO uint8_t ENDPT0 : 1;
\r
4370 __IO uint8_t ENDPT1 : 1;
\r
4371 __IO uint8_t ENDPT2 : 1;
\r
4372 __IO uint8_t ENDPT3 : 1;
\r
4373 __IO uint8_t TKNEN0 : 1;
\r
4374 __IO uint8_t TKNEN1 : 1;
\r
4375 __IO uint8_t TKNEN2 : 1;
\r
4376 __IO uint8_t TGGL : 1;
\r
4377 } stc_usb_htoken_field_t;
\r
4379 typedef struct stc_usb_udcc_field
\r
4381 __IO uint16_t PWC : 1;
\r
4382 __IO uint16_t RFBK : 1;
\r
4383 uint16_t RESERVED1 : 1;
\r
4384 __IO uint16_t STALCLREN : 1;
\r
4385 __IO uint16_t USTP : 1;
\r
4386 __IO uint16_t HCONX : 1;
\r
4387 __IO uint16_t RESUM : 1;
\r
4388 __IO uint16_t RST : 1;
\r
4389 } stc_usb_udcc_field_t;
\r
4391 typedef struct stc_usb_ep0c_field
\r
4393 __IO uint16_t PKS00 : 1;
\r
4394 __IO uint16_t PKS01 : 1;
\r
4395 __IO uint16_t PKS02 : 1;
\r
4396 __IO uint16_t PKS03 : 1;
\r
4397 __IO uint16_t PKS04 : 1;
\r
4398 __IO uint16_t PKS05 : 1;
\r
4399 __IO uint16_t PKS06 : 1;
\r
4400 uint16_t RESERVED1 : 2;
\r
4401 __IO uint16_t STAL : 1;
\r
4402 } stc_usb_ep0c_field_t;
\r
4404 typedef struct stc_usb_ep1c_field
\r
4406 __IO uint16_t PKS10 : 1;
\r
4407 __IO uint16_t PKS11 : 1;
\r
4408 __IO uint16_t PKS12 : 1;
\r
4409 __IO uint16_t PKS13 : 1;
\r
4410 __IO uint16_t PKS14 : 1;
\r
4411 __IO uint16_t PKS15 : 1;
\r
4412 __IO uint16_t PKS16 : 1;
\r
4413 __IO uint16_t PKS17 : 1;
\r
4414 __IO uint16_t PKS18 : 1;
\r
4415 __IO uint16_t STAL : 1;
\r
4416 __IO uint16_t NULE : 1;
\r
4417 __IO uint16_t DMAE : 1;
\r
4418 __IO uint16_t DIR : 1;
\r
4419 __IO uint16_t TYPE0 : 1;
\r
4420 __IO uint16_t TYPE1 : 1;
\r
4421 __IO uint16_t EPEN : 1;
\r
4422 } stc_usb_ep1c_field_t;
\r
4424 typedef struct stc_usb_ep2c_field
\r
4426 __IO uint16_t PKS20 : 1;
\r
4427 __IO uint16_t PKS21 : 1;
\r
4428 __IO uint16_t PKS22 : 1;
\r
4429 __IO uint16_t PKS23 : 1;
\r
4430 __IO uint16_t PKS24 : 1;
\r
4431 __IO uint16_t PKS25 : 1;
\r
4432 __IO uint16_t PKS26 : 1;
\r
4433 uint16_t RESERVED1 : 2;
\r
4434 __IO uint16_t STAL : 1;
\r
4435 __IO uint16_t NULE : 1;
\r
4436 __IO uint16_t DMAE : 1;
\r
4437 __IO uint16_t DIR : 1;
\r
4438 __IO uint16_t TYPE0 : 1;
\r
4439 __IO uint16_t TYPE1 : 1;
\r
4440 __IO uint16_t EPEN : 1;
\r
4441 } stc_usb_ep2c_field_t;
\r
4443 typedef struct stc_usb_ep3c_field
\r
4445 __IO uint16_t PKS30 : 1;
\r
4446 __IO uint16_t PKS31 : 1;
\r
4447 __IO uint16_t PKS32 : 1;
\r
4448 __IO uint16_t PKS33 : 1;
\r
4449 __IO uint16_t PKS34 : 1;
\r
4450 __IO uint16_t PKS35 : 1;
\r
4451 __IO uint16_t PKS36 : 1;
\r
4452 uint16_t RESERVED1 : 2;
\r
4453 __IO uint16_t STAL : 1;
\r
4454 __IO uint16_t NULE : 1;
\r
4455 __IO uint16_t DMAE : 1;
\r
4456 __IO uint16_t DIR : 1;
\r
4457 __IO uint16_t TYPE0 : 1;
\r
4458 __IO uint16_t TYPE1 : 1;
\r
4459 __IO uint16_t EPEN : 1;
\r
4460 } stc_usb_ep3c_field_t;
\r
4462 typedef struct stc_usb_ep4c_field
\r
4464 __IO uint16_t PKS40 : 1;
\r
4465 __IO uint16_t PKS41 : 1;
\r
4466 __IO uint16_t PKS42 : 1;
\r
4467 __IO uint16_t PKS43 : 1;
\r
4468 __IO uint16_t PKS44 : 1;
\r
4469 __IO uint16_t PKS45 : 1;
\r
4470 __IO uint16_t PKS46 : 1;
\r
4471 uint16_t RESERVED1 : 2;
\r
4472 __IO uint16_t STAL : 1;
\r
4473 __IO uint16_t NULE : 1;
\r
4474 __IO uint16_t DMAE : 1;
\r
4475 __IO uint16_t DIR : 1;
\r
4476 __IO uint16_t TYPE0 : 1;
\r
4477 __IO uint16_t TYPE1 : 1;
\r
4478 __IO uint16_t EPEN : 1;
\r
4479 } stc_usb_ep4c_field_t;
\r
4481 typedef struct stc_usb_ep5c_field
\r
4483 __IO uint16_t PKS50 : 1;
\r
4484 __IO uint16_t PKS51 : 1;
\r
4485 __IO uint16_t PKS52 : 1;
\r
4486 __IO uint16_t PKS53 : 1;
\r
4487 __IO uint16_t PKS54 : 1;
\r
4488 __IO uint16_t PKS55 : 1;
\r
4489 __IO uint16_t PKS56 : 1;
\r
4490 uint16_t RESERVED1 : 2;
\r
4491 __IO uint16_t STAL : 1;
\r
4492 __IO uint16_t NULE : 1;
\r
4493 __IO uint16_t DMAE : 1;
\r
4494 __IO uint16_t DIR : 1;
\r
4495 __IO uint16_t TYPE0 : 1;
\r
4496 __IO uint16_t TYPE1 : 1;
\r
4497 __IO uint16_t EPEN : 1;
\r
4498 } stc_usb_ep5c_field_t;
\r
4500 typedef struct stc_usb_tmsp_field
\r
4502 __IO uint16_t TMSP0 : 1;
\r
4503 __IO uint16_t TMSP1 : 1;
\r
4504 __IO uint16_t TMSP2 : 1;
\r
4505 __IO uint16_t TMSP3 : 1;
\r
4506 __IO uint16_t TMSP4 : 1;
\r
4507 __IO uint16_t TMSP5 : 1;
\r
4508 __IO uint16_t TMSP6 : 1;
\r
4509 __IO uint16_t TMSP7 : 1;
\r
4510 __IO uint16_t TMSP8 : 1;
\r
4511 __IO uint16_t TMSP9 : 1;
\r
4512 __IO uint16_t TMSP10 : 1;
\r
4513 } stc_usb_tmsp_field_t;
\r
4515 typedef struct stc_usb_udcs_field
\r
4517 __IO uint8_t CONF : 1;
\r
4518 __IO uint8_t SETP : 1;
\r
4519 __IO uint8_t WKUP : 1;
\r
4520 __IO uint8_t BRST : 1;
\r
4521 __IO uint8_t SOF : 1;
\r
4522 __IO uint8_t SUSP : 1;
\r
4523 } stc_usb_udcs_field_t;
\r
4525 typedef struct stc_usb_udcie_field
\r
4527 __IO uint8_t CONFIE : 1;
\r
4528 __IO uint8_t CONFN : 1;
\r
4529 __IO uint8_t WKUPIE : 1;
\r
4530 __IO uint8_t BRSTIE : 1;
\r
4531 __IO uint8_t SOFIE : 1;
\r
4532 __IO uint8_t SUSPIE : 1;
\r
4533 } stc_usb_udcie_field_t;
\r
4535 typedef struct stc_usb_ep0is_field
\r
4537 uint16_t RESERVED1 : 10;
\r
4538 __IO uint16_t DRQI : 1;
\r
4539 uint16_t RESERVED2 : 3;
\r
4540 __IO uint16_t DRQIIE : 1;
\r
4541 __IO uint16_t BFINI : 1;
\r
4542 } stc_usb_ep0is_field_t;
\r
4544 typedef struct stc_usb_ep0os_field
\r
4546 __IO uint16_t SIZE0 : 1;
\r
4547 __IO uint16_t SIZE1 : 1;
\r
4548 __IO uint16_t SIZE2 : 1;
\r
4549 __IO uint16_t SIZE3 : 1;
\r
4550 __IO uint16_t SIZE4 : 1;
\r
4551 __IO uint16_t SIZE5 : 1;
\r
4552 __IO uint16_t SIZE6 : 1;
\r
4553 uint16_t RESERVED1 : 2;
\r
4554 __IO uint16_t SPK : 1;
\r
4555 __IO uint16_t DRQO : 1;
\r
4556 uint16_t RESERVED2 : 2;
\r
4557 __IO uint16_t SPKIE : 1;
\r
4558 __IO uint16_t DRQOIE : 1;
\r
4559 __IO uint16_t BFINI : 1;
\r
4560 } stc_usb_ep0os_field_t;
\r
4562 typedef struct stc_usb_ep1s_field
\r
4564 __IO uint16_t SIZE10 : 1;
\r
4565 __IO uint16_t SIZE11 : 1;
\r
4566 __IO uint16_t SIZE12 : 1;
\r
4567 __IO uint16_t SIZE13 : 1;
\r
4568 __IO uint16_t SIZE14 : 1;
\r
4569 __IO uint16_t SIZE15 : 1;
\r
4570 __IO uint16_t SIZE16 : 1;
\r
4571 __IO uint16_t SIZE17 : 1;
\r
4572 __IO uint16_t SIZE18 : 1;
\r
4573 __IO uint16_t SPK : 1;
\r
4574 __IO uint16_t DRQ : 1;
\r
4575 __IO uint16_t BUSY : 1;
\r
4576 uint16_t RESERVED1 : 1;
\r
4577 __IO uint16_t SPKIE : 1;
\r
4578 __IO uint16_t DRQIE : 1;
\r
4579 __IO uint16_t BFINI : 1;
\r
4580 } stc_usb_ep1s_field_t;
\r
4582 typedef struct stc_usb_ep2s_field
\r
4584 __IO uint16_t SIZE20 : 1;
\r
4585 __IO uint16_t SIZE21 : 1;
\r
4586 __IO uint16_t SIZE22 : 1;
\r
4587 __IO uint16_t SIZE23 : 1;
\r
4588 __IO uint16_t SIZE24 : 1;
\r
4589 __IO uint16_t SIZE25 : 1;
\r
4590 __IO uint16_t SIZE26 : 1;
\r
4591 uint16_t RESERVED1 : 2;
\r
4592 __IO uint16_t SPK : 1;
\r
4593 __IO uint16_t DRQ : 1;
\r
4594 __IO uint16_t BUSY : 1;
\r
4595 uint16_t RESERVED2 : 1;
\r
4596 __IO uint16_t SPKIE : 1;
\r
4597 __IO uint16_t DRQIE : 1;
\r
4598 __IO uint16_t BFINI : 1;
\r
4599 } stc_usb_ep2s_field_t;
\r
4601 typedef struct stc_usb_ep4s_field
\r
4603 __IO uint16_t SIZE40 : 1;
\r
4604 __IO uint16_t SIZE41 : 1;
\r
4605 __IO uint16_t SIZE42 : 1;
\r
4606 __IO uint16_t SIZE43 : 1;
\r
4607 __IO uint16_t SIZE44 : 1;
\r
4608 __IO uint16_t SIZE45 : 1;
\r
4609 __IO uint16_t SIZE46 : 1;
\r
4610 uint16_t RESERVED1 : 2;
\r
4611 __IO uint16_t SPK : 1;
\r
4612 __IO uint16_t DRQ : 1;
\r
4613 __IO uint16_t BUSY : 1;
\r
4614 uint16_t RESERVED2 : 1;
\r
4615 __IO uint16_t SPKIE : 1;
\r
4616 __IO uint16_t DRQIE : 1;
\r
4617 __IO uint16_t BFINI : 1;
\r
4618 } stc_usb_ep4s_field_t;
\r
4620 typedef struct stc_usb_ep5s_field
\r
4622 __IO uint16_t SIZE50 : 1;
\r
4623 __IO uint16_t SIZE51 : 1;
\r
4624 __IO uint16_t SIZE52 : 1;
\r
4625 __IO uint16_t SIZE53 : 1;
\r
4626 __IO uint16_t SIZE54 : 1;
\r
4627 __IO uint16_t SIZE55 : 1;
\r
4628 __IO uint16_t SIZE56 : 1;
\r
4629 uint16_t RESERVED1 : 2;
\r
4630 __IO uint16_t SPK : 1;
\r
4631 __IO uint16_t DRQ : 1;
\r
4632 __IO uint16_t BUSY : 1;
\r
4633 uint16_t RESERVED2 : 1;
\r
4634 __IO uint16_t SPKIE : 1;
\r
4635 __IO uint16_t DRQIE : 1;
\r
4636 __IO uint16_t BFINI : 1;
\r
4637 } stc_usb_ep5s_field_t;
\r
4639 /******************************************************************************
\r
4641 ******************************************************************************/
\r
4642 /* DMAC_MODULE register bit fields */
\r
4643 typedef struct stc_dmac_dmacr_field
\r
4645 uint32_t RESERVED1 : 24;
\r
4646 __IO uint32_t DH0 : 1;
\r
4647 __IO uint32_t DH1 : 1;
\r
4648 __IO uint32_t DH2 : 1;
\r
4649 __IO uint32_t DH3 : 1;
\r
4650 __IO uint32_t PR : 1;
\r
4651 uint32_t RESERVED2 : 1;
\r
4652 __IO uint32_t DS : 1;
\r
4653 __IO uint32_t DE : 1;
\r
4654 } stc_dmac_dmacr_field_t;
\r
4656 typedef struct stc_dmac_dmaca0_field
\r
4658 __IO uint32_t TC0 : 1;
\r
4659 __IO uint32_t TC1 : 1;
\r
4660 __IO uint32_t TC2 : 1;
\r
4661 __IO uint32_t TC3 : 1;
\r
4662 __IO uint32_t TC4 : 1;
\r
4663 __IO uint32_t TC5 : 1;
\r
4664 __IO uint32_t TC6 : 1;
\r
4665 __IO uint32_t TC7 : 1;
\r
4666 __IO uint32_t TC8 : 1;
\r
4667 __IO uint32_t TC9 : 1;
\r
4668 __IO uint32_t TC10 : 1;
\r
4669 __IO uint32_t TC11 : 1;
\r
4670 __IO uint32_t TC12 : 1;
\r
4671 __IO uint32_t TC13 : 1;
\r
4672 __IO uint32_t TC14 : 1;
\r
4673 __IO uint32_t TC15 : 1;
\r
4674 __IO uint32_t BC0 : 1;
\r
4675 __IO uint32_t BC1 : 1;
\r
4676 __IO uint32_t BC2 : 1;
\r
4677 __IO uint32_t BC3 : 1;
\r
4678 uint32_t RESERVED1 : 3;
\r
4679 __IO uint32_t IS0 : 1;
\r
4680 __IO uint32_t IS1 : 1;
\r
4681 __IO uint32_t IS2 : 1;
\r
4682 __IO uint32_t IS3 : 1;
\r
4683 __IO uint32_t IS4 : 1;
\r
4684 __IO uint32_t IS5 : 1;
\r
4685 __IO uint32_t ST : 1;
\r
4686 __IO uint32_t PB : 1;
\r
4687 __IO uint32_t EB : 1;
\r
4688 } stc_dmac_dmaca0_field_t;
\r
4690 typedef struct stc_dmac_dmacb0_field
\r
4692 __IO uint32_t EM : 1;
\r
4693 uint32_t RESERVED1 : 15;
\r
4694 __IO uint32_t SS0 : 1;
\r
4695 __IO uint32_t SS1 : 1;
\r
4696 __IO uint32_t SS2 : 1;
\r
4697 __IO uint32_t CI : 1;
\r
4698 __IO uint32_t EI : 1;
\r
4699 __IO uint32_t RD : 1;
\r
4700 __IO uint32_t RS : 1;
\r
4701 __IO uint32_t RC : 1;
\r
4702 __IO uint32_t FD : 1;
\r
4703 __IO uint32_t FS : 1;
\r
4704 __IO uint32_t TW0 : 1;
\r
4705 __IO uint32_t TW1 : 1;
\r
4706 __IO uint32_t MS0 : 1;
\r
4707 __IO uint32_t MS1 : 1;
\r
4708 } stc_dmac_dmacb0_field_t;
\r
4710 typedef struct stc_dmac_dmaca1_field
\r
4712 __IO uint32_t TC0 : 1;
\r
4713 __IO uint32_t TC1 : 1;
\r
4714 __IO uint32_t TC2 : 1;
\r
4715 __IO uint32_t TC3 : 1;
\r
4716 __IO uint32_t TC4 : 1;
\r
4717 __IO uint32_t TC5 : 1;
\r
4718 __IO uint32_t TC6 : 1;
\r
4719 __IO uint32_t TC7 : 1;
\r
4720 __IO uint32_t TC8 : 1;
\r
4721 __IO uint32_t TC9 : 1;
\r
4722 __IO uint32_t TC10 : 1;
\r
4723 __IO uint32_t TC11 : 1;
\r
4724 __IO uint32_t TC12 : 1;
\r
4725 __IO uint32_t TC13 : 1;
\r
4726 __IO uint32_t TC14 : 1;
\r
4727 __IO uint32_t TC15 : 1;
\r
4728 __IO uint32_t BC0 : 1;
\r
4729 __IO uint32_t BC1 : 1;
\r
4730 __IO uint32_t BC2 : 1;
\r
4731 __IO uint32_t BC3 : 1;
\r
4732 uint32_t RESERVED1 : 3;
\r
4733 __IO uint32_t IS0 : 1;
\r
4734 __IO uint32_t IS1 : 1;
\r
4735 __IO uint32_t IS2 : 1;
\r
4736 __IO uint32_t IS3 : 1;
\r
4737 __IO uint32_t IS4 : 1;
\r
4738 __IO uint32_t IS5 : 1;
\r
4739 __IO uint32_t ST : 1;
\r
4740 __IO uint32_t PB : 1;
\r
4741 __IO uint32_t EB : 1;
\r
4742 } stc_dmac_dmaca1_field_t;
\r
4744 typedef struct stc_dmac_dmacb1_field
\r
4746 __IO uint32_t EM : 1;
\r
4747 uint32_t RESERVED1 : 15;
\r
4748 __IO uint32_t SS0 : 1;
\r
4749 __IO uint32_t SS1 : 1;
\r
4750 __IO uint32_t SS2 : 1;
\r
4751 __IO uint32_t CI : 1;
\r
4752 __IO uint32_t EI : 1;
\r
4753 __IO uint32_t RD : 1;
\r
4754 __IO uint32_t RS : 1;
\r
4755 __IO uint32_t RC : 1;
\r
4756 __IO uint32_t FD : 1;
\r
4757 __IO uint32_t FS : 1;
\r
4758 __IO uint32_t TW0 : 1;
\r
4759 __IO uint32_t TW1 : 1;
\r
4760 __IO uint32_t MS0 : 1;
\r
4761 __IO uint32_t MS1 : 1;
\r
4762 } stc_dmac_dmacb1_field_t;
\r
4764 typedef struct stc_dmac_dmaca2_field
\r
4766 __IO uint32_t TC0 : 1;
\r
4767 __IO uint32_t TC1 : 1;
\r
4768 __IO uint32_t TC2 : 1;
\r
4769 __IO uint32_t TC3 : 1;
\r
4770 __IO uint32_t TC4 : 1;
\r
4771 __IO uint32_t TC5 : 1;
\r
4772 __IO uint32_t TC6 : 1;
\r
4773 __IO uint32_t TC7 : 1;
\r
4774 __IO uint32_t TC8 : 1;
\r
4775 __IO uint32_t TC9 : 1;
\r
4776 __IO uint32_t TC10 : 1;
\r
4777 __IO uint32_t TC11 : 1;
\r
4778 __IO uint32_t TC12 : 1;
\r
4779 __IO uint32_t TC13 : 1;
\r
4780 __IO uint32_t TC14 : 1;
\r
4781 __IO uint32_t TC15 : 1;
\r
4782 __IO uint32_t BC0 : 1;
\r
4783 __IO uint32_t BC1 : 1;
\r
4784 __IO uint32_t BC2 : 1;
\r
4785 __IO uint32_t BC3 : 1;
\r
4786 uint32_t RESERVED1 : 3;
\r
4787 __IO uint32_t IS0 : 1;
\r
4788 __IO uint32_t IS1 : 1;
\r
4789 __IO uint32_t IS2 : 1;
\r
4790 __IO uint32_t IS3 : 1;
\r
4791 __IO uint32_t IS4 : 1;
\r
4792 __IO uint32_t IS5 : 1;
\r
4793 __IO uint32_t ST : 1;
\r
4794 __IO uint32_t PB : 1;
\r
4795 __IO uint32_t EB : 1;
\r
4796 } stc_dmac_dmaca2_field_t;
\r
4798 typedef struct stc_dmac_dmacb2_field
\r
4800 __IO uint32_t EM : 1;
\r
4801 uint32_t RESERVED1 : 15;
\r
4802 __IO uint32_t SS0 : 1;
\r
4803 __IO uint32_t SS1 : 1;
\r
4804 __IO uint32_t SS2 : 1;
\r
4805 __IO uint32_t CI : 1;
\r
4806 __IO uint32_t EI : 1;
\r
4807 __IO uint32_t RD : 1;
\r
4808 __IO uint32_t RS : 1;
\r
4809 __IO uint32_t RC : 1;
\r
4810 __IO uint32_t FD : 1;
\r
4811 __IO uint32_t FS : 1;
\r
4812 __IO uint32_t TW0 : 1;
\r
4813 __IO uint32_t TW1 : 1;
\r
4814 __IO uint32_t MS0 : 1;
\r
4815 __IO uint32_t MS1 : 1;
\r
4816 } stc_dmac_dmacb2_field_t;
\r
4818 typedef struct stc_dmac_dmaca3_field
\r
4820 __IO uint32_t TC0 : 1;
\r
4821 __IO uint32_t TC1 : 1;
\r
4822 __IO uint32_t TC2 : 1;
\r
4823 __IO uint32_t TC3 : 1;
\r
4824 __IO uint32_t TC4 : 1;
\r
4825 __IO uint32_t TC5 : 1;
\r
4826 __IO uint32_t TC6 : 1;
\r
4827 __IO uint32_t TC7 : 1;
\r
4828 __IO uint32_t TC8 : 1;
\r
4829 __IO uint32_t TC9 : 1;
\r
4830 __IO uint32_t TC10 : 1;
\r
4831 __IO uint32_t TC11 : 1;
\r
4832 __IO uint32_t TC12 : 1;
\r
4833 __IO uint32_t TC13 : 1;
\r
4834 __IO uint32_t TC14 : 1;
\r
4835 __IO uint32_t TC15 : 1;
\r
4836 __IO uint32_t BC0 : 1;
\r
4837 __IO uint32_t BC1 : 1;
\r
4838 __IO uint32_t BC2 : 1;
\r
4839 __IO uint32_t BC3 : 1;
\r
4840 uint32_t RESERVED1 : 3;
\r
4841 __IO uint32_t IS0 : 1;
\r
4842 __IO uint32_t IS1 : 1;
\r
4843 __IO uint32_t IS2 : 1;
\r
4844 __IO uint32_t IS3 : 1;
\r
4845 __IO uint32_t IS4 : 1;
\r
4846 __IO uint32_t IS5 : 1;
\r
4847 __IO uint32_t ST : 1;
\r
4848 __IO uint32_t PB : 1;
\r
4849 __IO uint32_t EB : 1;
\r
4850 } stc_dmac_dmaca3_field_t;
\r
4852 typedef struct stc_dmac_dmacb3_field
\r
4854 __IO uint32_t EM : 1;
\r
4855 uint32_t RESERVED1 : 15;
\r
4856 __IO uint32_t SS0 : 1;
\r
4857 __IO uint32_t SS1 : 1;
\r
4858 __IO uint32_t SS2 : 1;
\r
4859 __IO uint32_t CI : 1;
\r
4860 __IO uint32_t EI : 1;
\r
4861 __IO uint32_t RD : 1;
\r
4862 __IO uint32_t RS : 1;
\r
4863 __IO uint32_t RC : 1;
\r
4864 __IO uint32_t FD : 1;
\r
4865 __IO uint32_t FS : 1;
\r
4866 __IO uint32_t TW0 : 1;
\r
4867 __IO uint32_t TW1 : 1;
\r
4868 __IO uint32_t MS0 : 1;
\r
4869 __IO uint32_t MS1 : 1;
\r
4870 } stc_dmac_dmacb3_field_t;
\r
4872 typedef struct stc_dmac_dmaca4_field
\r
4874 __IO uint32_t TC0 : 1;
\r
4875 __IO uint32_t TC1 : 1;
\r
4876 __IO uint32_t TC2 : 1;
\r
4877 __IO uint32_t TC3 : 1;
\r
4878 __IO uint32_t TC4 : 1;
\r
4879 __IO uint32_t TC5 : 1;
\r
4880 __IO uint32_t TC6 : 1;
\r
4881 __IO uint32_t TC7 : 1;
\r
4882 __IO uint32_t TC8 : 1;
\r
4883 __IO uint32_t TC9 : 1;
\r
4884 __IO uint32_t TC10 : 1;
\r
4885 __IO uint32_t TC11 : 1;
\r
4886 __IO uint32_t TC12 : 1;
\r
4887 __IO uint32_t TC13 : 1;
\r
4888 __IO uint32_t TC14 : 1;
\r
4889 __IO uint32_t TC15 : 1;
\r
4890 __IO uint32_t BC0 : 1;
\r
4891 __IO uint32_t BC1 : 1;
\r
4892 __IO uint32_t BC2 : 1;
\r
4893 __IO uint32_t BC3 : 1;
\r
4894 uint32_t RESERVED1 : 3;
\r
4895 __IO uint32_t IS0 : 1;
\r
4896 __IO uint32_t IS1 : 1;
\r
4897 __IO uint32_t IS2 : 1;
\r
4898 __IO uint32_t IS3 : 1;
\r
4899 __IO uint32_t IS4 : 1;
\r
4900 __IO uint32_t IS5 : 1;
\r
4901 __IO uint32_t ST : 1;
\r
4902 __IO uint32_t PB : 1;
\r
4903 __IO uint32_t EB : 1;
\r
4904 } stc_dmac_dmaca4_field_t;
\r
4906 typedef struct stc_dmac_dmacb4_field
\r
4908 __IO uint32_t EM : 1;
\r
4909 uint32_t RESERVED1 : 15;
\r
4910 __IO uint32_t SS0 : 1;
\r
4911 __IO uint32_t SS1 : 1;
\r
4912 __IO uint32_t SS2 : 1;
\r
4913 __IO uint32_t CI : 1;
\r
4914 __IO uint32_t EI : 1;
\r
4915 __IO uint32_t RD : 1;
\r
4916 __IO uint32_t RS : 1;
\r
4917 __IO uint32_t RC : 1;
\r
4918 __IO uint32_t FD : 1;
\r
4919 __IO uint32_t FS : 1;
\r
4920 __IO uint32_t TW0 : 1;
\r
4921 __IO uint32_t TW1 : 1;
\r
4922 __IO uint32_t MS0 : 1;
\r
4923 __IO uint32_t MS1 : 1;
\r
4924 } stc_dmac_dmacb4_field_t;
\r
4926 typedef struct stc_dmac_dmaca5_field
\r
4928 __IO uint32_t TC0 : 1;
\r
4929 __IO uint32_t TC1 : 1;
\r
4930 __IO uint32_t TC2 : 1;
\r
4931 __IO uint32_t TC3 : 1;
\r
4932 __IO uint32_t TC4 : 1;
\r
4933 __IO uint32_t TC5 : 1;
\r
4934 __IO uint32_t TC6 : 1;
\r
4935 __IO uint32_t TC7 : 1;
\r
4936 __IO uint32_t TC8 : 1;
\r
4937 __IO uint32_t TC9 : 1;
\r
4938 __IO uint32_t TC10 : 1;
\r
4939 __IO uint32_t TC11 : 1;
\r
4940 __IO uint32_t TC12 : 1;
\r
4941 __IO uint32_t TC13 : 1;
\r
4942 __IO uint32_t TC14 : 1;
\r
4943 __IO uint32_t TC15 : 1;
\r
4944 __IO uint32_t BC0 : 1;
\r
4945 __IO uint32_t BC1 : 1;
\r
4946 __IO uint32_t BC2 : 1;
\r
4947 __IO uint32_t BC3 : 1;
\r
4948 uint32_t RESERVED1 : 3;
\r
4949 __IO uint32_t IS0 : 1;
\r
4950 __IO uint32_t IS1 : 1;
\r
4951 __IO uint32_t IS2 : 1;
\r
4952 __IO uint32_t IS3 : 1;
\r
4953 __IO uint32_t IS4 : 1;
\r
4954 __IO uint32_t IS5 : 1;
\r
4955 __IO uint32_t ST : 1;
\r
4956 __IO uint32_t PB : 1;
\r
4957 __IO uint32_t EB : 1;
\r
4958 } stc_dmac_dmaca5_field_t;
\r
4960 typedef struct stc_dmac_dmacb5_field
\r
4962 __IO uint32_t EM : 1;
\r
4963 uint32_t RESERVED1 : 15;
\r
4964 __IO uint32_t SS0 : 1;
\r
4965 __IO uint32_t SS1 : 1;
\r
4966 __IO uint32_t SS2 : 1;
\r
4967 __IO uint32_t CI : 1;
\r
4968 __IO uint32_t EI : 1;
\r
4969 __IO uint32_t RD : 1;
\r
4970 __IO uint32_t RS : 1;
\r
4971 __IO uint32_t RC : 1;
\r
4972 __IO uint32_t FD : 1;
\r
4973 __IO uint32_t FS : 1;
\r
4974 __IO uint32_t TW0 : 1;
\r
4975 __IO uint32_t TW1 : 1;
\r
4976 __IO uint32_t MS0 : 1;
\r
4977 __IO uint32_t MS1 : 1;
\r
4978 } stc_dmac_dmacb5_field_t;
\r
4980 typedef struct stc_dmac_dmaca6_field
\r
4982 __IO uint32_t TC0 : 1;
\r
4983 __IO uint32_t TC1 : 1;
\r
4984 __IO uint32_t TC2 : 1;
\r
4985 __IO uint32_t TC3 : 1;
\r
4986 __IO uint32_t TC4 : 1;
\r
4987 __IO uint32_t TC5 : 1;
\r
4988 __IO uint32_t TC6 : 1;
\r
4989 __IO uint32_t TC7 : 1;
\r
4990 __IO uint32_t TC8 : 1;
\r
4991 __IO uint32_t TC9 : 1;
\r
4992 __IO uint32_t TC10 : 1;
\r
4993 __IO uint32_t TC11 : 1;
\r
4994 __IO uint32_t TC12 : 1;
\r
4995 __IO uint32_t TC13 : 1;
\r
4996 __IO uint32_t TC14 : 1;
\r
4997 __IO uint32_t TC15 : 1;
\r
4998 __IO uint32_t BC0 : 1;
\r
4999 __IO uint32_t BC1 : 1;
\r
5000 __IO uint32_t BC2 : 1;
\r
5001 __IO uint32_t BC3 : 1;
\r
5002 uint32_t RESERVED1 : 3;
\r
5003 __IO uint32_t IS0 : 1;
\r
5004 __IO uint32_t IS1 : 1;
\r
5005 __IO uint32_t IS2 : 1;
\r
5006 __IO uint32_t IS3 : 1;
\r
5007 __IO uint32_t IS4 : 1;
\r
5008 __IO uint32_t IS5 : 1;
\r
5009 __IO uint32_t ST : 1;
\r
5010 __IO uint32_t PB : 1;
\r
5011 __IO uint32_t EB : 1;
\r
5012 } stc_dmac_dmaca6_field_t;
\r
5014 typedef struct stc_dmac_dmacb6_field
\r
5016 __IO uint32_t EM : 1;
\r
5017 uint32_t RESERVED1 : 15;
\r
5018 __IO uint32_t SS0 : 1;
\r
5019 __IO uint32_t SS1 : 1;
\r
5020 __IO uint32_t SS2 : 1;
\r
5021 __IO uint32_t CI : 1;
\r
5022 __IO uint32_t EI : 1;
\r
5023 __IO uint32_t RD : 1;
\r
5024 __IO uint32_t RS : 1;
\r
5025 __IO uint32_t RC : 1;
\r
5026 __IO uint32_t FD : 1;
\r
5027 __IO uint32_t FS : 1;
\r
5028 __IO uint32_t TW0 : 1;
\r
5029 __IO uint32_t TW1 : 1;
\r
5030 __IO uint32_t MS0 : 1;
\r
5031 __IO uint32_t MS1 : 1;
\r
5032 } stc_dmac_dmacb6_field_t;
\r
5034 typedef struct stc_dmac_dmaca7_field
\r
5036 __IO uint32_t TC0 : 1;
\r
5037 __IO uint32_t TC1 : 1;
\r
5038 __IO uint32_t TC2 : 1;
\r
5039 __IO uint32_t TC3 : 1;
\r
5040 __IO uint32_t TC4 : 1;
\r
5041 __IO uint32_t TC5 : 1;
\r
5042 __IO uint32_t TC6 : 1;
\r
5043 __IO uint32_t TC7 : 1;
\r
5044 __IO uint32_t TC8 : 1;
\r
5045 __IO uint32_t TC9 : 1;
\r
5046 __IO uint32_t TC10 : 1;
\r
5047 __IO uint32_t TC11 : 1;
\r
5048 __IO uint32_t TC12 : 1;
\r
5049 __IO uint32_t TC13 : 1;
\r
5050 __IO uint32_t TC14 : 1;
\r
5051 __IO uint32_t TC15 : 1;
\r
5052 __IO uint32_t BC0 : 1;
\r
5053 __IO uint32_t BC1 : 1;
\r
5054 __IO uint32_t BC2 : 1;
\r
5055 __IO uint32_t BC3 : 1;
\r
5056 uint32_t RESERVED1 : 3;
\r
5057 __IO uint32_t IS0 : 1;
\r
5058 __IO uint32_t IS1 : 1;
\r
5059 __IO uint32_t IS2 : 1;
\r
5060 __IO uint32_t IS3 : 1;
\r
5061 __IO uint32_t IS4 : 1;
\r
5062 __IO uint32_t IS5 : 1;
\r
5063 __IO uint32_t ST : 1;
\r
5064 __IO uint32_t PB : 1;
\r
5065 __IO uint32_t EB : 1;
\r
5066 } stc_dmac_dmaca7_field_t;
\r
5068 typedef struct stc_dmac_dmacb7_field
\r
5070 __IO uint32_t EM : 1;
\r
5071 uint32_t RESERVED1 : 15;
\r
5072 __IO uint32_t SS0 : 1;
\r
5073 __IO uint32_t SS1 : 1;
\r
5074 __IO uint32_t SS2 : 1;
\r
5075 __IO uint32_t CI : 1;
\r
5076 __IO uint32_t EI : 1;
\r
5077 __IO uint32_t RD : 1;
\r
5078 __IO uint32_t RS : 1;
\r
5079 __IO uint32_t RC : 1;
\r
5080 __IO uint32_t FD : 1;
\r
5081 __IO uint32_t FS : 1;
\r
5082 __IO uint32_t TW0 : 1;
\r
5083 __IO uint32_t TW1 : 1;
\r
5084 __IO uint32_t MS0 : 1;
\r
5085 __IO uint32_t MS1 : 1;
\r
5086 } stc_dmac_dmacb7_field_t;
\r
5089 /******************************************************************************
\r
5090 * Peripheral register structures
\r
5091 ******************************************************************************/
\r
5093 /******************************************************************************
\r
5095 ******************************************************************************/
\r
5096 /* Flash interface registers */
\r
5100 __IO uint32_t FASZR;
\r
5101 stc_flash_if_faszr_field_t FASZR_f;
\r
5104 __IO uint32_t FRWTR;
\r
5105 stc_flash_if_frwtr_field_t FRWTR_f;
\r
5108 __IO uint32_t FSTR;
\r
5109 stc_flash_if_fstr_field_t FSTR_f;
\r
5111 uint8_t RESERVED0[4];
\r
5113 __IO uint32_t FSYNDN;
\r
5114 stc_flash_if_fsyndn_field_t FSYNDN_f;
\r
5116 uint8_t RESERVED1[236];
\r
5118 __IO uint32_t CRTRMM;
\r
5119 stc_flash_if_crtrmm_field_t CRTRMM_f;
\r
5121 }FM3_FLASH_IF_TypeDef;
\r
5123 /******************************************************************************
\r
5124 * Clock_Reset_MODULE
\r
5125 ******************************************************************************/
\r
5126 /* Clock and reset registers */
\r
5130 __IO uint8_t SCM_CTL;
\r
5131 stc_crg_scm_ctl_field_t SCM_CTL_f;
\r
5133 uint8_t RESERVED0[3];
\r
5135 __IO uint8_t SCM_STR;
\r
5136 stc_crg_scm_str_field_t SCM_STR_f;
\r
5138 uint8_t RESERVED1[3];
\r
5139 __IO uint32_t STB_CTL;
\r
5141 __IO uint16_t RST_STR;
\r
5142 stc_crg_rst_str_field_t RST_STR_f;
\r
5144 uint8_t RESERVED2[2];
\r
5146 __IO uint8_t BSC_PSR;
\r
5147 stc_crg_bsc_psr_field_t BSC_PSR_f;
\r
5149 uint8_t RESERVED3[3];
\r
5151 __IO uint8_t APBC0_PSR;
\r
5152 stc_crg_apbc0_psr_field_t APBC0_PSR_f;
\r
5154 uint8_t RESERVED4[3];
\r
5156 __IO uint8_t APBC1_PSR;
\r
5157 stc_crg_apbc1_psr_field_t APBC1_PSR_f;
\r
5159 uint8_t RESERVED5[3];
\r
5161 __IO uint8_t APBC2_PSR;
\r
5162 stc_crg_apbc2_psr_field_t APBC2_PSR_f;
\r
5164 uint8_t RESERVED6[3];
\r
5166 __IO uint8_t SWC_PSR;
\r
5167 stc_crg_swc_psr_field_t SWC_PSR_f;
\r
5169 uint8_t RESERVED7[7];
\r
5171 __IO uint8_t TTC_PSR;
\r
5172 stc_crg_ttc_psr_field_t TTC_PSR_f;
\r
5174 uint8_t RESERVED8[7];
\r
5176 __IO uint8_t CSW_TMR;
\r
5177 stc_crg_csw_tmr_field_t CSW_TMR_f;
\r
5179 uint8_t RESERVED9[3];
\r
5181 __IO uint8_t PSW_TMR;
\r
5182 stc_crg_psw_tmr_field_t PSW_TMR_f;
\r
5184 uint8_t RESERVED10[3];
\r
5186 __IO uint8_t PLL_CTL1;
\r
5187 stc_crg_pll_ctl1_field_t PLL_CTL1_f;
\r
5189 uint8_t RESERVED11[3];
\r
5191 __IO uint8_t PLL_CTL2;
\r
5192 stc_crg_pll_ctl2_field_t PLL_CTL2_f;
\r
5194 uint8_t RESERVED12[3];
\r
5196 __IO uint16_t CSV_CTL;
\r
5197 stc_crg_csv_ctl_field_t CSV_CTL_f;
\r
5199 uint8_t RESERVED13[2];
\r
5201 __IO uint8_t CSV_STR;
\r
5202 stc_crg_csv_str_field_t CSV_STR_f;
\r
5204 uint8_t RESERVED14[3];
\r
5205 __IO uint16_t FCSWH_CTL;
\r
5206 uint8_t RESERVED15[2];
\r
5207 __IO uint16_t FCSWL_CTL;
\r
5208 uint8_t RESERVED16[2];
\r
5209 __IO uint16_t FCSWD_CTL;
\r
5210 uint8_t RESERVED17[2];
\r
5212 __IO uint8_t DBWDT_CTL;
\r
5213 stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
\r
5215 uint8_t RESERVED18[11];
\r
5217 __IO uint8_t INT_ENR;
\r
5218 stc_crg_int_enr_field_t INT_ENR_f;
\r
5220 uint8_t RESERVED19[3];
\r
5222 __IO uint8_t INT_STR;
\r
5223 stc_crg_int_str_field_t INT_STR_f;
\r
5225 uint8_t RESERVED20[3];
\r
5227 __IO uint8_t INT_CLR;
\r
5228 stc_crg_int_clr_field_t INT_CLR_f;
\r
5232 /******************************************************************************
\r
5234 ******************************************************************************/
\r
5235 /* Hardware watchdog registers */
\r
5238 __IO uint32_t WDG_LDR;
\r
5239 __IO uint32_t WDG_VLR;
\r
5241 __IO uint8_t WDG_CTL;
\r
5242 stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
\r
5244 uint8_t RESERVED0[3];
\r
5245 __IO uint8_t WDG_ICL;
\r
5246 uint8_t RESERVED1[3];
\r
5248 __IO uint8_t WDG_RIS;
\r
5249 stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
\r
5251 uint8_t RESERVED2[3055];
\r
5252 __IO uint32_t WDG_LCK;
\r
5253 }FM3_HWWDT_TypeDef;
\r
5255 /******************************************************************************
\r
5257 ******************************************************************************/
\r
5258 /* Software watchdog registers */
\r
5261 __IO uint32_t WDOGLOAD;
\r
5262 __IO uint32_t WDOGVALUE;
\r
5264 __IO uint8_t WDOGCONTROL;
\r
5265 stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
\r
5267 uint8_t RESERVED0[3];
\r
5268 __IO uint32_t WDOGINTCLR;
\r
5270 __IO uint8_t WDOGRIS;
\r
5271 stc_swwdt_wdogris_field_t WDOGRIS_f;
\r
5273 uint8_t RESERVED1[3055];
\r
5274 __IO uint32_t WDOGLOCK;
\r
5275 }FM3_SWWDT_TypeDef;
\r
5277 /******************************************************************************
\r
5279 ******************************************************************************/
\r
5280 /* Dual timer 1/2 registers */
\r
5283 __IO uint32_t TIMER1LOAD;
\r
5284 __IO uint32_t TIMER1VALUE;
\r
5286 __IO uint32_t TIMER1CONTROL;
\r
5287 stc_dtim_timer1control_field_t TIMER1CONTROL_f;
\r
5289 __IO uint32_t TIMER1INTCLR;
\r
5291 __IO uint32_t TIMER1RIS;
\r
5292 stc_dtim_timer1ris_field_t TIMER1RIS_f;
\r
5295 __IO uint32_t TIMER1MIS;
\r
5296 stc_dtim_timer1mis_field_t TIMER1MIS_f;
\r
5298 __IO uint32_t TIMER1BGLOAD;
\r
5299 uint8_t RESERVED0[4];
\r
5300 __IO uint32_t TIMER2LOAD;
\r
5301 __IO uint32_t TIMER2VALUE;
\r
5303 __IO uint32_t TIMER2CONTROL;
\r
5304 stc_dtim_timer2control_field_t TIMER2CONTROL_f;
\r
5306 __IO uint32_t TIMER2INTCLR;
\r
5308 __IO uint32_t TIMER2RIS;
\r
5309 stc_dtim_timer2ris_field_t TIMER2RIS_f;
\r
5312 __IO uint32_t TIMER2MIS;
\r
5313 stc_dtim_timer2mis_field_t TIMER2MIS_f;
\r
5315 __IO uint32_t TIMER2BGLOAD;
\r
5316 }FM3_DTIM_TypeDef;
\r
5318 /******************************************************************************
\r
5320 ******************************************************************************/
\r
5321 /* Multifunction Timer unit 0 Free Running Timer registers */
\r
5324 uint8_t RESERVED0[40];
\r
5325 __IO uint16_t TCCP0;
\r
5326 uint8_t RESERVED1[2];
\r
5327 __IO uint16_t TCDT0;
\r
5328 uint8_t RESERVED2[2];
\r
5330 __IO uint16_t TCSA0;
\r
5331 stc_mft_frt_tcsa0_field_t TCSA0_f;
\r
5333 uint8_t RESERVED3[2];
\r
5335 __IO uint16_t TCSB0;
\r
5336 stc_mft_frt_tcsb0_field_t TCSB0_f;
\r
5338 uint8_t RESERVED4[2];
\r
5339 __IO uint16_t TCCP1;
\r
5340 uint8_t RESERVED5[2];
\r
5341 __IO uint16_t TCDT1;
\r
5342 uint8_t RESERVED6[2];
\r
5344 __IO uint16_t TCSA1;
\r
5345 stc_mft_frt_tcsa1_field_t TCSA1_f;
\r
5347 uint8_t RESERVED7[2];
\r
5349 __IO uint16_t TCSB1;
\r
5350 stc_mft_frt_tcsb1_field_t TCSB1_f;
\r
5352 uint8_t RESERVED8[2];
\r
5353 __IO uint16_t TCCP2;
\r
5354 uint8_t RESERVED9[2];
\r
5355 __IO uint16_t TCDT2;
\r
5356 uint8_t RESERVED10[2];
\r
5358 __IO uint16_t TCSA2;
\r
5359 stc_mft_frt_tcsa2_field_t TCSA2_f;
\r
5361 uint8_t RESERVED11[2];
\r
5363 __IO uint16_t TCSB2;
\r
5364 stc_mft_frt_tcsb2_field_t TCSB2_f;
\r
5366 }FM3_MFT_FRT_TypeDef;
\r
5368 /******************************************************************************
\r
5370 ******************************************************************************/
\r
5371 /* Multifunction Timer unit 0 Output Compare Unit registers */
\r
5374 __IO uint16_t OCCP0;
\r
5375 uint8_t RESERVED0[2];
\r
5376 __IO uint16_t OCCP1;
\r
5377 uint8_t RESERVED1[2];
\r
5378 __IO uint16_t OCCP2;
\r
5379 uint8_t RESERVED2[2];
\r
5380 __IO uint16_t OCCP3;
\r
5381 uint8_t RESERVED3[2];
\r
5382 __IO uint16_t OCCP4;
\r
5383 uint8_t RESERVED4[2];
\r
5384 __IO uint16_t OCCP5;
\r
5385 uint8_t RESERVED5[2];
\r
5387 __IO uint8_t OCSA10;
\r
5388 stc_mft_ocu_ocsa10_field_t OCSA10_f;
\r
5391 __IO uint8_t OCSB10;
\r
5392 stc_mft_ocu_ocsb10_field_t OCSB10_f;
\r
5394 uint8_t RESERVED6[2];
\r
5396 __IO uint8_t OCSA32;
\r
5397 stc_mft_ocu_ocsa32_field_t OCSA32_f;
\r
5400 __IO uint8_t OCSB32;
\r
5401 stc_mft_ocu_ocsb32_field_t OCSB32_f;
\r
5403 uint8_t RESERVED7[2];
\r
5405 __IO uint8_t OCSA54;
\r
5406 stc_mft_ocu_ocsa54_field_t OCSA54_f;
\r
5409 __IO uint8_t OCSB54;
\r
5410 stc_mft_ocu_ocsb54_field_t OCSB54_f;
\r
5412 uint8_t RESERVED8[3];
\r
5414 __IO uint8_t OCSC;
\r
5415 stc_mft_ocu_ocsc_field_t OCSC_f;
\r
5417 uint8_t RESERVED9[50];
\r
5419 __IO uint8_t OCFS10;
\r
5420 stc_mft_ocu_ocfs10_field_t OCFS10_f;
\r
5423 __IO uint8_t OCFS32;
\r
5424 stc_mft_ocu_ocfs32_field_t OCFS32_f;
\r
5426 uint8_t RESERVED10[2];
\r
5428 __IO uint8_t OCFS54;
\r
5429 stc_mft_ocu_ocfs54_field_t OCFS54_f;
\r
5431 }FM3_MFT_OCU_TypeDef;
\r
5433 /******************************************************************************
\r
5435 ******************************************************************************/
\r
5436 /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
\r
5439 uint8_t RESERVED0[128];
\r
5440 __IO uint16_t WFTM10;
\r
5441 uint8_t RESERVED1[2];
\r
5442 __IO uint16_t WFTM32;
\r
5443 uint8_t RESERVED2[2];
\r
5444 __IO uint16_t WFTM54;
\r
5445 uint8_t RESERVED3[2];
\r
5447 __IO uint16_t WFSA10;
\r
5448 stc_mft_wfg_wfsa10_field_t WFSA10_f;
\r
5450 uint8_t RESERVED4[2];
\r
5452 __IO uint16_t WFSA32;
\r
5453 stc_mft_wfg_wfsa32_field_t WFSA32_f;
\r
5455 uint8_t RESERVED5[2];
\r
5457 __IO uint16_t WFSA54;
\r
5458 stc_mft_wfg_wfsa54_field_t WFSA54_f;
\r
5460 uint8_t RESERVED6[2];
\r
5462 __IO uint16_t WFIR;
\r
5463 stc_mft_wfg_wfir_field_t WFIR_f;
\r
5465 uint8_t RESERVED7[2];
\r
5467 __IO uint16_t NZCL;
\r
5468 stc_mft_wfg_nzcl_field_t NZCL_f;
\r
5470 }FM3_MFT_WFG_TypeDef;
\r
5472 /******************************************************************************
\r
5474 ******************************************************************************/
\r
5475 /* Multifunction Timer unit 0 Input Capture Unit registers */
\r
5478 uint8_t RESERVED0[96];
\r
5480 __IO uint8_t ICFS10;
\r
5481 stc_mft_icu_icfs10_field_t ICFS10_f;
\r
5484 __IO uint8_t ICFS32;
\r
5485 stc_mft_icu_icfs32_field_t ICFS32_f;
\r
5487 uint8_t RESERVED1[6];
\r
5488 __IO uint16_t ICCP0;
\r
5489 uint8_t RESERVED2[2];
\r
5490 __IO uint16_t ICCP1;
\r
5491 uint8_t RESERVED3[2];
\r
5492 __IO uint16_t ICCP2;
\r
5493 uint8_t RESERVED4[2];
\r
5494 __IO uint16_t ICCP3;
\r
5495 uint8_t RESERVED5[2];
\r
5497 __IO uint8_t ICSA10;
\r
5498 stc_mft_icu_icsa10_field_t ICSA10_f;
\r
5501 __IO uint8_t ICSB10;
\r
5502 stc_mft_icu_icsb10_field_t ICSB10_f;
\r
5504 uint8_t RESERVED6[2];
\r
5506 __IO uint8_t ICSA32;
\r
5507 stc_mft_icu_icsa32_field_t ICSA32_f;
\r
5510 __IO uint8_t ICSB32;
\r
5511 stc_mft_icu_icsb32_field_t ICSB32_f;
\r
5513 }FM3_MFT_ICU_TypeDef;
\r
5515 /******************************************************************************
\r
5516 * MFT_ADCMP_MODULE
\r
5517 ******************************************************************************/
\r
5518 /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
\r
5521 uint8_t RESERVED0[160];
\r
5522 __IO uint16_t ACCP0;
\r
5523 uint8_t RESERVED1[2];
\r
5524 __IO uint16_t ACCPDN0;
\r
5525 uint8_t RESERVED2[2];
\r
5526 __IO uint16_t ACCP1;
\r
5527 uint8_t RESERVED3[2];
\r
5528 __IO uint16_t ACCPDN1;
\r
5529 uint8_t RESERVED4[2];
\r
5530 __IO uint16_t ACCP2;
\r
5531 uint8_t RESERVED5[2];
\r
5532 __IO uint16_t ACCPDN2;
\r
5533 uint8_t RESERVED6[2];
\r
5535 __IO uint8_t ACSB;
\r
5536 stc_mft_adcmp_acsb_field_t ACSB_f;
\r
5538 uint8_t RESERVED7[3];
\r
5540 __IO uint16_t ACSA;
\r
5541 stc_mft_adcmp_acsa_field_t ACSA_f;
\r
5543 uint8_t RESERVED8[2];
\r
5545 __IO uint16_t ATSA;
\r
5546 stc_mft_adcmp_atsa_field_t ATSA_f;
\r
5548 }FM3_MFT_ADCMP_TypeDef;
\r
5550 /******************************************************************************
\r
5552 ******************************************************************************/
\r
5553 /* Multifunction Timer PPG registers */
\r
5556 uint8_t RESERVED0;
\r
5558 __IO uint8_t TTCR0;
\r
5559 stc_mft_ppg_ttcr0_field_t TTCR0_f;
\r
5561 uint8_t RESERVED1[7];
\r
5562 __IO uint8_t COMP0;
\r
5563 uint8_t RESERVED2[2];
\r
5564 __IO uint8_t COMP2;
\r
5565 uint8_t RESERVED3[4];
\r
5566 __IO uint8_t COMP4;
\r
5567 uint8_t RESERVED4[2];
\r
5568 __IO uint8_t COMP6;
\r
5569 uint8_t RESERVED5[12];
\r
5571 __IO uint8_t TTCR1;
\r
5572 stc_mft_ppg_ttcr1_field_t TTCR1_f;
\r
5574 uint8_t RESERVED6[7];
\r
5575 __IO uint8_t COMP1;
\r
5576 uint8_t RESERVED7[2];
\r
5577 __IO uint8_t COMP3;
\r
5578 uint8_t RESERVED8[4];
\r
5579 __IO uint8_t COMP5;
\r
5580 uint8_t RESERVED9[2];
\r
5581 __IO uint8_t COMP7;
\r
5582 uint8_t RESERVED10[203];
\r
5584 __IO uint16_t TRG;
\r
5585 stc_mft_ppg_trg_field_t TRG_f;
\r
5587 uint8_t RESERVED11[2];
\r
5589 __IO uint16_t REVC;
\r
5590 stc_mft_ppg_revc_field_t REVC_f;
\r
5592 uint8_t RESERVED12[250];
\r
5594 __IO uint8_t PPGC1;
\r
5595 stc_mft_ppg_ppgc1_field_t PPGC1_f;
\r
5598 __IO uint8_t PPGC0;
\r
5599 stc_mft_ppg_ppgc0_field_t PPGC0_f;
\r
5601 uint8_t RESERVED13[2];
\r
5603 __IO uint8_t PPGC3;
\r
5604 stc_mft_ppg_ppgc3_field_t PPGC3_f;
\r
5607 __IO uint8_t PPGC2;
\r
5608 stc_mft_ppg_ppgc2_field_t PPGC2_f;
\r
5610 uint8_t RESERVED14[2];
\r
5612 __IO uint16_t PRL0;
\r
5614 __IO uint8_t PRLL0;
\r
5615 __IO uint8_t PRLH0;
\r
5618 uint8_t RESERVED15[2];
\r
5620 __IO uint16_t PRL1;
\r
5622 __IO uint8_t PRLL1;
\r
5623 __IO uint8_t PRLH1;
\r
5626 uint8_t RESERVED16[2];
\r
5628 __IO uint16_t PRL2;
\r
5630 __IO uint8_t PRLL2;
\r
5631 __IO uint8_t PRLH2;
\r
5634 uint8_t RESERVED17[2];
\r
5636 __IO uint16_t PRL3;
\r
5638 __IO uint8_t PRLL3;
\r
5639 __IO uint8_t PRLH3;
\r
5642 uint8_t RESERVED18[2];
\r
5644 __IO uint8_t GATEC0;
\r
5645 stc_mft_ppg_gatec0_field_t GATEC0_f;
\r
5647 uint8_t RESERVED19[39];
\r
5649 __IO uint8_t PPGC5;
\r
5650 stc_mft_ppg_ppgc5_field_t PPGC5_f;
\r
5653 __IO uint8_t PPGC4;
\r
5654 stc_mft_ppg_ppgc4_field_t PPGC4_f;
\r
5656 uint8_t RESERVED20[2];
\r
5658 __IO uint8_t PPGC7;
\r
5659 stc_mft_ppg_ppgc7_field_t PPGC7_f;
\r
5662 __IO uint8_t PPGC6;
\r
5663 stc_mft_ppg_ppgc6_field_t PPGC6_f;
\r
5665 uint8_t RESERVED21[2];
\r
5667 __IO uint16_t PRL4;
\r
5669 __IO uint8_t PRLL4;
\r
5670 __IO uint8_t PRLH4;
\r
5673 uint8_t RESERVED22[2];
\r
5675 __IO uint16_t PRL5;
\r
5677 __IO uint8_t PRLL5;
\r
5678 __IO uint8_t PRLH5;
\r
5681 uint8_t RESERVED23[2];
\r
5683 __IO uint16_t PRL6;
\r
5685 __IO uint8_t PRLL6;
\r
5686 __IO uint8_t PRLH6;
\r
5689 uint8_t RESERVED24[2];
\r
5691 __IO uint16_t PRL7;
\r
5693 __IO uint8_t PRLL7;
\r
5694 __IO uint8_t PRLH7;
\r
5697 uint8_t RESERVED25[2];
\r
5699 __IO uint8_t GATEC4;
\r
5700 stc_mft_ppg_gatec4_field_t GATEC4_f;
\r
5702 uint8_t RESERVED26[39];
\r
5704 __IO uint8_t PPGC9;
\r
5705 stc_mft_ppg_ppgc9_field_t PPGC9_f;
\r
5708 __IO uint8_t PPGC8;
\r
5709 stc_mft_ppg_ppgc8_field_t PPGC8_f;
\r
5711 uint8_t RESERVED27[2];
\r
5713 __IO uint8_t PPGC11;
\r
5714 stc_mft_ppg_ppgc11_field_t PPGC11_f;
\r
5717 __IO uint8_t PPGC10;
\r
5718 stc_mft_ppg_ppgc10_field_t PPGC10_f;
\r
5720 uint8_t RESERVED28[2];
\r
5722 __IO uint16_t PRL8;
\r
5724 __IO uint8_t PRLL8;
\r
5725 __IO uint8_t PRLH8;
\r
5728 uint8_t RESERVED29[2];
\r
5730 __IO uint16_t PRL9;
\r
5732 __IO uint8_t PRLL9;
\r
5733 __IO uint8_t PRLH9;
\r
5736 uint8_t RESERVED30[2];
\r
5738 __IO uint16_t PRL10;
\r
5740 __IO uint8_t PRLL10;
\r
5741 __IO uint8_t PRLH10;
\r
5744 uint8_t RESERVED31[2];
\r
5746 __IO uint16_t PRL11;
\r
5748 __IO uint8_t PRLL11;
\r
5749 __IO uint8_t PRLH11;
\r
5752 uint8_t RESERVED32[2];
\r
5754 __IO uint8_t GATEC8;
\r
5755 stc_mft_ppg_gatec8_field_t GATEC8_f;
\r
5757 uint8_t RESERVED33[39];
\r
5759 __IO uint8_t PPGC13;
\r
5760 stc_mft_ppg_ppgc13_field_t PPGC13_f;
\r
5763 __IO uint8_t PPGC12;
\r
5764 stc_mft_ppg_ppgc12_field_t PPGC12_f;
\r
5766 uint8_t RESERVED34[2];
\r
5768 __IO uint8_t PPGC15;
\r
5769 stc_mft_ppg_ppgc15_field_t PPGC15_f;
\r
5772 __IO uint8_t PPGC14;
\r
5773 stc_mft_ppg_ppgc14_field_t PPGC14_f;
\r
5775 uint8_t RESERVED35[2];
\r
5777 __IO uint16_t PRL12;
\r
5779 __IO uint8_t PRLL12;
\r
5780 __IO uint8_t PRLH12;
\r
5783 uint8_t RESERVED36[2];
\r
5785 __IO uint16_t PRL13;
\r
5787 __IO uint8_t PRLL13;
\r
5788 __IO uint8_t PRLH13;
\r
5791 uint8_t RESERVED37[2];
\r
5793 __IO uint16_t PRL14;
\r
5795 __IO uint8_t PRLL14;
\r
5796 __IO uint8_t PRLH14;
\r
5799 uint8_t RESERVED38[2];
\r
5801 __IO uint16_t PRL15;
\r
5803 __IO uint8_t PRLL15;
\r
5804 __IO uint8_t PRLH15;
\r
5807 uint8_t RESERVED39[2];
\r
5809 __IO uint8_t GATEC12;
\r
5810 stc_mft_ppg_gatec12_field_t GATEC12_f;
\r
5812 }FM3_MFT_PPG_TypeDef;
\r
5814 /******************************************************************************
\r
5816 ******************************************************************************/
\r
5817 /* Base Timer 0 PPG registers */
\r
5820 __IO uint16_t PRLL;
\r
5821 uint8_t RESERVED0[2];
\r
5822 __IO uint16_t PRLH;
\r
5823 uint8_t RESERVED1[2];
\r
5824 __IO uint16_t TMR;
\r
5825 uint8_t RESERVED2[2];
\r
5827 __IO uint16_t TMCR;
\r
5828 stc_bt_ppg_tmcr_field_t TMCR_f;
\r
5830 uint8_t RESERVED3[2];
\r
5833 stc_bt_ppg_stc_field_t STC_f;
\r
5836 __IO uint8_t TMCR2;
\r
5837 stc_bt_ppg_tmcr2_field_t TMCR2_f;
\r
5839 }FM3_BT_PPG_TypeDef;
\r
5841 /******************************************************************************
\r
5843 ******************************************************************************/
\r
5844 /* Base Timer 0 PWM registers */
\r
5847 __IO uint16_t PCSR;
\r
5848 uint8_t RESERVED0[2];
\r
5849 __IO uint16_t PDUT;
\r
5850 uint8_t RESERVED1[2];
\r
5851 __IO uint16_t TMR;
\r
5852 uint8_t RESERVED2[2];
\r
5854 __IO uint16_t TMCR;
\r
5855 stc_bt_pwm_tmcr_field_t TMCR_f;
\r
5857 uint8_t RESERVED3[2];
\r
5860 stc_bt_pwm_stc_field_t STC_f;
\r
5863 __IO uint8_t TMCR2;
\r
5864 stc_bt_pwm_tmcr2_field_t TMCR2_f;
\r
5866 }FM3_BT_PWM_TypeDef;
\r
5868 /******************************************************************************
\r
5870 ******************************************************************************/
\r
5871 /* Base Timer 0 RT registers */
\r
5874 __IO uint16_t PCSR;
\r
5875 uint8_t RESERVED0[6];
\r
5876 __IO uint16_t TMR;
\r
5877 uint8_t RESERVED1[2];
\r
5879 __IO uint16_t TMCR;
\r
5880 stc_bt_rt_tmcr_field_t TMCR_f;
\r
5882 uint8_t RESERVED2[2];
\r
5885 stc_bt_rt_stc_field_t STC_f;
\r
5888 __IO uint8_t TMCR2;
\r
5889 stc_bt_rt_tmcr2_field_t TMCR2_f;
\r
5891 }FM3_BT_RT_TypeDef;
\r
5893 /******************************************************************************
\r
5895 ******************************************************************************/
\r
5896 /* Base Timer 0 PWC registers */
\r
5899 uint8_t RESERVED0[4];
\r
5900 __IO uint16_t DTBF;
\r
5901 uint8_t RESERVED1[6];
\r
5903 __IO uint16_t TMCR;
\r
5904 stc_bt_pwc_tmcr_field_t TMCR_f;
\r
5906 uint8_t RESERVED2[2];
\r
5909 stc_bt_pwc_stc_field_t STC_f;
\r
5912 __IO uint8_t TMCR2;
\r
5913 stc_bt_pwc_tmcr2_field_t TMCR2_f;
\r
5915 }FM3_BT_PWC_TypeDef;
\r
5917 /******************************************************************************
\r
5918 * BTIOSEL03_MODULE
\r
5919 ******************************************************************************/
\r
5920 /* Base Timer I/O selector channel 0 - channel 3 registers */
\r
5923 uint8_t RESERVED0;
\r
5925 __IO uint8_t BTSEL0123;
\r
5926 stc_btiosel03_btsel0123_field_t BTSEL0123_f;
\r
5928 }FM3_BTIOSEL03_TypeDef;
\r
5930 /******************************************************************************
\r
5931 * BTIOSEL47_MODULE
\r
5932 ******************************************************************************/
\r
5933 /* Base Timer I/O selector channel 4 - channel 7 registers */
\r
5936 uint8_t RESERVED0;
\r
5938 __IO uint8_t BTSEL4567;
\r
5939 stc_btiosel47_btsel4567_field_t BTSEL4567_f;
\r
5941 }FM3_BTIOSEL47_TypeDef;
\r
5943 /******************************************************************************
\r
5945 ******************************************************************************/
\r
5946 /* Software based Simulation Startup (Base Timer) register */
\r
5950 __IO uint16_t BTSSSR;
\r
5951 stc_sbssr_btsssr_field_t BTSSSR_f;
\r
5953 }FM3_SBSSR_TypeDef;
\r
5955 /******************************************************************************
\r
5957 ******************************************************************************/
\r
5958 /* Quad position and revolution counter channel 0 registers */
\r
5961 __IO uint16_t QPCR;
\r
5962 uint8_t RESERVED0[2];
\r
5963 __IO uint16_t QRCR;
\r
5964 uint8_t RESERVED1[2];
\r
5965 __IO uint16_t QPCCR;
\r
5966 uint8_t RESERVED2[2];
\r
5967 __IO uint16_t QPRCR;
\r
5968 uint8_t RESERVED3[2];
\r
5969 __IO uint16_t QMPR;
\r
5970 uint8_t RESERVED4[2];
\r
5973 __IO uint16_t QICR;
\r
5974 stc_qprc_qicr_field_t QICR_f;
\r
5978 __IO uint8_t QICRL;
\r
5979 stc_qprc_qicrl_field_t QICRL_f;
\r
5982 __IO uint8_t QICRH;
\r
5983 stc_qprc_qicrh_field_t QICRH_f;
\r
5987 uint8_t RESERVED5[2];
\r
5990 __IO uint16_t QCR;
\r
5991 stc_qprc_qcr_field_t QCR_f;
\r
5995 __IO uint8_t QCRL;
\r
5996 stc_qprc_qcrl_field_t QCRL_f;
\r
5999 __IO uint8_t QCRH;
\r
6000 stc_qprc_qcrh_field_t QCRH_f;
\r
6004 uint8_t RESERVED6[2];
\r
6006 __IO uint16_t QECR;
\r
6007 stc_qprc_qecr_field_t QECR_f;
\r
6009 }FM3_QPRC_TypeDef;
\r
6011 /******************************************************************************
\r
6013 ******************************************************************************/
\r
6014 /* 12-bit ADC unit 0 registers */
\r
6018 __IO uint8_t ADSR;
\r
6019 stc_adc_adsr_field_t ADSR_f;
\r
6022 __IO uint8_t ADCR;
\r
6023 stc_adc_adcr_field_t ADCR_f;
\r
6025 uint8_t RESERVED0[6];
\r
6027 __IO uint8_t SFNS;
\r
6028 stc_adc_sfns_field_t SFNS_f;
\r
6031 __IO uint8_t SCCR;
\r
6032 stc_adc_sccr_field_t SCCR_f;
\r
6034 uint8_t RESERVED1[2];
\r
6037 __IO uint32_t SCFD;
\r
6038 stc_adc_scfd_field_t SCFD_f;
\r
6042 __IO uint16_t SCFDL;
\r
6043 stc_adc_scfdl_field_t SCFDL_f;
\r
6046 __IO uint16_t SCFDH;
\r
6047 stc_adc_scfdh_field_t SCFDH_f;
\r
6053 __IO uint16_t SCIS23;
\r
6054 stc_adc_scis23_field_t SCIS23_f;
\r
6058 __IO uint8_t SCIS2;
\r
6059 stc_adc_scis2_field_t SCIS2_f;
\r
6062 __IO uint8_t SCIS3;
\r
6063 stc_adc_scis3_field_t SCIS3_f;
\r
6067 uint8_t RESERVED2[2];
\r
6070 __IO uint16_t SCIS01;
\r
6071 stc_adc_scis01_field_t SCIS01_f;
\r
6075 __IO uint8_t SCIS0;
\r
6076 stc_adc_scis0_field_t SCIS0_f;
\r
6079 __IO uint8_t SCIS1;
\r
6080 stc_adc_scis1_field_t SCIS1_f;
\r
6084 uint8_t RESERVED3[2];
\r
6086 __IO uint8_t PFNS;
\r
6087 stc_adc_pfns_field_t PFNS_f;
\r
6090 __IO uint8_t PCCR;
\r
6091 stc_adc_pccr_field_t PCCR_f;
\r
6093 uint8_t RESERVED4[2];
\r
6096 __IO uint32_t PCFD;
\r
6097 stc_adc_pcfd_field_t PCFD_f;
\r
6101 __IO uint16_t PCFDL;
\r
6102 stc_adc_pcfdl_field_t PCFDL_f;
\r
6105 __IO uint16_t PCFDH;
\r
6106 stc_adc_pcfdh_field_t PCFDH_f;
\r
6111 __IO uint8_t PCIS;
\r
6112 stc_adc_pcis_field_t PCIS_f;
\r
6114 uint8_t RESERVED5[3];
\r
6116 __IO uint8_t CMPCR;
\r
6117 stc_adc_cmpcr_field_t CMPCR_f;
\r
6119 uint8_t RESERVED6;
\r
6121 __IO uint16_t CMPD;
\r
6122 stc_adc_cmpd_field_t CMPD_f;
\r
6126 __IO uint16_t ADSS23;
\r
6127 stc_adc_adss23_field_t ADSS23_f;
\r
6131 __IO uint8_t ADSS2;
\r
6132 stc_adc_adss2_field_t ADSS2_f;
\r
6135 __IO uint8_t ADSS3;
\r
6136 stc_adc_adss3_field_t ADSS3_f;
\r
6140 uint8_t RESERVED7[2];
\r
6143 __IO uint16_t ADSS01;
\r
6144 stc_adc_adss01_field_t ADSS01_f;
\r
6148 __IO uint8_t ADSS0;
\r
6149 stc_adc_adss0_field_t ADSS0_f;
\r
6152 __IO uint8_t ADSS1;
\r
6153 stc_adc_adss1_field_t ADSS1_f;
\r
6157 uint8_t RESERVED8[2];
\r
6160 __IO uint16_t ADST01;
\r
6161 stc_adc_adst01_field_t ADST01_f;
\r
6165 __IO uint8_t ADST1;
\r
6166 stc_adc_adst1_field_t ADST1_f;
\r
6169 __IO uint8_t ADST0;
\r
6170 stc_adc_adst0_field_t ADST0_f;
\r
6174 uint8_t RESERVED9[2];
\r
6176 __IO uint8_t ADCT;
\r
6177 stc_adc_adct_field_t ADCT_f;
\r
6179 uint8_t RESERVED10[3];
\r
6181 __IO uint8_t PRTSL;
\r
6182 stc_adc_prtsl_field_t PRTSL_f;
\r
6185 __IO uint8_t SCTSL;
\r
6186 stc_adc_sctsl_field_t SCTSL_f;
\r
6188 uint8_t RESERVED11[2];
\r
6190 __IO uint8_t ADCEN;
\r
6191 stc_adc_adcen_field_t ADCEN_f;
\r
6195 /******************************************************************************
\r
6197 ******************************************************************************/
\r
6198 /* CR trimming registers */
\r
6202 __IO uint8_t MCR_PSR;
\r
6203 stc_crtrim_mcr_psr_field_t MCR_PSR_f;
\r
6205 uint8_t RESERVED0[3];
\r
6207 __IO uint16_t MCR_FTRM;
\r
6208 stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
\r
6210 uint8_t RESERVED1[6];
\r
6211 __IO uint32_t MCR_RLR;
\r
6212 }FM3_CRTRIM_TypeDef;
\r
6214 /******************************************************************************
\r
6216 ******************************************************************************/
\r
6217 /* External interrupt registers */
\r
6221 __IO uint16_t ENIR;
\r
6222 stc_exti_enir_field_t ENIR_f;
\r
6224 uint8_t RESERVED0[2];
\r
6226 __IO uint16_t EIRR;
\r
6227 stc_exti_eirr_field_t EIRR_f;
\r
6229 uint8_t RESERVED1[2];
\r
6231 __IO uint16_t EICL;
\r
6232 stc_exti_eicl_field_t EICL_f;
\r
6234 uint8_t RESERVED2[2];
\r
6236 __IO uint32_t ELVR;
\r
6237 stc_exti_elvr_field_t ELVR_f;
\r
6239 uint8_t RESERVED3[4];
\r
6241 __IO uint8_t NMIRR;
\r
6242 stc_exti_nmirr_field_t NMIRR_f;
\r
6244 uint8_t RESERVED4[3];
\r
6246 __IO uint8_t NMICL;
\r
6247 stc_exti_nmicl_field_t NMICL_f;
\r
6249 }FM3_EXTI_TypeDef;
\r
6251 /******************************************************************************
\r
6253 ******************************************************************************/
\r
6254 /* Interrupt request read registers */
\r
6258 __IO uint32_t DRQSEL;
\r
6259 stc_intreq_drqsel_field_t DRQSEL_f;
\r
6261 uint8_t RESERVED0[7];
\r
6263 __IO uint32_t ODDPKS;
\r
6264 stc_intreq_oddpks_field_t ODDPKS_f;
\r
6266 uint8_t RESERVED1;
\r
6268 __IO uint32_t EXC02MON;
\r
6269 stc_intreq_exc02mon_field_t EXC02MON_f;
\r
6272 __IO uint32_t IRQ00MON;
\r
6273 stc_intreq_irq00mon_field_t IRQ00MON_f;
\r
6276 __IO uint32_t IRQ01MON;
\r
6277 stc_intreq_irq01mon_field_t IRQ01MON_f;
\r
6280 __IO uint32_t IRQ02MON;
\r
6281 stc_intreq_irq02mon_field_t IRQ02MON_f;
\r
6284 __IO uint32_t IRQ03MON;
\r
6285 stc_intreq_irq03mon_field_t IRQ03MON_f;
\r
6288 __IO uint32_t IRQ04MON;
\r
6289 stc_intreq_irq04mon_field_t IRQ04MON_f;
\r
6292 __IO uint32_t IRQ05MON;
\r
6293 stc_intreq_irq05mon_field_t IRQ05MON_f;
\r
6296 __IO uint32_t IRQ06MON;
\r
6297 stc_intreq_irq06mon_field_t IRQ06MON_f;
\r
6300 __IO uint32_t IRQ07MON;
\r
6301 stc_intreq_irq07mon_field_t IRQ07MON_f;
\r
6304 __IO uint32_t IRQ08MON;
\r
6305 stc_intreq_irq08mon_field_t IRQ08MON_f;
\r
6308 __IO uint32_t IRQ09MON;
\r
6309 stc_intreq_irq09mon_field_t IRQ09MON_f;
\r
6312 __IO uint32_t IRQ10MON;
\r
6313 stc_intreq_irq10mon_field_t IRQ10MON_f;
\r
6316 __IO uint32_t IRQ11MON;
\r
6317 stc_intreq_irq11mon_field_t IRQ11MON_f;
\r
6320 __IO uint32_t IRQ12MON;
\r
6321 stc_intreq_irq12mon_field_t IRQ12MON_f;
\r
6324 __IO uint32_t IRQ13MON;
\r
6325 stc_intreq_irq13mon_field_t IRQ13MON_f;
\r
6328 __IO uint32_t IRQ14MON;
\r
6329 stc_intreq_irq14mon_field_t IRQ14MON_f;
\r
6332 __IO uint32_t IRQ15MON;
\r
6333 stc_intreq_irq15mon_field_t IRQ15MON_f;
\r
6336 __IO uint32_t IRQ16MON;
\r
6337 stc_intreq_irq16mon_field_t IRQ16MON_f;
\r
6340 __IO uint32_t IRQ17MON;
\r
6341 stc_intreq_irq17mon_field_t IRQ17MON_f;
\r
6344 __IO uint32_t IRQ18MON;
\r
6345 stc_intreq_irq18mon_field_t IRQ18MON_f;
\r
6348 __IO uint32_t IRQ19MON;
\r
6349 stc_intreq_irq19mon_field_t IRQ19MON_f;
\r
6352 __IO uint32_t IRQ20MON;
\r
6353 stc_intreq_irq20mon_field_t IRQ20MON_f;
\r
6356 __IO uint32_t IRQ21MON;
\r
6357 stc_intreq_irq21mon_field_t IRQ21MON_f;
\r
6360 __IO uint32_t IRQ22MON;
\r
6361 stc_intreq_irq22mon_field_t IRQ22MON_f;
\r
6364 __IO uint32_t IRQ23MON;
\r
6365 stc_intreq_irq23mon_field_t IRQ23MON_f;
\r
6368 __IO uint32_t IRQ24MON;
\r
6369 stc_intreq_irq24mon_field_t IRQ24MON_f;
\r
6372 __IO uint32_t IRQ25MON;
\r
6373 stc_intreq_irq25mon_field_t IRQ25MON_f;
\r
6376 __IO uint32_t IRQ26MON;
\r
6377 stc_intreq_irq26mon_field_t IRQ26MON_f;
\r
6379 __IO uint32_t IRQ27MON;
\r
6381 __IO uint32_t IRQ28MON;
\r
6382 stc_intreq_irq28mon_field_t IRQ28MON_f;
\r
6385 __IO uint32_t IRQ29MON;
\r
6386 stc_intreq_irq29mon_field_t IRQ29MON_f;
\r
6389 __IO uint32_t IRQ30MON;
\r
6390 stc_intreq_irq30mon_field_t IRQ30MON_f;
\r
6393 __IO uint32_t IRQ31MON;
\r
6394 stc_intreq_irq31mon_field_t IRQ31MON_f;
\r
6396 __IO uint32_t IRQ32MON;
\r
6397 __IO uint32_t IRQ33MON;
\r
6399 __IO uint32_t IRQ34MON;
\r
6400 stc_intreq_irq34mon_field_t IRQ34MON_f;
\r
6403 __IO uint32_t IRQ35MON;
\r
6404 stc_intreq_irq35mon_field_t IRQ35MON_f;
\r
6406 __IO uint32_t IRQ36MON;
\r
6407 __IO uint32_t IRQ37MON;
\r
6409 __IO uint32_t IRQ38MON;
\r
6410 stc_intreq_irq38mon_field_t IRQ38MON_f;
\r
6413 __IO uint32_t IRQ39MON;
\r
6414 stc_intreq_irq39mon_field_t IRQ39MON_f;
\r
6417 __IO uint32_t IRQ40MON;
\r
6418 stc_intreq_irq40mon_field_t IRQ40MON_f;
\r
6421 __IO uint32_t IRQ41MON;
\r
6422 stc_intreq_irq41mon_field_t IRQ41MON_f;
\r
6425 __IO uint32_t IRQ42MON;
\r
6426 stc_intreq_irq42mon_field_t IRQ42MON_f;
\r
6429 __IO uint32_t IRQ43MON;
\r
6430 stc_intreq_irq43mon_field_t IRQ43MON_f;
\r
6433 __IO uint32_t IRQ44MON;
\r
6434 stc_intreq_irq44mon_field_t IRQ44MON_f;
\r
6437 __IO uint32_t IRQ45MON;
\r
6438 stc_intreq_irq45mon_field_t IRQ45MON_f;
\r
6440 __IO uint32_t IRQ46MON;
\r
6441 __IO uint32_t IRQ47MON;
\r
6442 }FM3_INTREQ_TypeDef;
\r
6444 /******************************************************************************
\r
6446 ******************************************************************************/
\r
6447 /* General purpose I/O registers */
\r
6451 __IO uint32_t PFR0;
\r
6452 stc_gpio_pfr0_field_t PFR0_f;
\r
6455 __IO uint32_t PFR1;
\r
6456 stc_gpio_pfr1_field_t PFR1_f;
\r
6459 __IO uint32_t PFR2;
\r
6460 stc_gpio_pfr2_field_t PFR2_f;
\r
6463 __IO uint32_t PFR3;
\r
6464 stc_gpio_pfr3_field_t PFR3_f;
\r
6467 __IO uint32_t PFR4;
\r
6468 stc_gpio_pfr4_field_t PFR4_f;
\r
6471 __IO uint32_t PFR5;
\r
6472 stc_gpio_pfr5_field_t PFR5_f;
\r
6475 __IO uint32_t PFR6;
\r
6476 stc_gpio_pfr6_field_t PFR6_f;
\r
6478 uint8_t RESERVED0[4];
\r
6480 __IO uint32_t PFR8;
\r
6481 stc_gpio_pfr8_field_t PFR8_f;
\r
6483 uint8_t RESERVED1[20];
\r
6485 __IO uint32_t PFRE;
\r
6486 stc_gpio_pfre_field_t PFRE_f;
\r
6488 uint8_t RESERVED2[196];
\r
6490 __IO uint32_t PCR0;
\r
6491 stc_gpio_pcr0_field_t PCR0_f;
\r
6494 __IO uint32_t PCR1;
\r
6495 stc_gpio_pcr1_field_t PCR1_f;
\r
6498 __IO uint32_t PCR2;
\r
6499 stc_gpio_pcr2_field_t PCR2_f;
\r
6502 __IO uint32_t PCR3;
\r
6503 stc_gpio_pcr3_field_t PCR3_f;
\r
6506 __IO uint32_t PCR4;
\r
6507 stc_gpio_pcr4_field_t PCR4_f;
\r
6510 __IO uint32_t PCR5;
\r
6511 stc_gpio_pcr5_field_t PCR5_f;
\r
6514 __IO uint32_t PCR6;
\r
6515 stc_gpio_pcr6_field_t PCR6_f;
\r
6517 uint8_t RESERVED3[28];
\r
6519 __IO uint32_t PCRE;
\r
6520 stc_gpio_pcre_field_t PCRE_f;
\r
6522 uint8_t RESERVED4[196];
\r
6524 __IO uint32_t DDR0;
\r
6525 stc_gpio_ddr0_field_t DDR0_f;
\r
6528 __IO uint32_t DDR1;
\r
6529 stc_gpio_ddr1_field_t DDR1_f;
\r
6532 __IO uint32_t DDR2;
\r
6533 stc_gpio_ddr2_field_t DDR2_f;
\r
6536 __IO uint32_t DDR3;
\r
6537 stc_gpio_ddr3_field_t DDR3_f;
\r
6540 __IO uint32_t DDR4;
\r
6541 stc_gpio_ddr4_field_t DDR4_f;
\r
6544 __IO uint32_t DDR5;
\r
6545 stc_gpio_ddr5_field_t DDR5_f;
\r
6548 __IO uint32_t DDR6;
\r
6549 stc_gpio_ddr6_field_t DDR6_f;
\r
6551 uint8_t RESERVED5[4];
\r
6553 __IO uint32_t DDR8;
\r
6554 stc_gpio_ddr8_field_t DDR8_f;
\r
6556 uint8_t RESERVED6[20];
\r
6558 __IO uint32_t DDRE;
\r
6559 stc_gpio_ddre_field_t DDRE_f;
\r
6561 uint8_t RESERVED7[196];
\r
6563 __IO uint32_t PDIR0;
\r
6564 stc_gpio_pdir0_field_t PDIR0_f;
\r
6567 __IO uint32_t PDIR1;
\r
6568 stc_gpio_pdir1_field_t PDIR1_f;
\r
6571 __IO uint32_t PDIR2;
\r
6572 stc_gpio_pdir2_field_t PDIR2_f;
\r
6575 __IO uint32_t PDIR3;
\r
6576 stc_gpio_pdir3_field_t PDIR3_f;
\r
6579 __IO uint32_t PDIR4;
\r
6580 stc_gpio_pdir4_field_t PDIR4_f;
\r
6583 __IO uint32_t PDIR5;
\r
6584 stc_gpio_pdir5_field_t PDIR5_f;
\r
6587 __IO uint32_t PDIR6;
\r
6588 stc_gpio_pdir6_field_t PDIR6_f;
\r
6590 uint8_t RESERVED8[4];
\r
6592 __IO uint32_t PDIR8;
\r
6593 stc_gpio_pdir8_field_t PDIR8_f;
\r
6595 uint8_t RESERVED9[20];
\r
6597 __IO uint32_t PDIRE;
\r
6598 stc_gpio_pdire_field_t PDIRE_f;
\r
6600 uint8_t RESERVED10[196];
\r
6602 __IO uint32_t PDOR0;
\r
6603 stc_gpio_pdor0_field_t PDOR0_f;
\r
6606 __IO uint32_t PDOR1;
\r
6607 stc_gpio_pdor1_field_t PDOR1_f;
\r
6610 __IO uint32_t PDOR2;
\r
6611 stc_gpio_pdor2_field_t PDOR2_f;
\r
6614 __IO uint32_t PDOR3;
\r
6615 stc_gpio_pdor3_field_t PDOR3_f;
\r
6618 __IO uint32_t PDOR4;
\r
6619 stc_gpio_pdor4_field_t PDOR4_f;
\r
6622 __IO uint32_t PDOR5;
\r
6623 stc_gpio_pdor5_field_t PDOR5_f;
\r
6626 __IO uint32_t PDOR6;
\r
6627 stc_gpio_pdor6_field_t PDOR6_f;
\r
6629 uint8_t RESERVED11[4];
\r
6631 __IO uint32_t PDOR8;
\r
6632 stc_gpio_pdor8_field_t PDOR8_f;
\r
6634 uint8_t RESERVED12[20];
\r
6636 __IO uint32_t PDORE;
\r
6637 stc_gpio_pdore_field_t PDORE_f;
\r
6639 uint8_t RESERVED13[196];
\r
6641 __IO uint32_t ADE;
\r
6642 stc_gpio_ade_field_t ADE_f;
\r
6644 uint8_t RESERVED14[124];
\r
6646 __IO uint32_t SPSR;
\r
6647 stc_gpio_spsr_field_t SPSR_f;
\r
6649 uint8_t RESERVED15[124];
\r
6651 __IO uint32_t EPFR00;
\r
6652 stc_gpio_epfr00_field_t EPFR00_f;
\r
6655 __IO uint32_t EPFR01;
\r
6656 stc_gpio_epfr01_field_t EPFR01_f;
\r
6658 uint8_t RESERVED16[8];
\r
6660 __IO uint32_t EPFR04;
\r
6661 stc_gpio_epfr04_field_t EPFR04_f;
\r
6664 __IO uint32_t EPFR05;
\r
6665 stc_gpio_epfr05_field_t EPFR05_f;
\r
6668 __IO uint32_t EPFR06;
\r
6669 stc_gpio_epfr06_field_t EPFR06_f;
\r
6672 __IO uint32_t EPFR07;
\r
6673 stc_gpio_epfr07_field_t EPFR07_f;
\r
6676 __IO uint32_t EPFR08;
\r
6677 stc_gpio_epfr08_field_t EPFR08_f;
\r
6680 __IO uint32_t EPFR09;
\r
6681 stc_gpio_epfr09_field_t EPFR09_f;
\r
6683 }FM3_GPIO_TypeDef;
\r
6685 /******************************************************************************
\r
6687 ******************************************************************************/
\r
6688 /* Low voltage detection registers */
\r
6692 __IO uint8_t LVD_CTL;
\r
6693 stc_lvd_lvd_ctl_field_t LVD_CTL_f;
\r
6695 uint8_t RESERVED0[3];
\r
6697 __IO uint8_t LVD_STR;
\r
6698 stc_lvd_lvd_str_field_t LVD_STR_f;
\r
6700 uint8_t RESERVED1[3];
\r
6702 __IO uint8_t LVD_CLR;
\r
6703 stc_lvd_lvd_clr_field_t LVD_CLR_f;
\r
6705 uint8_t RESERVED2[3];
\r
6706 __IO uint32_t LVD_RLR;
\r
6708 __IO uint8_t LVD_STR2;
\r
6709 stc_lvd_lvd_str2_field_t LVD_STR2_f;
\r
6713 /******************************************************************************
\r
6715 ******************************************************************************/
\r
6716 /* USB clock registers */
\r
6720 __IO uint8_t UCCR;
\r
6721 stc_usbclk_uccr_field_t UCCR_f;
\r
6723 uint8_t RESERVED0[3];
\r
6725 __IO uint8_t UPCR1;
\r
6726 stc_usbclk_upcr1_field_t UPCR1_f;
\r
6728 uint8_t RESERVED1[3];
\r
6730 __IO uint8_t UPCR2;
\r
6731 stc_usbclk_upcr2_field_t UPCR2_f;
\r
6733 uint8_t RESERVED2[3];
\r
6735 __IO uint8_t UPCR3;
\r
6736 stc_usbclk_upcr3_field_t UPCR3_f;
\r
6738 uint8_t RESERVED3[3];
\r
6740 __IO uint8_t UPCR4;
\r
6741 stc_usbclk_upcr4_field_t UPCR4_f;
\r
6743 uint8_t RESERVED4[3];
\r
6745 __IO uint8_t UP_STR;
\r
6746 stc_usbclk_up_str_field_t UP_STR_f;
\r
6748 uint8_t RESERVED5[3];
\r
6750 __IO uint8_t UPINT_ENR;
\r
6751 stc_usbclk_upint_enr_field_t UPINT_ENR_f;
\r
6753 uint8_t RESERVED6[3];
\r
6755 __IO uint8_t UPINT_CLR;
\r
6756 stc_usbclk_upint_clr_field_t UPINT_CLR_f;
\r
6758 uint8_t RESERVED7[3];
\r
6760 __IO uint8_t UPINT_STR;
\r
6761 stc_usbclk_upint_str_field_t UPINT_STR_f;
\r
6763 uint8_t RESERVED8[3];
\r
6765 __IO uint8_t UPCR5;
\r
6766 stc_usbclk_upcr5_field_t UPCR5_f;
\r
6768 uint8_t RESERVED9[11];
\r
6770 __IO uint8_t USBEN;
\r
6771 stc_usbclk_usben_field_t USBEN_f;
\r
6773 }FM3_USBCLK_TypeDef;
\r
6775 /******************************************************************************
\r
6776 * MFS03_UART_MODULE
\r
6777 ******************************************************************************/
\r
6778 /* UART asynchronous channel 0 registers */
\r
6783 stc_mfs03_uart_smr_field_t SMR_f;
\r
6787 stc_mfs03_uart_scr_field_t SCR_f;
\r
6789 uint8_t RESERVED0[2];
\r
6791 __IO uint8_t ESCR;
\r
6792 stc_mfs03_uart_escr_field_t ESCR_f;
\r
6796 stc_mfs03_uart_ssr_field_t SSR_f;
\r
6798 uint8_t RESERVED1[2];
\r
6801 __IO uint16_t RDR;
\r
6802 stc_mfs03_uart_rdr_field_t RDR_f;
\r
6805 __IO uint16_t TDR;
\r
6806 stc_mfs03_uart_tdr_field_t TDR_f;
\r
6809 uint8_t RESERVED2[2];
\r
6812 __IO uint16_t BGR;
\r
6813 stc_mfs03_uart_bgr_field_t BGR_f;
\r
6816 __IO uint8_t BGR0;
\r
6818 __IO uint8_t BGR1;
\r
6819 stc_mfs03_uart_bgr1_field_t BGR1_f;
\r
6823 }FM3_MFS03_UART_TypeDef;
\r
6825 /******************************************************************************
\r
6826 * MFS03_CSIO_MODULE
\r
6827 ******************************************************************************/
\r
6828 /* UART synchronous channel 0 registers */
\r
6833 stc_mfs03_csio_smr_field_t SMR_f;
\r
6837 stc_mfs03_csio_scr_field_t SCR_f;
\r
6839 uint8_t RESERVED0[2];
\r
6841 __IO uint8_t ESCR;
\r
6842 stc_mfs03_csio_escr_field_t ESCR_f;
\r
6846 stc_mfs03_csio_ssr_field_t SSR_f;
\r
6848 uint8_t RESERVED1[2];
\r
6850 __IO uint16_t RDR;
\r
6851 __IO uint16_t TDR;
\r
6853 uint8_t RESERVED2[2];
\r
6855 __IO uint16_t BGR;
\r
6857 __IO uint8_t BGR0;
\r
6858 __IO uint8_t BGR1;
\r
6861 }FM3_MFS03_CSIO_TypeDef;
\r
6863 /******************************************************************************
\r
6864 * MFS03_LIN_MODULE
\r
6865 ******************************************************************************/
\r
6866 /* UART LIN channel 0 registers */
\r
6871 stc_mfs03_lin_smr_field_t SMR_f;
\r
6875 stc_mfs03_lin_scr_field_t SCR_f;
\r
6877 uint8_t RESERVED0[2];
\r
6879 __IO uint8_t ESCR;
\r
6880 stc_mfs03_lin_escr_field_t ESCR_f;
\r
6884 stc_mfs03_lin_ssr_field_t SSR_f;
\r
6886 uint8_t RESERVED1[2];
\r
6888 __IO uint16_t RDR;
\r
6889 __IO uint16_t TDR;
\r
6891 uint8_t RESERVED2[2];
\r
6894 __IO uint16_t BGR;
\r
6895 stc_mfs03_lin_bgr_field_t BGR_f;
\r
6898 __IO uint8_t BGR0;
\r
6900 __IO uint8_t BGR1;
\r
6901 stc_mfs03_lin_bgr1_field_t BGR1_f;
\r
6905 }FM3_MFS03_LIN_TypeDef;
\r
6907 /******************************************************************************
\r
6908 * MFS03_I2C_MODULE
\r
6909 ******************************************************************************/
\r
6910 /* I2C channel 0 registers */
\r
6915 stc_mfs03_i2c_smr_field_t SMR_f;
\r
6918 __IO uint8_t IBCR;
\r
6919 stc_mfs03_i2c_ibcr_field_t IBCR_f;
\r
6921 uint8_t RESERVED0[2];
\r
6923 __IO uint8_t IBSR;
\r
6924 stc_mfs03_i2c_ibsr_field_t IBSR_f;
\r
6928 stc_mfs03_i2c_ssr_field_t SSR_f;
\r
6930 uint8_t RESERVED1[2];
\r
6932 __IO uint16_t RDR;
\r
6933 __IO uint16_t TDR;
\r
6935 uint8_t RESERVED2[2];
\r
6937 __IO uint16_t BGR;
\r
6939 __IO uint8_t BGR0;
\r
6940 __IO uint8_t BGR1;
\r
6943 uint8_t RESERVED3[2];
\r
6945 __IO uint8_t ISBA;
\r
6946 stc_mfs03_i2c_isba_field_t ISBA_f;
\r
6949 __IO uint8_t ISMK;
\r
6950 stc_mfs03_i2c_ismk_field_t ISMK_f;
\r
6952 }FM3_MFS03_I2C_TypeDef;
\r
6954 /******************************************************************************
\r
6955 * MFS47_UART_MODULE
\r
6956 ******************************************************************************/
\r
6957 /* UART asynchronous channel 4 registers */
\r
6962 stc_mfs47_uart_smr_field_t SMR_f;
\r
6966 stc_mfs47_uart_scr_field_t SCR_f;
\r
6968 uint8_t RESERVED0[2];
\r
6970 __IO uint8_t ESCR;
\r
6971 stc_mfs47_uart_escr_field_t ESCR_f;
\r
6975 stc_mfs47_uart_ssr_field_t SSR_f;
\r
6977 uint8_t RESERVED1[2];
\r
6980 __IO uint16_t RDR;
\r
6981 stc_mfs47_uart_rdr_field_t RDR_f;
\r
6984 __IO uint16_t TDR;
\r
6985 stc_mfs47_uart_tdr_field_t TDR_f;
\r
6988 uint8_t RESERVED2[2];
\r
6991 __IO uint16_t BGR;
\r
6992 stc_mfs47_uart_bgr_field_t BGR_f;
\r
6995 __IO uint8_t BGR0;
\r
6997 __IO uint8_t BGR1;
\r
6998 stc_mfs47_uart_bgr1_field_t BGR1_f;
\r
7002 uint8_t RESERVED3[6];
\r
7005 __IO uint16_t FCR;
\r
7006 stc_mfs47_uart_fcr_field_t FCR_f;
\r
7010 __IO uint8_t FCR0;
\r
7011 stc_mfs47_uart_fcr0_field_t FCR0_f;
\r
7014 __IO uint8_t FCR1;
\r
7015 stc_mfs47_uart_fcr1_field_t FCR1_f;
\r
7019 uint8_t RESERVED4[2];
\r
7022 __IO uint16_t FBYTE;
\r
7023 stc_mfs47_uart_fbyte_field_t FBYTE_f;
\r
7027 __IO uint8_t FBYTE1;
\r
7028 stc_mfs47_uart_fbyte1_field_t FBYTE1_f;
\r
7031 __IO uint8_t FBYTE2;
\r
7032 stc_mfs47_uart_fbyte2_field_t FBYTE2_f;
\r
7036 }FM3_MFS47_UART_TypeDef;
\r
7038 /******************************************************************************
\r
7039 * MFS47_CSIO_MODULE
\r
7040 ******************************************************************************/
\r
7041 /* UART synchronous channel 4 registers */
\r
7046 stc_mfs47_csio_smr_field_t SMR_f;
\r
7050 stc_mfs47_csio_scr_field_t SCR_f;
\r
7052 uint8_t RESERVED0[2];
\r
7054 __IO uint8_t ESCR;
\r
7055 stc_mfs47_csio_escr_field_t ESCR_f;
\r
7059 stc_mfs47_csio_ssr_field_t SSR_f;
\r
7061 uint8_t RESERVED1[2];
\r
7063 __IO uint16_t RDR;
\r
7064 __IO uint16_t TDR;
\r
7066 uint8_t RESERVED2[2];
\r
7068 __IO uint16_t BGR;
\r
7070 __IO uint8_t BGR0;
\r
7071 __IO uint8_t BGR1;
\r
7074 uint8_t RESERVED3[6];
\r
7077 __IO uint16_t FCR;
\r
7078 stc_mfs47_csio_fcr_field_t FCR_f;
\r
7082 __IO uint8_t FCR0;
\r
7083 stc_mfs47_csio_fcr0_field_t FCR0_f;
\r
7086 __IO uint8_t FCR1;
\r
7087 stc_mfs47_csio_fcr1_field_t FCR1_f;
\r
7091 uint8_t RESERVED4[2];
\r
7094 __IO uint16_t FBYTE;
\r
7095 stc_mfs47_csio_fbyte_field_t FBYTE_f;
\r
7099 __IO uint8_t FBYTE1;
\r
7100 stc_mfs47_csio_fbyte1_field_t FBYTE1_f;
\r
7103 __IO uint8_t FBYTE2;
\r
7104 stc_mfs47_csio_fbyte2_field_t FBYTE2_f;
\r
7108 }FM3_MFS47_CSIO_TypeDef;
\r
7110 /******************************************************************************
\r
7111 * MFS47_LIN_MODULE
\r
7112 ******************************************************************************/
\r
7113 /* UART LIN channel 4 registers */
\r
7118 stc_mfs47_lin_smr_field_t SMR_f;
\r
7122 stc_mfs47_lin_scr_field_t SCR_f;
\r
7124 uint8_t RESERVED0[2];
\r
7126 __IO uint8_t ESCR;
\r
7127 stc_mfs47_lin_escr_field_t ESCR_f;
\r
7131 stc_mfs47_lin_ssr_field_t SSR_f;
\r
7133 uint8_t RESERVED1[2];
\r
7135 __IO uint16_t RDR;
\r
7136 __IO uint16_t TDR;
\r
7138 uint8_t RESERVED2[2];
\r
7141 __IO uint16_t BGR;
\r
7142 stc_mfs47_lin_bgr_field_t BGR_f;
\r
7145 __IO uint8_t BGR0;
\r
7147 __IO uint8_t BGR1;
\r
7148 stc_mfs47_lin_bgr1_field_t BGR1_f;
\r
7152 uint8_t RESERVED3[6];
\r
7155 __IO uint16_t FCR;
\r
7156 stc_mfs47_lin_fcr_field_t FCR_f;
\r
7160 __IO uint8_t FCR0;
\r
7161 stc_mfs47_lin_fcr0_field_t FCR0_f;
\r
7164 __IO uint8_t FCR1;
\r
7165 stc_mfs47_lin_fcr1_field_t FCR1_f;
\r
7169 uint8_t RESERVED4[2];
\r
7172 __IO uint16_t FBYTE;
\r
7173 stc_mfs47_lin_fbyte_field_t FBYTE_f;
\r
7177 __IO uint8_t FBYTE1;
\r
7178 stc_mfs47_lin_fbyte1_field_t FBYTE1_f;
\r
7181 __IO uint8_t FBYTE2;
\r
7182 stc_mfs47_lin_fbyte2_field_t FBYTE2_f;
\r
7186 }FM3_MFS47_LIN_TypeDef;
\r
7188 /******************************************************************************
\r
7189 * MFS47_I2C_MODULE
\r
7190 ******************************************************************************/
\r
7191 /* I2C channel 4 registers */
\r
7196 stc_mfs47_i2c_smr_field_t SMR_f;
\r
7199 __IO uint8_t IBCR;
\r
7200 stc_mfs47_i2c_ibcr_field_t IBCR_f;
\r
7202 uint8_t RESERVED0[2];
\r
7204 __IO uint8_t IBSR;
\r
7205 stc_mfs47_i2c_ibsr_field_t IBSR_f;
\r
7209 stc_mfs47_i2c_ssr_field_t SSR_f;
\r
7211 uint8_t RESERVED1[2];
\r
7213 __IO uint16_t RDR;
\r
7214 __IO uint16_t TDR;
\r
7216 uint8_t RESERVED2[2];
\r
7218 __IO uint16_t BGR;
\r
7220 __IO uint8_t BGR0;
\r
7221 __IO uint8_t BGR1;
\r
7224 uint8_t RESERVED3[2];
\r
7226 __IO uint8_t ISBA;
\r
7227 stc_mfs47_i2c_isba_field_t ISBA_f;
\r
7230 __IO uint8_t ISMK;
\r
7231 stc_mfs47_i2c_ismk_field_t ISMK_f;
\r
7233 uint8_t RESERVED4[2];
\r
7236 __IO uint16_t FCR;
\r
7237 stc_mfs47_i2c_fcr_field_t FCR_f;
\r
7241 __IO uint8_t FCR0;
\r
7242 stc_mfs47_i2c_fcr0_field_t FCR0_f;
\r
7245 __IO uint8_t FCR1;
\r
7246 stc_mfs47_i2c_fcr1_field_t FCR1_f;
\r
7250 uint8_t RESERVED5[2];
\r
7253 __IO uint16_t FBYTE;
\r
7254 stc_mfs47_i2c_fbyte_field_t FBYTE_f;
\r
7258 __IO uint8_t FBYTE1;
\r
7259 stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;
\r
7262 __IO uint8_t FBYTE2;
\r
7263 stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;
\r
7267 }FM3_MFS47_I2C_TypeDef;
\r
7269 /******************************************************************************
\r
7271 ******************************************************************************/
\r
7272 /* CRC registers */
\r
7276 __IO uint8_t CRCCR;
\r
7277 stc_crc_crccr_field_t CRCCR_f;
\r
7279 uint8_t RESERVED0[3];
\r
7280 __IO uint32_t CRCINIT;
\r
7282 __IO uint32_t CRCIN;
\r
7285 __IO uint16_t CRCINL;
\r
7287 __IO uint8_t CRCINLL;
\r
7288 __IO uint8_t CRCINLH;
\r
7292 __IO uint16_t CRCINH;
\r
7294 __IO uint8_t CRCINHL;
\r
7295 __IO uint8_t CRCINHH;
\r
7300 __IO uint32_t CRCR;
\r
7303 /******************************************************************************
\r
7305 ******************************************************************************/
\r
7306 /* Watch counter registers */
\r
7310 __IO uint8_t WCRD;
\r
7311 stc_wc_wcrd_field_t WCRD_f;
\r
7314 __IO uint8_t WCRL;
\r
7315 stc_wc_wcrl_field_t WCRL_f;
\r
7318 __IO uint8_t WCCR;
\r
7319 stc_wc_wccr_field_t WCCR_f;
\r
7321 uint8_t RESERVED0[13];
\r
7323 __IO uint16_t CLK_SEL;
\r
7324 stc_wc_clk_sel_field_t CLK_SEL_f;
\r
7326 uint8_t RESERVED1[2];
\r
7328 __IO uint8_t CLK_EN;
\r
7329 stc_wc_clk_en_field_t CLK_EN_f;
\r
7333 /******************************************************************************
\r
7335 ******************************************************************************/
\r
7336 /* USB channel 0 registers */
\r
7341 __IO uint16_t HCNT;
\r
7342 stc_usb_hcnt_field_t HCNT_f;
\r
7346 __IO uint8_t HCNT0;
\r
7347 stc_usb_hcnt0_field_t HCNT0_f;
\r
7350 __IO uint8_t HCNT1;
\r
7351 stc_usb_hcnt1_field_t HCNT1_f;
\r
7355 uint8_t RESERVED0[2];
\r
7357 __IO uint8_t HIRQ;
\r
7358 stc_usb_hirq_field_t HIRQ_f;
\r
7361 __IO uint8_t HERR;
\r
7362 stc_usb_herr_field_t HERR_f;
\r
7364 uint8_t RESERVED1[2];
\r
7366 __IO uint8_t HSTATE;
\r
7367 stc_usb_hstate_field_t HSTATE_f;
\r
7370 __IO uint8_t HFCOMP;
\r
7371 stc_usb_hfcomp_field_t HFCOMP_f;
\r
7373 uint8_t RESERVED2[2];
\r
7376 __IO uint16_t HRTIMER;
\r
7377 stc_usb_hrtimer_field_t HRTIMER_f;
\r
7381 __IO uint8_t HRTIMER0;
\r
7382 stc_usb_hrtimer0_field_t HRTIMER0_f;
\r
7385 __IO uint8_t HRTIMER1;
\r
7386 stc_usb_hrtimer1_field_t HRTIMER1_f;
\r
7390 uint8_t RESERVED3[2];
\r
7392 __IO uint8_t HRTIMER2;
\r
7393 stc_usb_hrtimer2_field_t HRTIMER2_f;
\r
7396 __IO uint8_t HADR;
\r
7397 stc_usb_hadr_field_t HADR_f;
\r
7399 uint8_t RESERVED4[2];
\r
7402 __IO uint16_t HEOF;
\r
7403 stc_usb_heof_field_t HEOF_f;
\r
7407 __IO uint8_t HEOF0;
\r
7408 stc_usb_heof0_field_t HEOF0_f;
\r
7411 __IO uint8_t HEOF1;
\r
7412 stc_usb_heof1_field_t HEOF1_f;
\r
7416 uint8_t RESERVED5[2];
\r
7419 __IO uint16_t HFRAME;
\r
7420 stc_usb_hframe_field_t HFRAME_f;
\r
7424 __IO uint8_t HFRAME0;
\r
7425 stc_usb_hframe0_field_t HFRAME0_f;
\r
7428 __IO uint8_t HFRAME1;
\r
7429 stc_usb_hframe1_field_t HFRAME1_f;
\r
7433 uint8_t RESERVED6[2];
\r
7435 __IO uint8_t HTOKEN;
\r
7436 stc_usb_htoken_field_t HTOKEN_f;
\r
7438 uint8_t RESERVED7[3];
\r
7440 __IO uint16_t UDCC;
\r
7441 stc_usb_udcc_field_t UDCC_f;
\r
7443 uint8_t RESERVED8[2];
\r
7445 __IO uint16_t EP0C;
\r
7446 stc_usb_ep0c_field_t EP0C_f;
\r
7448 uint8_t RESERVED9[2];
\r
7450 __IO uint16_t EP1C;
\r
7451 stc_usb_ep1c_field_t EP1C_f;
\r
7453 uint8_t RESERVED10[2];
\r
7455 __IO uint16_t EP2C;
\r
7456 stc_usb_ep2c_field_t EP2C_f;
\r
7458 uint8_t RESERVED11[2];
\r
7460 __IO uint16_t EP3C;
\r
7461 stc_usb_ep3c_field_t EP3C_f;
\r
7463 uint8_t RESERVED12[2];
\r
7465 __IO uint16_t EP4C;
\r
7466 stc_usb_ep4c_field_t EP4C_f;
\r
7468 uint8_t RESERVED13[2];
\r
7470 __IO uint16_t EP5C;
\r
7471 stc_usb_ep5c_field_t EP5C_f;
\r
7473 uint8_t RESERVED14[2];
\r
7475 __IO uint16_t TMSP;
\r
7476 stc_usb_tmsp_field_t TMSP_f;
\r
7478 uint8_t RESERVED15[2];
\r
7480 __IO uint8_t UDCS;
\r
7481 stc_usb_udcs_field_t UDCS_f;
\r
7484 __IO uint8_t UDCIE;
\r
7485 stc_usb_udcie_field_t UDCIE_f;
\r
7487 uint8_t RESERVED16[2];
\r
7489 __IO uint16_t EP0IS;
\r
7490 stc_usb_ep0is_field_t EP0IS_f;
\r
7492 uint8_t RESERVED17[2];
\r
7494 __IO uint16_t EP0OS;
\r
7495 stc_usb_ep0os_field_t EP0OS_f;
\r
7497 uint8_t RESERVED18[2];
\r
7499 __IO uint16_t EP1S;
\r
7500 stc_usb_ep1s_field_t EP1S_f;
\r
7502 uint8_t RESERVED19[2];
\r
7504 __IO uint16_t EP2S;
\r
7505 stc_usb_ep2s_field_t EP2S_f;
\r
7507 uint8_t RESERVED20[2];
\r
7508 __IO uint16_t EP3S;
\r
7509 uint8_t RESERVED21[2];
\r
7511 __IO uint16_t EP4S;
\r
7512 stc_usb_ep4s_field_t EP4S_f;
\r
7514 uint8_t RESERVED22[2];
\r
7516 __IO uint16_t EP5S;
\r
7517 stc_usb_ep5s_field_t EP5S_f;
\r
7519 uint8_t RESERVED23[2];
\r
7521 __IO uint16_t EP0DT;
\r
7523 __IO uint8_t EP0DTL;
\r
7524 __IO uint8_t EP0DTH;
\r
7527 uint8_t RESERVED24[2];
\r
7529 __IO uint16_t EP1DT;
\r
7531 __IO uint8_t EP1DTL;
\r
7532 __IO uint8_t EP1DTH;
\r
7535 uint8_t RESERVED25[2];
\r
7537 __IO uint16_t EP2DT;
\r
7539 __IO uint8_t EP2DTL;
\r
7540 __IO uint8_t EP2DTH;
\r
7543 uint8_t RESERVED26[2];
\r
7545 __IO uint16_t EP3DT;
\r
7547 __IO uint8_t EP3DTL;
\r
7548 __IO uint8_t EP3DTH;
\r
7551 uint8_t RESERVED27[2];
\r
7553 __IO uint16_t EP4DT;
\r
7555 __IO uint8_t EP4DTL;
\r
7556 __IO uint8_t EP4DTH;
\r
7559 uint8_t RESERVED28[2];
\r
7561 __IO uint16_t EP5DT;
\r
7563 __IO uint8_t EP5DTL;
\r
7564 __IO uint8_t EP5DTH;
\r
7569 /******************************************************************************
\r
7571 ******************************************************************************/
\r
7572 /* DMA controller */
\r
7576 __IO uint32_t DMACR;
\r
7577 stc_dmac_dmacr_field_t DMACR_f;
\r
7579 uint8_t RESERVED0[12];
\r
7581 __IO uint32_t DMACA0;
\r
7582 stc_dmac_dmaca0_field_t DMACA0_f;
\r
7585 __IO uint32_t DMACB0;
\r
7586 stc_dmac_dmacb0_field_t DMACB0_f;
\r
7588 __IO uint32_t DMACSA0;
\r
7589 __IO uint32_t DMACDA0;
\r
7591 __IO uint32_t DMACA1;
\r
7592 stc_dmac_dmaca1_field_t DMACA1_f;
\r
7595 __IO uint32_t DMACB1;
\r
7596 stc_dmac_dmacb1_field_t DMACB1_f;
\r
7598 __IO uint32_t DMACSA1;
\r
7599 __IO uint32_t DMACDA1;
\r
7601 __IO uint32_t DMACA2;
\r
7602 stc_dmac_dmaca2_field_t DMACA2_f;
\r
7605 __IO uint32_t DMACB2;
\r
7606 stc_dmac_dmacb2_field_t DMACB2_f;
\r
7608 __IO uint32_t DMACSA2;
\r
7609 __IO uint32_t DMACDA2;
\r
7611 __IO uint32_t DMACA3;
\r
7612 stc_dmac_dmaca3_field_t DMACA3_f;
\r
7615 __IO uint32_t DMACB3;
\r
7616 stc_dmac_dmacb3_field_t DMACB3_f;
\r
7618 __IO uint32_t DMACSA3;
\r
7619 __IO uint32_t DMACDA3;
\r
7621 __IO uint32_t DMACA4;
\r
7622 stc_dmac_dmaca4_field_t DMACA4_f;
\r
7625 __IO uint32_t DMACB4;
\r
7626 stc_dmac_dmacb4_field_t DMACB4_f;
\r
7628 __IO uint32_t DMACSA4;
\r
7629 __IO uint32_t DMACDA4;
\r
7631 __IO uint32_t DMACA5;
\r
7632 stc_dmac_dmaca5_field_t DMACA5_f;
\r
7635 __IO uint32_t DMACB5;
\r
7636 stc_dmac_dmacb5_field_t DMACB5_f;
\r
7638 __IO uint32_t DMACSA5;
\r
7639 __IO uint32_t DMACDA5;
\r
7641 __IO uint32_t DMACA6;
\r
7642 stc_dmac_dmaca6_field_t DMACA6_f;
\r
7645 __IO uint32_t DMACB6;
\r
7646 stc_dmac_dmacb6_field_t DMACB6_f;
\r
7648 __IO uint32_t DMACSA6;
\r
7649 __IO uint32_t DMACDA6;
\r
7651 __IO uint32_t DMACA7;
\r
7652 stc_dmac_dmaca7_field_t DMACA7_f;
\r
7655 __IO uint32_t DMACB7;
\r
7656 stc_dmac_dmacb7_field_t DMACB7_f;
\r
7658 __IO uint32_t DMACSA7;
\r
7659 __IO uint32_t DMACDA7;
\r
7660 }FM3_DMAC_TypeDef;
\r
7663 /******************************************************************************
\r
7664 * Peripheral memory map
\r
7665 ******************************************************************************/
\r
7666 #define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */
\r
7667 #define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */
\r
7668 #define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */
\r
7670 #define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */
\r
7671 #define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */
\r
7672 #define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */
\r
7673 #define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */
\r
7674 #define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */
\r
7675 #define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */
\r
7676 #define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */
\r
7677 #define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
\r
7678 #define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */
\r
7679 #define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
\r
7680 #define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */
\r
7681 #define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */
\r
7682 #define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
\r
7683 #define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */
\r
7684 #define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
\r
7685 #define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */
\r
7686 #define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */
\r
7687 #define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */
\r
7688 #define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */
\r
7689 #define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */
\r
7690 #define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */
\r
7691 #define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */
\r
7692 #define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */
\r
7693 #define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */
\r
7694 #define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */
\r
7695 #define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */
\r
7696 #define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */
\r
7697 #define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */
\r
7698 #define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */
\r
7699 #define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */
\r
7700 #define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */
\r
7701 #define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */
\r
7702 #define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */
\r
7703 #define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */
\r
7704 #define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */
\r
7705 #define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */
\r
7706 #define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */
\r
7707 #define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */
\r
7708 #define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */
\r
7709 #define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */
\r
7710 #define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */
\r
7711 #define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */
\r
7712 #define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */
\r
7713 #define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */
\r
7714 #define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */
\r
7715 #define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */
\r
7716 #define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */
\r
7717 #define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */
\r
7718 #define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */
\r
7719 #define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */
\r
7720 #define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */
\r
7721 #define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */
\r
7722 #define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */
\r
7723 #define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */
\r
7724 #define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */
\r
7725 #define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */
\r
7726 #define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */
\r
7727 #define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */
\r
7728 #define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */
\r
7729 #define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */
\r
7730 #define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */
\r
7731 #define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */
\r
7732 #define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */
\r
7733 #define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */
\r
7734 #define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */
\r
7735 #define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */
\r
7736 #define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */
\r
7737 #define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */
\r
7738 #define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */
\r
7739 #define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */
\r
7740 #define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */
\r
7741 #define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */
\r
7742 #define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */
\r
7743 #define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */
\r
7744 #define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */
\r
7745 #define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */
\r
7746 #define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */
\r
7747 #define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */
\r
7748 #define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */
\r
7749 #define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */
\r
7750 #define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */
\r
7751 #define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */
\r
7752 #define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */
\r
7753 #define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */
\r
7754 #define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */
\r
7755 #define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */
\r
7756 #define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */
\r
7757 #define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */
\r
7758 #define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */
\r
7759 #define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */
\r
7760 #define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */
\r
7761 #define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */
\r
7762 #define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */
\r
7763 #define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */
\r
7764 #define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */
\r
7765 #define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */
\r
7766 #define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */
\r
7768 /******************************************************************************
\r
7769 * Peripheral declaration
\r
7770 ******************************************************************************/
\r
7771 #define FM3_FLASH_IF ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)
\r
7772 #define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
\r
7773 #define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
\r
7774 #define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
\r
7775 #define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)
\r
7776 #define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)
\r
7777 #define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)
\r
7778 #define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)
\r
7779 #define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)
\r
7780 #define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)
\r
7781 #define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)
\r
7782 #define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)
\r
7783 #define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)
\r
7784 #define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)
\r
7785 #define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)
\r
7786 #define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)
\r
7787 #define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)
\r
7788 #define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)
\r
7789 #define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)
\r
7790 #define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)
\r
7791 #define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)
\r
7792 #define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)
\r
7793 #define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)
\r
7794 #define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)
\r
7795 #define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)
\r
7796 #define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)
\r
7797 #define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)
\r
7798 #define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)
\r
7799 #define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)
\r
7800 #define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)
\r
7801 #define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)
\r
7802 #define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)
\r
7803 #define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)
\r
7804 #define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)
\r
7805 #define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)
\r
7806 #define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)
\r
7807 #define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)
\r
7808 #define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)
\r
7809 #define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)
\r
7810 #define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)
\r
7811 #define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)
\r
7812 #define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)
\r
7813 #define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)
\r
7814 #define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)
\r
7815 #define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)
\r
7816 #define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)
\r
7817 #define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)
\r
7818 #define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)
\r
7819 #define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)
\r
7820 #define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)
\r
7821 #define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)
\r
7822 #define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)
\r
7823 #define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)
\r
7824 #define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)
\r
7825 #define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)
\r
7826 #define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)
\r
7827 #define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)
\r
7828 #define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)
\r
7829 #define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)
\r
7830 #define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE)
\r
7831 #define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE)
\r
7832 #define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)
\r
7833 #define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)
\r
7834 #define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)
\r
7835 #define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)
\r
7836 #define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)
\r
7837 #define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)
\r
7838 #define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)
\r
7839 #define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)
\r
7840 #define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)
\r
7841 #define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)
\r
7842 #define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)
\r
7843 #define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)
\r
7844 #define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)
\r
7845 #define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)
\r
7846 #define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)
\r
7847 #define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)
\r
7848 #define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)
\r
7849 #define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)
\r
7850 #define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)
\r
7851 #define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)
\r
7852 #define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)
\r
7853 #define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)
\r
7854 #define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)
\r
7855 #define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)
\r
7856 #define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)
\r
7857 #define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)
\r
7858 #define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)
\r
7859 #define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)
\r
7860 #define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)
\r
7861 #define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)
\r
7862 #define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)
\r
7863 #define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)
\r
7864 #define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE)
\r
7865 #define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE)
\r
7866 #define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE)
\r
7867 #define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)
\r
7869 /******************************************************************************
\r
7870 * Peripheral Bit Band Alias declaration
\r
7871 ******************************************************************************/
\r
7873 /* Flash interface registers */
\r
7874 #define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL))
\r
7875 #define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL))
\r
7876 #define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL))
\r
7877 #define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL))
\r
7878 #define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL))
\r
7879 #define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL))
\r
7880 #define bFM3_FLASH_IF_FSTR_EER *((volatile unsigned int*)(0x42000108UL))
\r
7881 #define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL))
\r
7882 #define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL))
\r
7883 #define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL))
\r
7884 #define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL))
\r
7885 #define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL))
\r
7886 #define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL))
\r
7887 #define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL))
\r
7888 #define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL))
\r
7889 #define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL))
\r
7890 #define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL))
\r
7891 #define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL))
\r
7892 #define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL))
\r
7893 #define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL))
\r
7895 /* Clock and reset registers */
\r
7896 #define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL))
\r
7897 #define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL))
\r
7898 #define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL))
\r
7899 #define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL))
\r
7900 #define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL))
\r
7901 #define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL))
\r
7902 #define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL))
\r
7903 #define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL))
\r
7904 #define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL))
\r
7905 #define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL))
\r
7906 #define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL))
\r
7907 #define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL))
\r
7908 #define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL))
\r
7909 #define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL))
\r
7910 #define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL))
\r
7911 #define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL))
\r
7912 #define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL))
\r
7913 #define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL))
\r
7914 #define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL))
\r
7915 #define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL))
\r
7916 #define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL))
\r
7917 #define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL))
\r
7918 #define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL))
\r
7919 #define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL))
\r
7920 #define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL))
\r
7921 #define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL))
\r
7922 #define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL))
\r
7923 #define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL))
\r
7924 #define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL))
\r
7925 #define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL))
\r
7926 #define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL))
\r
7927 #define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL))
\r
7928 #define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL))
\r
7929 #define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL))
\r
7930 #define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL))
\r
7931 #define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL))
\r
7932 #define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL))
\r
7933 #define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL))
\r
7934 #define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL))
\r
7935 #define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL))
\r
7936 #define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL))
\r
7937 #define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL))
\r
7938 #define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL))
\r
7939 #define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL))
\r
7940 #define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL))
\r
7941 #define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL))
\r
7942 #define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL))
\r
7943 #define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL))
\r
7944 #define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL))
\r
7945 #define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL))
\r
7946 #define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL))
\r
7947 #define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL))
\r
7948 #define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL))
\r
7949 #define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL))
\r
7950 #define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL))
\r
7951 #define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL))
\r
7952 #define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL))
\r
7953 #define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL))
\r
7954 #define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL))
\r
7955 #define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL))
\r
7956 #define bFM3_CRG_PLL_CTL2_PLLN5 *((volatile unsigned int*)(0x42200794UL))
\r
7957 #define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL))
\r
7958 #define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL))
\r
7959 #define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL))
\r
7960 #define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL))
\r
7961 #define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL))
\r
7962 #define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL))
\r
7963 #define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL))
\r
7964 #define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL))
\r
7965 #define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL))
\r
7966 #define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL))
\r
7967 #define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL))
\r
7968 #define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL))
\r
7969 #define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL))
\r
7970 #define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL))
\r
7971 #define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL))
\r
7972 #define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL))
\r
7973 #define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL))
\r
7974 #define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL))
\r
7975 #define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL))
\r
7976 #define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL))
\r
7977 #define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL))
\r
7978 #define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL))
\r
7979 #define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL))
\r
7981 /* Hardware watchdog registers */
\r
7982 #define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL))
\r
7983 #define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL))
\r
7984 #define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL))
\r
7986 /* Software watchdog registers */
\r
7987 #define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL))
\r
7988 #define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL))
\r
7989 #define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL))
\r
7991 /* Dual timer 1/2 registers */
\r
7992 #define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL))
\r
7993 #define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL))
\r
7994 #define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL))
\r
7995 #define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL))
\r
7996 #define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL))
\r
7997 #define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL))
\r
7998 #define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL))
\r
7999 #define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL))
\r
8000 #define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL))
\r
8001 #define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL))
\r
8002 #define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL))
\r
8003 #define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL))
\r
8004 #define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL))
\r
8005 #define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL))
\r
8006 #define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL))
\r
8007 #define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL))
\r
8008 #define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL))
\r
8009 #define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL))
\r
8011 /* Multifunction Timer unit 0 Free Running Timer registers */
\r
8012 #define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL))
\r
8013 #define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL))
\r
8014 #define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL))
\r
8015 #define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL))
\r
8016 #define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL))
\r
8017 #define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL))
\r
8018 #define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL))
\r
8019 #define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL))
\r
8020 #define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL))
\r
8021 #define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL))
\r
8022 #define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL))
\r
8023 #define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL))
\r
8024 #define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL))
\r
8025 #define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL))
\r
8026 #define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL))
\r
8027 #define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL))
\r
8028 #define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL))
\r
8029 #define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL))
\r
8030 #define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL))
\r
8031 #define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL))
\r
8032 #define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL))
\r
8033 #define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL))
\r
8034 #define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL))
\r
8035 #define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL))
\r
8036 #define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL))
\r
8037 #define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL))
\r
8038 #define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL))
\r
8039 #define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL))
\r
8040 #define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL))
\r
8041 #define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL))
\r
8042 #define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL))
\r
8043 #define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL))
\r
8044 #define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL))
\r
8045 #define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL))
\r
8046 #define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL))
\r
8047 #define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL))
\r
8048 #define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL))
\r
8049 #define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL))
\r
8050 #define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL))
\r
8051 #define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL))
\r
8052 #define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL))
\r
8053 #define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL))
\r
8054 #define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL))
\r
8055 #define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL))
\r
8056 #define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL))
\r
8057 #define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL))
\r
8058 #define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL))
\r
8059 #define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL))
\r
8061 /* Multifunction Timer unit 0 Output Compare Unit registers */
\r
8062 #define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL))
\r
8063 #define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL))
\r
8064 #define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL))
\r
8065 #define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL))
\r
8066 #define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL))
\r
8067 #define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL))
\r
8068 #define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL))
\r
8069 #define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL))
\r
8070 #define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL))
\r
8071 #define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL))
\r
8072 #define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL))
\r
8073 #define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL))
\r
8074 #define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL))
\r
8075 #define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL))
\r
8076 #define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL))
\r
8077 #define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL))
\r
8078 #define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL))
\r
8079 #define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL))
\r
8080 #define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL))
\r
8081 #define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL))
\r
8082 #define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL))
\r
8083 #define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL))
\r
8084 #define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL))
\r
8085 #define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL))
\r
8086 #define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL))
\r
8087 #define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL))
\r
8088 #define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL))
\r
8089 #define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL))
\r
8090 #define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL))
\r
8091 #define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL))
\r
8092 #define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL))
\r
8093 #define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL))
\r
8094 #define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL))
\r
8095 #define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL))
\r
8096 #define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL))
\r
8097 #define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL))
\r
8098 #define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL))
\r
8099 #define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL))
\r
8100 #define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL))
\r
8101 #define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL))
\r
8102 #define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL))
\r
8103 #define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL))
\r
8104 #define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL))
\r
8105 #define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL))
\r
8106 #define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL))
\r
8107 #define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL))
\r
8108 #define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL))
\r
8109 #define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL))
\r
8110 #define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL))
\r
8111 #define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL))
\r
8112 #define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL))
\r
8113 #define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL))
\r
8114 #define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL))
\r
8115 #define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL))
\r
8116 #define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL))
\r
8117 #define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL))
\r
8118 #define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL))
\r
8119 #define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL))
\r
8120 #define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL))
\r
8121 #define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL))
\r
8122 #define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL))
\r
8123 #define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL))
\r
8124 #define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL))
\r
8125 #define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL))
\r
8126 #define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL))
\r
8127 #define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL))
\r
8128 #define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL))
\r
8129 #define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL))
\r
8130 #define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL))
\r
8132 /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
\r
8133 #define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL))
\r
8134 #define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL))
\r
8135 #define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL))
\r
8136 #define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL))
\r
8137 #define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL))
\r
8138 #define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL))
\r
8139 #define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL))
\r
8140 #define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL))
\r
8141 #define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL))
\r
8142 #define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL))
\r
8143 #define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL))
\r
8144 #define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL))
\r
8145 #define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL))
\r
8146 #define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL))
\r
8147 #define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL))
\r
8148 #define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL))
\r
8149 #define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL))
\r
8150 #define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL))
\r
8151 #define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL))
\r
8152 #define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL))
\r
8153 #define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL))
\r
8154 #define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL))
\r
8155 #define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL))
\r
8156 #define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL))
\r
8157 #define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL))
\r
8158 #define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL))
\r
8159 #define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL))
\r
8160 #define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL))
\r
8161 #define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL))
\r
8162 #define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL))
\r
8163 #define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL))
\r
8164 #define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL))
\r
8165 #define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL))
\r
8166 #define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL))
\r
8167 #define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL))
\r
8168 #define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL))
\r
8169 #define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL))
\r
8170 #define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL))
\r
8171 #define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL))
\r
8172 #define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL))
\r
8173 #define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL))
\r
8174 #define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL))
\r
8175 #define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL))
\r
8176 #define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL))
\r
8177 #define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL))
\r
8178 #define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL))
\r
8179 #define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL))
\r
8180 #define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL))
\r
8181 #define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL))
\r
8182 #define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL))
\r
8183 #define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL))
\r
8184 #define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL))
\r
8185 #define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL))
\r
8186 #define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL))
\r
8187 #define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL))
\r
8188 #define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL))
\r
8189 #define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL))
\r
8190 #define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL))
\r
8192 /* Multifunction Timer unit 0 Input Capture Unit registers */
\r
8193 #define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL))
\r
8194 #define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL))
\r
8195 #define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL))
\r
8196 #define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL))
\r
8197 #define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL))
\r
8198 #define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL))
\r
8199 #define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL))
\r
8200 #define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL))
\r
8201 #define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL))
\r
8202 #define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL))
\r
8203 #define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL))
\r
8204 #define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL))
\r
8205 #define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL))
\r
8206 #define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL))
\r
8207 #define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL))
\r
8208 #define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL))
\r
8209 #define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL))
\r
8210 #define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL))
\r
8211 #define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL))
\r
8212 #define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL))
\r
8213 #define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL))
\r
8214 #define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL))
\r
8215 #define bFM3_MFT0_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42400F18UL))
\r
8216 #define bFM3_MFT0_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42400F1CUL))
\r
8217 #define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL))
\r
8218 #define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL))
\r
8219 #define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL))
\r
8220 #define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL))
\r
8221 #define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL))
\r
8222 #define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL))
\r
8223 #define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL))
\r
8224 #define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL))
\r
8225 #define bFM3_MFT0_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42400F98UL))
\r
8226 #define bFM3_MFT0_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42400F9CUL))
\r
8227 #define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL))
\r
8228 #define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL))
\r
8230 /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
\r
8231 #define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL))
\r
8232 #define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL))
\r
8233 #define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL))
\r
8234 #define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL))
\r
8235 #define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL))
\r
8236 #define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL))
\r
8237 #define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL))
\r
8238 #define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL))
\r
8239 #define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL))
\r
8240 #define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL))
\r
8241 #define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL))
\r
8242 #define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL))
\r
8243 #define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL))
\r
8244 #define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL))
\r
8245 #define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL))
\r
8246 #define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL))
\r
8247 #define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL))
\r
8248 #define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL))
\r
8249 #define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL))
\r
8250 #define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL))
\r
8251 #define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL))
\r
8252 #define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL))
\r
8253 #define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL))
\r
8254 #define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL))
\r
8255 #define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL))
\r
8256 #define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL))
\r
8257 #define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL))
\r
8258 #define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL))
\r
8259 #define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL))
\r
8260 #define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL))
\r
8262 /* Multifunction Timer unit 1 Free Running Timer registers */
\r
8263 #define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL))
\r
8264 #define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL))
\r
8265 #define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL))
\r
8266 #define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL))
\r
8267 #define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL))
\r
8268 #define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL))
\r
8269 #define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL))
\r
8270 #define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL))
\r
8271 #define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL))
\r
8272 #define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL))
\r
8273 #define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL))
\r
8274 #define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL))
\r
8275 #define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL))
\r
8276 #define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL))
\r
8277 #define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL))
\r
8278 #define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL))
\r
8279 #define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL))
\r
8280 #define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL))
\r
8281 #define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL))
\r
8282 #define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL))
\r
8283 #define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL))
\r
8284 #define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL))
\r
8285 #define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL))
\r
8286 #define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL))
\r
8287 #define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL))
\r
8288 #define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL))
\r
8289 #define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL))
\r
8290 #define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL))
\r
8291 #define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL))
\r
8292 #define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL))
\r
8293 #define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL))
\r
8294 #define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL))
\r
8295 #define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL))
\r
8296 #define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL))
\r
8297 #define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL))
\r
8298 #define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL))
\r
8299 #define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL))
\r
8300 #define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL))
\r
8301 #define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL))
\r
8302 #define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL))
\r
8303 #define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL))
\r
8304 #define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL))
\r
8305 #define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL))
\r
8306 #define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL))
\r
8307 #define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL))
\r
8308 #define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL))
\r
8309 #define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL))
\r
8310 #define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL))
\r
8312 /* Multifunction Timer unit 1 Output Compare Unit registers */
\r
8313 #define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL))
\r
8314 #define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL))
\r
8315 #define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL))
\r
8316 #define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL))
\r
8317 #define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL))
\r
8318 #define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL))
\r
8319 #define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL))
\r
8320 #define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL))
\r
8321 #define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL))
\r
8322 #define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL))
\r
8323 #define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL))
\r
8324 #define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL))
\r
8325 #define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL))
\r
8326 #define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL))
\r
8327 #define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL))
\r
8328 #define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL))
\r
8329 #define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL))
\r
8330 #define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL))
\r
8331 #define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL))
\r
8332 #define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL))
\r
8333 #define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL))
\r
8334 #define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL))
\r
8335 #define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL))
\r
8336 #define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL))
\r
8337 #define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL))
\r
8338 #define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL))
\r
8339 #define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL))
\r
8340 #define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL))
\r
8341 #define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL))
\r
8342 #define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL))
\r
8343 #define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL))
\r
8344 #define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL))
\r
8345 #define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL))
\r
8346 #define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL))
\r
8347 #define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL))
\r
8348 #define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL))
\r
8349 #define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL))
\r
8350 #define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL))
\r
8351 #define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL))
\r
8352 #define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL))
\r
8353 #define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL))
\r
8354 #define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL))
\r
8355 #define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL))
\r
8356 #define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL))
\r
8357 #define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL))
\r
8358 #define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL))
\r
8359 #define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL))
\r
8360 #define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL))
\r
8361 #define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL))
\r
8362 #define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL))
\r
8363 #define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL))
\r
8364 #define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL))
\r
8365 #define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL))
\r
8366 #define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL))
\r
8367 #define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL))
\r
8368 #define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL))
\r
8369 #define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL))
\r
8370 #define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL))
\r
8371 #define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL))
\r
8372 #define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL))
\r
8373 #define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL))
\r
8374 #define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL))
\r
8375 #define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL))
\r
8376 #define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL))
\r
8377 #define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL))
\r
8378 #define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL))
\r
8379 #define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL))
\r
8380 #define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL))
\r
8381 #define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL))
\r
8383 /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
\r
8384 #define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL))
\r
8385 #define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL))
\r
8386 #define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL))
\r
8387 #define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL))
\r
8388 #define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL))
\r
8389 #define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL))
\r
8390 #define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL))
\r
8391 #define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL))
\r
8392 #define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL))
\r
8393 #define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL))
\r
8394 #define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL))
\r
8395 #define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL))
\r
8396 #define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL))
\r
8397 #define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL))
\r
8398 #define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL))
\r
8399 #define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL))
\r
8400 #define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL))
\r
8401 #define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL))
\r
8402 #define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL))
\r
8403 #define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL))
\r
8404 #define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL))
\r
8405 #define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL))
\r
8406 #define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL))
\r
8407 #define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL))
\r
8408 #define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL))
\r
8409 #define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL))
\r
8410 #define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL))
\r
8411 #define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL))
\r
8412 #define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL))
\r
8413 #define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL))
\r
8414 #define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL))
\r
8415 #define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL))
\r
8416 #define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL))
\r
8417 #define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL))
\r
8418 #define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL))
\r
8419 #define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL))
\r
8420 #define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL))
\r
8421 #define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL))
\r
8422 #define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL))
\r
8423 #define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL))
\r
8424 #define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL))
\r
8425 #define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL))
\r
8426 #define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL))
\r
8427 #define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL))
\r
8428 #define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL))
\r
8429 #define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL))
\r
8430 #define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL))
\r
8431 #define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL))
\r
8432 #define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL))
\r
8433 #define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL))
\r
8434 #define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL))
\r
8435 #define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL))
\r
8436 #define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL))
\r
8437 #define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL))
\r
8438 #define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL))
\r
8439 #define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL))
\r
8440 #define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL))
\r
8441 #define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL))
\r
8443 /* Multifunction Timer unit 1 Input Capture Unit registers */
\r
8444 #define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL))
\r
8445 #define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL))
\r
8446 #define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL))
\r
8447 #define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL))
\r
8448 #define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL))
\r
8449 #define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL))
\r
8450 #define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL))
\r
8451 #define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL))
\r
8452 #define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL))
\r
8453 #define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL))
\r
8454 #define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL))
\r
8455 #define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL))
\r
8456 #define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL))
\r
8457 #define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL))
\r
8458 #define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL))
\r
8459 #define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL))
\r
8460 #define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL))
\r
8461 #define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL))
\r
8462 #define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL))
\r
8463 #define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL))
\r
8464 #define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL))
\r
8465 #define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL))
\r
8466 #define bFM3_MFT1_ICU_ICSA10_ICP0 *((volatile unsigned int*)(0x42420F18UL))
\r
8467 #define bFM3_MFT1_ICU_ICSA10_ICP1 *((volatile unsigned int*)(0x42420F1CUL))
\r
8468 #define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL))
\r
8469 #define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL))
\r
8470 #define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL))
\r
8471 #define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL))
\r
8472 #define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL))
\r
8473 #define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL))
\r
8474 #define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL))
\r
8475 #define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL))
\r
8476 #define bFM3_MFT1_ICU_ICSA32_ICP2 *((volatile unsigned int*)(0x42420F98UL))
\r
8477 #define bFM3_MFT1_ICU_ICSA32_ICP3 *((volatile unsigned int*)(0x42420F9CUL))
\r
8478 #define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL))
\r
8479 #define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL))
\r
8481 /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
\r
8482 #define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL))
\r
8483 #define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL))
\r
8484 #define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL))
\r
8485 #define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL))
\r
8486 #define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL))
\r
8487 #define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL))
\r
8488 #define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL))
\r
8489 #define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL))
\r
8490 #define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL))
\r
8491 #define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL))
\r
8492 #define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL))
\r
8493 #define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL))
\r
8494 #define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL))
\r
8495 #define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL))
\r
8496 #define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL))
\r
8497 #define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL))
\r
8498 #define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL))
\r
8499 #define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL))
\r
8500 #define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL))
\r
8501 #define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL))
\r
8502 #define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL))
\r
8503 #define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL))
\r
8504 #define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL))
\r
8505 #define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL))
\r
8506 #define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL))
\r
8507 #define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL))
\r
8508 #define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL))
\r
8509 #define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL))
\r
8510 #define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL))
\r
8511 #define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL))
\r
8513 /* Multifunction Timer PPG registers */
\r
8514 #define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL))
\r
8515 #define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL))
\r
8516 #define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL))
\r
8517 #define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL))
\r
8518 #define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL))
\r
8519 #define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL))
\r
8520 #define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL))
\r
8521 #define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL))
\r
8522 #define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL))
\r
8523 #define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL))
\r
8524 #define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL))
\r
8525 #define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL))
\r
8526 #define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL))
\r
8527 #define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL))
\r
8528 #define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL))
\r
8529 #define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL))
\r
8530 #define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL))
\r
8531 #define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL))
\r
8532 #define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL))
\r
8533 #define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL))
\r
8534 #define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL))
\r
8535 #define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL))
\r
8536 #define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL))
\r
8537 #define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL))
\r
8538 #define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL))
\r
8539 #define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL))
\r
8540 #define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL))
\r
8541 #define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL))
\r
8542 #define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL))
\r
8543 #define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL))
\r
8544 #define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL))
\r
8545 #define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL))
\r
8546 #define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL))
\r
8547 #define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL))
\r
8548 #define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL))
\r
8549 #define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL))
\r
8550 #define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL))
\r
8551 #define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL))
\r
8552 #define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL))
\r
8553 #define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL))
\r
8554 #define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL))
\r
8555 #define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL))
\r
8556 #define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL))
\r
8557 #define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL))
\r
8558 #define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL))
\r
8559 #define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL))
\r
8560 #define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL))
\r
8561 #define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL))
\r
8562 #define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL))
\r
8563 #define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL))
\r
8564 #define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL))
\r
8565 #define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL))
\r
8566 #define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL))
\r
8567 #define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL))
\r
8568 #define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL))
\r
8569 #define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL))
\r
8570 #define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL))
\r
8571 #define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL))
\r
8572 #define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL))
\r
8573 #define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL))
\r
8574 #define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL))
\r
8575 #define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL))
\r
8576 #define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL))
\r
8577 #define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL))
\r
8578 #define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL))
\r
8579 #define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL))
\r
8580 #define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL))
\r
8581 #define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL))
\r
8582 #define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL))
\r
8583 #define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL))
\r
8584 #define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL))
\r
8585 #define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL))
\r
8586 #define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL))
\r
8587 #define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL))
\r
8588 #define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL))
\r
8589 #define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL))
\r
8590 #define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL))
\r
8591 #define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL))
\r
8592 #define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL))
\r
8593 #define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL))
\r
8594 #define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL))
\r
8595 #define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL))
\r
8596 #define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL))
\r
8597 #define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL))
\r
8598 #define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL))
\r
8599 #define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL))
\r
8600 #define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL))
\r
8601 #define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL))
\r
8602 #define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL))
\r
8603 #define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL))
\r
8604 #define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL))
\r
8605 #define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL))
\r
8606 #define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL))
\r
8607 #define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL))
\r
8608 #define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL))
\r
8609 #define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL))
\r
8610 #define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL))
\r
8611 #define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL))
\r
8612 #define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL))
\r
8613 #define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL))
\r
8614 #define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL))
\r
8615 #define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL))
\r
8616 #define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL))
\r
8617 #define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL))
\r
8618 #define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL))
\r
8619 #define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL))
\r
8620 #define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL))
\r
8621 #define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL))
\r
8622 #define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL))
\r
8623 #define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL))
\r
8624 #define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL))
\r
8625 #define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL))
\r
8626 #define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL))
\r
8627 #define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL))
\r
8628 #define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL))
\r
8629 #define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL))
\r
8630 #define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL))
\r
8631 #define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL))
\r
8632 #define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL))
\r
8633 #define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL))
\r
8634 #define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL))
\r
8635 #define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL))
\r
8636 #define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL))
\r
8637 #define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL))
\r
8638 #define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL))
\r
8639 #define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL))
\r
8640 #define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL))
\r
8641 #define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL))
\r
8642 #define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL))
\r
8643 #define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL))
\r
8644 #define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL))
\r
8645 #define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL))
\r
8646 #define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL))
\r
8647 #define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL))
\r
8648 #define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL))
\r
8649 #define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL))
\r
8650 #define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL))
\r
8651 #define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL))
\r
8652 #define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL))
\r
8653 #define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL))
\r
8654 #define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL))
\r
8655 #define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL))
\r
8656 #define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL))
\r
8657 #define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL))
\r
8658 #define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL))
\r
8659 #define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL))
\r
8660 #define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL))
\r
8661 #define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL))
\r
8662 #define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL))
\r
8663 #define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL))
\r
8664 #define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL))
\r
8665 #define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL))
\r
8666 #define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL))
\r
8667 #define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL))
\r
8668 #define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL))
\r
8669 #define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL))
\r
8670 #define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL))
\r
8671 #define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL))
\r
8672 #define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL))
\r
8673 #define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL))
\r
8674 #define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL))
\r
8675 #define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL))
\r
8676 #define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL))
\r
8677 #define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL))
\r
8678 #define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL))
\r
8679 #define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL))
\r
8680 #define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL))
\r
8681 #define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL))
\r
8682 #define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL))
\r
8683 #define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL))
\r
8684 #define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL))
\r
8685 #define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL))
\r
8686 #define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL))
\r
8687 #define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL))
\r
8688 #define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL))
\r
8689 #define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL))
\r
8690 #define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL))
\r
8691 #define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL))
\r
8692 #define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL))
\r
8693 #define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL))
\r
8694 #define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL))
\r
8695 #define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL))
\r
8696 #define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL))
\r
8697 #define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL))
\r
8698 #define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL))
\r
8699 #define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL))
\r
8700 #define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL))
\r
8701 #define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL))
\r
8702 #define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL))
\r
8703 #define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL))
\r
8704 #define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL))
\r
8705 #define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL))
\r
8707 /* Base Timer 0 PPG registers */
\r
8708 #define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL))
\r
8709 #define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL))
\r
8710 #define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL))
\r
8711 #define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL))
\r
8712 #define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL))
\r
8713 #define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL))
\r
8714 #define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL))
\r
8715 #define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL))
\r
8716 #define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL))
\r
8717 #define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL))
\r
8718 #define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL))
\r
8719 #define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL))
\r
8720 #define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL))
\r
8721 #define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL))
\r
8722 #define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL))
\r
8723 #define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL))
\r
8724 #define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL))
\r
8725 #define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL))
\r
8726 #define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL))
\r
8728 /* Base Timer 0 PWM registers */
\r
8729 #define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL))
\r
8730 #define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL))
\r
8731 #define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL))
\r
8732 #define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL))
\r
8733 #define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL))
\r
8734 #define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL))
\r
8735 #define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL))
\r
8736 #define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL))
\r
8737 #define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL))
\r
8738 #define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL))
\r
8739 #define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL))
\r
8740 #define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL))
\r
8741 #define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL))
\r
8742 #define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL))
\r
8743 #define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL))
\r
8744 #define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL))
\r
8745 #define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL))
\r
8746 #define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL))
\r
8747 #define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL))
\r
8748 #define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL))
\r
8749 #define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL))
\r
8751 /* Base Timer 0 RT registers */
\r
8752 #define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL))
\r
8753 #define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL))
\r
8754 #define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL))
\r
8755 #define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL))
\r
8756 #define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL))
\r
8757 #define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL))
\r
8758 #define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL))
\r
8759 #define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL))
\r
8760 #define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL))
\r
8761 #define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL))
\r
8762 #define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL))
\r
8763 #define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL))
\r
8764 #define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL))
\r
8765 #define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL))
\r
8766 #define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL))
\r
8767 #define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL))
\r
8768 #define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL))
\r
8769 #define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL))
\r
8771 /* Base Timer 0 PWC registers */
\r
8772 #define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL))
\r
8773 #define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL))
\r
8774 #define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL))
\r
8775 #define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL))
\r
8776 #define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL))
\r
8777 #define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL))
\r
8778 #define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL))
\r
8779 #define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL))
\r
8780 #define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL))
\r
8781 #define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL))
\r
8782 #define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL))
\r
8783 #define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL))
\r
8784 #define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL))
\r
8785 #define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL))
\r
8786 #define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL))
\r
8787 #define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL))
\r
8788 #define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL))
\r
8789 #define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL))
\r
8791 /* Base Timer 1 PPG registers */
\r
8792 #define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL))
\r
8793 #define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL))
\r
8794 #define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL))
\r
8795 #define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL))
\r
8796 #define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL))
\r
8797 #define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL))
\r
8798 #define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL))
\r
8799 #define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL))
\r
8800 #define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL))
\r
8801 #define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL))
\r
8802 #define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL))
\r
8803 #define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL))
\r
8804 #define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL))
\r
8805 #define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL))
\r
8806 #define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL))
\r
8807 #define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL))
\r
8808 #define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL))
\r
8809 #define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL))
\r
8810 #define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL))
\r
8812 /* Base Timer 1 PWM registers */
\r
8813 #define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL))
\r
8814 #define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL))
\r
8815 #define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL))
\r
8816 #define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL))
\r
8817 #define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL))
\r
8818 #define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL))
\r
8819 #define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL))
\r
8820 #define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL))
\r
8821 #define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL))
\r
8822 #define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL))
\r
8823 #define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL))
\r
8824 #define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL))
\r
8825 #define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL))
\r
8826 #define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL))
\r
8827 #define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL))
\r
8828 #define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL))
\r
8829 #define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL))
\r
8830 #define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL))
\r
8831 #define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL))
\r
8832 #define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL))
\r
8833 #define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL))
\r
8835 /* Base Timer 1 RT registers */
\r
8836 #define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL))
\r
8837 #define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL))
\r
8838 #define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL))
\r
8839 #define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL))
\r
8840 #define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL))
\r
8841 #define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL))
\r
8842 #define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL))
\r
8843 #define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL))
\r
8844 #define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL))
\r
8845 #define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL))
\r
8846 #define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL))
\r
8847 #define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL))
\r
8848 #define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL))
\r
8849 #define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL))
\r
8850 #define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL))
\r
8851 #define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL))
\r
8852 #define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL))
\r
8853 #define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL))
\r
8855 /* Base Timer 1 PWC registers */
\r
8856 #define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL))
\r
8857 #define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL))
\r
8858 #define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL))
\r
8859 #define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL))
\r
8860 #define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL))
\r
8861 #define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL))
\r
8862 #define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL))
\r
8863 #define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL))
\r
8864 #define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL))
\r
8865 #define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL))
\r
8866 #define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL))
\r
8867 #define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL))
\r
8868 #define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL))
\r
8869 #define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL))
\r
8870 #define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL))
\r
8871 #define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL))
\r
8872 #define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL))
\r
8873 #define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL))
\r
8875 /* Base Timer 2 PPG registers */
\r
8876 #define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL))
\r
8877 #define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL))
\r
8878 #define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL))
\r
8879 #define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL))
\r
8880 #define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL))
\r
8881 #define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL))
\r
8882 #define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL))
\r
8883 #define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL))
\r
8884 #define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL))
\r
8885 #define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL))
\r
8886 #define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL))
\r
8887 #define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL))
\r
8888 #define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL))
\r
8889 #define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL))
\r
8890 #define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL))
\r
8891 #define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL))
\r
8892 #define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL))
\r
8893 #define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL))
\r
8894 #define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL))
\r
8896 /* Base Timer 2 PWM registers */
\r
8897 #define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL))
\r
8898 #define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL))
\r
8899 #define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL))
\r
8900 #define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL))
\r
8901 #define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL))
\r
8902 #define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL))
\r
8903 #define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL))
\r
8904 #define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL))
\r
8905 #define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL))
\r
8906 #define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL))
\r
8907 #define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL))
\r
8908 #define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL))
\r
8909 #define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL))
\r
8910 #define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL))
\r
8911 #define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL))
\r
8912 #define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL))
\r
8913 #define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL))
\r
8914 #define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL))
\r
8915 #define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL))
\r
8916 #define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL))
\r
8917 #define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL))
\r
8919 /* Base Timer 2 RT registers */
\r
8920 #define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL))
\r
8921 #define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL))
\r
8922 #define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL))
\r
8923 #define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL))
\r
8924 #define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL))
\r
8925 #define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL))
\r
8926 #define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL))
\r
8927 #define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL))
\r
8928 #define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL))
\r
8929 #define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL))
\r
8930 #define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL))
\r
8931 #define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL))
\r
8932 #define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL))
\r
8933 #define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL))
\r
8934 #define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL))
\r
8935 #define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL))
\r
8936 #define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL))
\r
8937 #define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL))
\r
8939 /* Base Timer 2 PWC registers */
\r
8940 #define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL))
\r
8941 #define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL))
\r
8942 #define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL))
\r
8943 #define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL))
\r
8944 #define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL))
\r
8945 #define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL))
\r
8946 #define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL))
\r
8947 #define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL))
\r
8948 #define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL))
\r
8949 #define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL))
\r
8950 #define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL))
\r
8951 #define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL))
\r
8952 #define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL))
\r
8953 #define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL))
\r
8954 #define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL))
\r
8955 #define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL))
\r
8956 #define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL))
\r
8957 #define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL))
\r
8959 /* Base Timer 3 PPG registers */
\r
8960 #define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL))
\r
8961 #define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL))
\r
8962 #define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL))
\r
8963 #define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL))
\r
8964 #define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL))
\r
8965 #define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL))
\r
8966 #define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL))
\r
8967 #define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL))
\r
8968 #define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL))
\r
8969 #define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL))
\r
8970 #define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL))
\r
8971 #define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL))
\r
8972 #define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL))
\r
8973 #define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL))
\r
8974 #define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL))
\r
8975 #define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL))
\r
8976 #define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL))
\r
8977 #define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL))
\r
8978 #define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL))
\r
8980 /* Base Timer 3 PWM registers */
\r
8981 #define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL))
\r
8982 #define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL))
\r
8983 #define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL))
\r
8984 #define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL))
\r
8985 #define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL))
\r
8986 #define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL))
\r
8987 #define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL))
\r
8988 #define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL))
\r
8989 #define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL))
\r
8990 #define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL))
\r
8991 #define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL))
\r
8992 #define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL))
\r
8993 #define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL))
\r
8994 #define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL))
\r
8995 #define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL))
\r
8996 #define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL))
\r
8997 #define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL))
\r
8998 #define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL))
\r
8999 #define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL))
\r
9000 #define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL))
\r
9001 #define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL))
\r
9003 /* Base Timer 3 RT registers */
\r
9004 #define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL))
\r
9005 #define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL))
\r
9006 #define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL))
\r
9007 #define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL))
\r
9008 #define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL))
\r
9009 #define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL))
\r
9010 #define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL))
\r
9011 #define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL))
\r
9012 #define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL))
\r
9013 #define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL))
\r
9014 #define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL))
\r
9015 #define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL))
\r
9016 #define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL))
\r
9017 #define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL))
\r
9018 #define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL))
\r
9019 #define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL))
\r
9020 #define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL))
\r
9021 #define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL))
\r
9023 /* Base Timer 3 PWC registers */
\r
9024 #define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL))
\r
9025 #define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL))
\r
9026 #define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL))
\r
9027 #define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL))
\r
9028 #define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL))
\r
9029 #define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL))
\r
9030 #define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL))
\r
9031 #define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL))
\r
9032 #define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL))
\r
9033 #define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL))
\r
9034 #define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL))
\r
9035 #define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL))
\r
9036 #define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL))
\r
9037 #define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL))
\r
9038 #define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL))
\r
9039 #define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL))
\r
9040 #define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL))
\r
9041 #define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL))
\r
9043 /* Base Timer 4 PPG registers */
\r
9044 #define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL))
\r
9045 #define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL))
\r
9046 #define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL))
\r
9047 #define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL))
\r
9048 #define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL))
\r
9049 #define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL))
\r
9050 #define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL))
\r
9051 #define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL))
\r
9052 #define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL))
\r
9053 #define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL))
\r
9054 #define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL))
\r
9055 #define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL))
\r
9056 #define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL))
\r
9057 #define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL))
\r
9058 #define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL))
\r
9059 #define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL))
\r
9060 #define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL))
\r
9061 #define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL))
\r
9062 #define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL))
\r
9064 /* Base Timer 4 PWM registers */
\r
9065 #define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL))
\r
9066 #define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL))
\r
9067 #define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL))
\r
9068 #define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL))
\r
9069 #define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL))
\r
9070 #define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL))
\r
9071 #define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL))
\r
9072 #define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL))
\r
9073 #define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL))
\r
9074 #define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL))
\r
9075 #define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL))
\r
9076 #define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL))
\r
9077 #define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL))
\r
9078 #define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL))
\r
9079 #define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL))
\r
9080 #define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL))
\r
9081 #define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL))
\r
9082 #define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL))
\r
9083 #define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL))
\r
9084 #define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL))
\r
9085 #define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL))
\r
9087 /* Base Timer 4 RT registers */
\r
9088 #define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL))
\r
9089 #define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL))
\r
9090 #define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL))
\r
9091 #define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL))
\r
9092 #define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL))
\r
9093 #define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL))
\r
9094 #define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL))
\r
9095 #define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL))
\r
9096 #define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL))
\r
9097 #define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL))
\r
9098 #define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL))
\r
9099 #define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL))
\r
9100 #define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL))
\r
9101 #define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL))
\r
9102 #define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL))
\r
9103 #define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL))
\r
9104 #define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL))
\r
9105 #define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL))
\r
9107 /* Base Timer 4 PWC registers */
\r
9108 #define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL))
\r
9109 #define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL))
\r
9110 #define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL))
\r
9111 #define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL))
\r
9112 #define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL))
\r
9113 #define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL))
\r
9114 #define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL))
\r
9115 #define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL))
\r
9116 #define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL))
\r
9117 #define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL))
\r
9118 #define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL))
\r
9119 #define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL))
\r
9120 #define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL))
\r
9121 #define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL))
\r
9122 #define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL))
\r
9123 #define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL))
\r
9124 #define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL))
\r
9125 #define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL))
\r
9127 /* Base Timer 5 PPG registers */
\r
9128 #define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL))
\r
9129 #define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL))
\r
9130 #define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL))
\r
9131 #define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL))
\r
9132 #define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL))
\r
9133 #define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL))
\r
9134 #define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL))
\r
9135 #define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL))
\r
9136 #define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL))
\r
9137 #define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL))
\r
9138 #define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL))
\r
9139 #define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL))
\r
9140 #define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL))
\r
9141 #define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL))
\r
9142 #define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL))
\r
9143 #define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL))
\r
9144 #define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL))
\r
9145 #define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL))
\r
9146 #define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL))
\r
9148 /* Base Timer 5 PWM registers */
\r
9149 #define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL))
\r
9150 #define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL))
\r
9151 #define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL))
\r
9152 #define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL))
\r
9153 #define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL))
\r
9154 #define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL))
\r
9155 #define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL))
\r
9156 #define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL))
\r
9157 #define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL))
\r
9158 #define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL))
\r
9159 #define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL))
\r
9160 #define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL))
\r
9161 #define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL))
\r
9162 #define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL))
\r
9163 #define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL))
\r
9164 #define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL))
\r
9165 #define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL))
\r
9166 #define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL))
\r
9167 #define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL))
\r
9168 #define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL))
\r
9169 #define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL))
\r
9171 /* Base Timer 5 RT registers */
\r
9172 #define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL))
\r
9173 #define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL))
\r
9174 #define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL))
\r
9175 #define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL))
\r
9176 #define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL))
\r
9177 #define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL))
\r
9178 #define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL))
\r
9179 #define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL))
\r
9180 #define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL))
\r
9181 #define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL))
\r
9182 #define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL))
\r
9183 #define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL))
\r
9184 #define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL))
\r
9185 #define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL))
\r
9186 #define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL))
\r
9187 #define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL))
\r
9188 #define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL))
\r
9189 #define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL))
\r
9191 /* Base Timer 5 PWC registers */
\r
9192 #define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL))
\r
9193 #define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL))
\r
9194 #define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL))
\r
9195 #define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL))
\r
9196 #define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL))
\r
9197 #define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL))
\r
9198 #define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL))
\r
9199 #define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL))
\r
9200 #define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL))
\r
9201 #define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL))
\r
9202 #define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL))
\r
9203 #define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL))
\r
9204 #define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL))
\r
9205 #define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL))
\r
9206 #define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL))
\r
9207 #define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL))
\r
9208 #define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL))
\r
9209 #define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL))
\r
9211 /* Base Timer 6 PPG registers */
\r
9212 #define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL))
\r
9213 #define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL))
\r
9214 #define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL))
\r
9215 #define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL))
\r
9216 #define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL))
\r
9217 #define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL))
\r
9218 #define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL))
\r
9219 #define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL))
\r
9220 #define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL))
\r
9221 #define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL))
\r
9222 #define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL))
\r
9223 #define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL))
\r
9224 #define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL))
\r
9225 #define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL))
\r
9226 #define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL))
\r
9227 #define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL))
\r
9228 #define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL))
\r
9229 #define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL))
\r
9230 #define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL))
\r
9232 /* Base Timer 6 PWM registers */
\r
9233 #define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL))
\r
9234 #define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL))
\r
9235 #define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL))
\r
9236 #define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL))
\r
9237 #define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL))
\r
9238 #define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL))
\r
9239 #define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL))
\r
9240 #define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL))
\r
9241 #define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL))
\r
9242 #define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL))
\r
9243 #define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL))
\r
9244 #define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL))
\r
9245 #define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL))
\r
9246 #define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL))
\r
9247 #define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL))
\r
9248 #define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL))
\r
9249 #define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL))
\r
9250 #define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL))
\r
9251 #define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL))
\r
9252 #define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL))
\r
9253 #define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL))
\r
9255 /* Base Timer 6 RT registers */
\r
9256 #define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL))
\r
9257 #define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL))
\r
9258 #define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL))
\r
9259 #define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL))
\r
9260 #define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL))
\r
9261 #define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL))
\r
9262 #define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL))
\r
9263 #define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL))
\r
9264 #define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL))
\r
9265 #define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL))
\r
9266 #define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL))
\r
9267 #define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL))
\r
9268 #define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL))
\r
9269 #define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL))
\r
9270 #define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL))
\r
9271 #define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL))
\r
9272 #define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL))
\r
9273 #define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL))
\r
9275 /* Base Timer 6 PWC registers */
\r
9276 #define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL))
\r
9277 #define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL))
\r
9278 #define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL))
\r
9279 #define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL))
\r
9280 #define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL))
\r
9281 #define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL))
\r
9282 #define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL))
\r
9283 #define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL))
\r
9284 #define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL))
\r
9285 #define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL))
\r
9286 #define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL))
\r
9287 #define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL))
\r
9288 #define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL))
\r
9289 #define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL))
\r
9290 #define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL))
\r
9291 #define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL))
\r
9292 #define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL))
\r
9293 #define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL))
\r
9295 /* Base Timer 7 PPG registers */
\r
9296 #define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL))
\r
9297 #define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL))
\r
9298 #define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL))
\r
9299 #define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL))
\r
9300 #define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL))
\r
9301 #define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL))
\r
9302 #define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL))
\r
9303 #define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL))
\r
9304 #define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL))
\r
9305 #define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL))
\r
9306 #define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL))
\r
9307 #define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL))
\r
9308 #define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL))
\r
9309 #define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL))
\r
9310 #define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL))
\r
9311 #define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL))
\r
9312 #define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL))
\r
9313 #define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL))
\r
9314 #define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL))
\r
9316 /* Base Timer 7 PWM registers */
\r
9317 #define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL))
\r
9318 #define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL))
\r
9319 #define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL))
\r
9320 #define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL))
\r
9321 #define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL))
\r
9322 #define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL))
\r
9323 #define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL))
\r
9324 #define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL))
\r
9325 #define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL))
\r
9326 #define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL))
\r
9327 #define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL))
\r
9328 #define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL))
\r
9329 #define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL))
\r
9330 #define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL))
\r
9331 #define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL))
\r
9332 #define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL))
\r
9333 #define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL))
\r
9334 #define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL))
\r
9335 #define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL))
\r
9336 #define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL))
\r
9337 #define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL))
\r
9339 /* Base Timer 7 RT registers */
\r
9340 #define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL))
\r
9341 #define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL))
\r
9342 #define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL))
\r
9343 #define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL))
\r
9344 #define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL))
\r
9345 #define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL))
\r
9346 #define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL))
\r
9347 #define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL))
\r
9348 #define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL))
\r
9349 #define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL))
\r
9350 #define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL))
\r
9351 #define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL))
\r
9352 #define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL))
\r
9353 #define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL))
\r
9354 #define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL))
\r
9355 #define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL))
\r
9356 #define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL))
\r
9357 #define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL))
\r
9359 /* Base Timer 7 PWC registers */
\r
9360 #define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL))
\r
9361 #define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL))
\r
9362 #define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL))
\r
9363 #define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL))
\r
9364 #define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL))
\r
9365 #define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL))
\r
9366 #define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL))
\r
9367 #define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL))
\r
9368 #define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL))
\r
9369 #define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL))
\r
9370 #define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL))
\r
9371 #define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL))
\r
9372 #define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL))
\r
9373 #define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL))
\r
9374 #define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL))
\r
9375 #define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL))
\r
9376 #define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL))
\r
9377 #define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL))
\r
9379 /* Base Timer I/O selector channel 0 - channel 3 registers */
\r
9380 #define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL))
\r
9381 #define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL))
\r
9382 #define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL))
\r
9383 #define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL))
\r
9384 #define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL))
\r
9385 #define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL))
\r
9386 #define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL))
\r
9387 #define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL))
\r
9389 /* Base Timer I/O selector channel 4 - channel 7 registers */
\r
9390 #define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL))
\r
9391 #define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL))
\r
9392 #define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL))
\r
9393 #define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL))
\r
9394 #define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL))
\r
9395 #define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL))
\r
9396 #define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL))
\r
9397 #define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL))
\r
9399 /* Software based Simulation Startup (Base Timer) register */
\r
9400 #define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL))
\r
9401 #define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL))
\r
9402 #define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL))
\r
9403 #define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL))
\r
9404 #define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL))
\r
9405 #define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL))
\r
9406 #define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL))
\r
9407 #define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL))
\r
9408 #define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL))
\r
9409 #define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL))
\r
9410 #define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL))
\r
9411 #define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL))
\r
9412 #define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL))
\r
9413 #define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL))
\r
9414 #define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL))
\r
9415 #define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL))
\r
9417 /* Quad position and revolution counter channel 0 registers */
\r
9418 #define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL))
\r
9419 #define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL))
\r
9420 #define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL))
\r
9421 #define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL))
\r
9422 #define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL))
\r
9423 #define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL))
\r
9424 #define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL))
\r
9425 #define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL))
\r
9426 #define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL))
\r
9427 #define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL))
\r
9428 #define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL))
\r
9429 #define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL))
\r
9430 #define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL))
\r
9431 #define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL))
\r
9432 #define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL))
\r
9433 #define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL))
\r
9434 #define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL))
\r
9435 #define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL))
\r
9436 #define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL))
\r
9437 #define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL))
\r
9438 #define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL))
\r
9439 #define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL))
\r
9440 #define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL))
\r
9441 #define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL))
\r
9442 #define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL))
\r
9443 #define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL))
\r
9444 #define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL))
\r
9445 #define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL))
\r
9446 #define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL))
\r
9447 #define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL))
\r
9448 #define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL))
\r
9449 #define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL))
\r
9450 #define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL))
\r
9451 #define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL))
\r
9452 #define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL))
\r
9453 #define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL))
\r
9454 #define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL))
\r
9455 #define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL))
\r
9456 #define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL))
\r
9457 #define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL))
\r
9458 #define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL))
\r
9459 #define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL))
\r
9460 #define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL))
\r
9461 #define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL))
\r
9462 #define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL))
\r
9463 #define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL))
\r
9464 #define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL))
\r
9465 #define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL))
\r
9466 #define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL))
\r
9467 #define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL))
\r
9468 #define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL))
\r
9469 #define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL))
\r
9470 #define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL))
\r
9471 #define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL))
\r
9472 #define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL))
\r
9473 #define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL))
\r
9474 #define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL))
\r
9475 #define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL))
\r
9476 #define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL))
\r
9477 #define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL))
\r
9478 #define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL))
\r
9479 #define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL))
\r
9480 #define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL))
\r
9482 /* Quad position and revolution counter channel 1 registers */
\r
9483 #define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL))
\r
9484 #define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL))
\r
9485 #define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL))
\r
9486 #define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL))
\r
9487 #define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL))
\r
9488 #define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL))
\r
9489 #define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL))
\r
9490 #define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL))
\r
9491 #define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL))
\r
9492 #define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL))
\r
9493 #define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL))
\r
9494 #define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL))
\r
9495 #define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL))
\r
9496 #define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL))
\r
9497 #define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL))
\r
9498 #define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL))
\r
9499 #define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL))
\r
9500 #define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL))
\r
9501 #define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL))
\r
9502 #define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL))
\r
9503 #define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL))
\r
9504 #define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL))
\r
9505 #define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL))
\r
9506 #define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL))
\r
9507 #define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL))
\r
9508 #define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL))
\r
9509 #define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL))
\r
9510 #define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL))
\r
9511 #define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL))
\r
9512 #define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL))
\r
9513 #define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL))
\r
9514 #define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL))
\r
9515 #define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL))
\r
9516 #define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL))
\r
9517 #define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL))
\r
9518 #define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL))
\r
9519 #define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL))
\r
9520 #define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL))
\r
9521 #define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL))
\r
9522 #define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL))
\r
9523 #define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL))
\r
9524 #define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL))
\r
9525 #define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL))
\r
9526 #define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL))
\r
9527 #define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL))
\r
9528 #define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL))
\r
9529 #define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL))
\r
9530 #define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL))
\r
9531 #define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL))
\r
9532 #define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL))
\r
9533 #define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL))
\r
9534 #define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL))
\r
9535 #define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL))
\r
9536 #define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL))
\r
9537 #define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL))
\r
9538 #define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL))
\r
9539 #define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL))
\r
9540 #define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL))
\r
9541 #define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL))
\r
9542 #define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL))
\r
9543 #define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL))
\r
9544 #define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL))
\r
9545 #define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL))
\r
9547 /* 12-bit ADC unit 0 registers */
\r
9548 #define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL))
\r
9549 #define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL))
\r
9550 #define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL))
\r
9551 #define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL))
\r
9552 #define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL))
\r
9553 #define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL))
\r
9554 #define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL))
\r
9555 #define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL))
\r
9556 #define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL))
\r
9557 #define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL))
\r
9558 #define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL))
\r
9559 #define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL))
\r
9560 #define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL))
\r
9561 #define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL))
\r
9562 #define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL))
\r
9563 #define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL))
\r
9564 #define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL))
\r
9565 #define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL))
\r
9566 #define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL))
\r
9567 #define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL))
\r
9568 #define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL))
\r
9569 #define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL))
\r
9570 #define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL))
\r
9571 #define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL))
\r
9572 #define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL))
\r
9573 #define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL))
\r
9574 #define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL))
\r
9575 #define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL))
\r
9576 #define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL))
\r
9577 #define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL))
\r
9578 #define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL))
\r
9579 #define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL))
\r
9580 #define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL))
\r
9581 #define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL))
\r
9582 #define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL))
\r
9583 #define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL))
\r
9584 #define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL))
\r
9585 #define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL))
\r
9586 #define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL))
\r
9587 #define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL))
\r
9588 #define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL))
\r
9589 #define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL))
\r
9590 #define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL))
\r
9591 #define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL))
\r
9592 #define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL))
\r
9593 #define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL))
\r
9594 #define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL))
\r
9595 #define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL))
\r
9596 #define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL))
\r
9597 #define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL))
\r
9598 #define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL))
\r
9599 #define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL))
\r
9600 #define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL))
\r
9601 #define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL))
\r
9602 #define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL))
\r
9603 #define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL))
\r
9604 #define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL))
\r
9605 #define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL))
\r
9606 #define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL))
\r
9607 #define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL))
\r
9608 #define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL))
\r
9609 #define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL))
\r
9610 #define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL))
\r
9611 #define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL))
\r
9612 #define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL))
\r
9613 #define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL))
\r
9614 #define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL))
\r
9615 #define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL))
\r
9616 #define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL))
\r
9617 #define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL))
\r
9618 #define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL))
\r
9619 #define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL))
\r
9620 #define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL))
\r
9621 #define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL))
\r
9622 #define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL))
\r
9623 #define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL))
\r
9624 #define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL))
\r
9625 #define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL))
\r
9626 #define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL))
\r
9627 #define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL))
\r
9628 #define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL))
\r
9629 #define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL))
\r
9630 #define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL))
\r
9631 #define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL))
\r
9632 #define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL))
\r
9633 #define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL))
\r
9634 #define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL))
\r
9635 #define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL))
\r
9636 #define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL))
\r
9637 #define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL))
\r
9638 #define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL))
\r
9639 #define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL))
\r
9640 #define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL))
\r
9641 #define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL))
\r
9642 #define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL))
\r
9643 #define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL))
\r
9644 #define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL))
\r
9645 #define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL))
\r
9646 #define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL))
\r
9647 #define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL))
\r
9648 #define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL))
\r
9649 #define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL))
\r
9650 #define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL))
\r
9651 #define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL))
\r
9652 #define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL))
\r
9653 #define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL))
\r
9654 #define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL))
\r
9655 #define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL))
\r
9656 #define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL))
\r
9657 #define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL))
\r
9658 #define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL))
\r
9659 #define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL))
\r
9660 #define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL))
\r
9661 #define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL))
\r
9662 #define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL))
\r
9663 #define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL))
\r
9664 #define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL))
\r
9665 #define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL))
\r
9666 #define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL))
\r
9667 #define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL))
\r
9668 #define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL))
\r
9669 #define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL))
\r
9670 #define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL))
\r
9671 #define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL))
\r
9672 #define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL))
\r
9673 #define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL))
\r
9674 #define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL))
\r
9675 #define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL))
\r
9676 #define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL))
\r
9677 #define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL))
\r
9678 #define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL))
\r
9679 #define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL))
\r
9680 #define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL))
\r
9681 #define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL))
\r
9682 #define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL))
\r
9683 #define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL))
\r
9684 #define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL))
\r
9685 #define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL))
\r
9686 #define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL))
\r
9687 #define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL))
\r
9688 #define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL))
\r
9689 #define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL))
\r
9690 #define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL))
\r
9691 #define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL))
\r
9692 #define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL))
\r
9693 #define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL))
\r
9694 #define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL))
\r
9695 #define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL))
\r
9696 #define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL))
\r
9697 #define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL))
\r
9698 #define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL))
\r
9699 #define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL))
\r
9700 #define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL))
\r
9701 #define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL))
\r
9702 #define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL))
\r
9703 #define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL))
\r
9704 #define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL))
\r
9705 #define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL))
\r
9706 #define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL))
\r
9707 #define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL))
\r
9708 #define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL))
\r
9709 #define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL))
\r
9710 #define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL))
\r
9711 #define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL))
\r
9712 #define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL))
\r
9713 #define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL))
\r
9714 #define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL))
\r
9715 #define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL))
\r
9716 #define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL))
\r
9717 #define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL))
\r
9718 #define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL))
\r
9719 #define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL))
\r
9720 #define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL))
\r
9721 #define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL))
\r
9722 #define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL))
\r
9723 #define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL))
\r
9724 #define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL))
\r
9725 #define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL))
\r
9726 #define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL))
\r
9727 #define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL))
\r
9728 #define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL))
\r
9729 #define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL))
\r
9730 #define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL))
\r
9731 #define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL))
\r
9732 #define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL))
\r
9733 #define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL))
\r
9734 #define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL))
\r
9735 #define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL))
\r
9736 #define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL))
\r
9737 #define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL))
\r
9738 #define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL))
\r
9739 #define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL))
\r
9740 #define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL))
\r
9741 #define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL))
\r
9742 #define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL))
\r
9743 #define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL))
\r
9744 #define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL))
\r
9745 #define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL))
\r
9746 #define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL))
\r
9747 #define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL))
\r
9748 #define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL))
\r
9749 #define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL))
\r
9750 #define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL))
\r
9751 #define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL))
\r
9752 #define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL))
\r
9753 #define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL))
\r
9754 #define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL))
\r
9755 #define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL))
\r
9756 #define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL))
\r
9757 #define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL))
\r
9758 #define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL))
\r
9759 #define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL))
\r
9760 #define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL))
\r
9761 #define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL))
\r
9762 #define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL))
\r
9763 #define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL))
\r
9764 #define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL))
\r
9765 #define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL))
\r
9766 #define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL))
\r
9767 #define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL))
\r
9768 #define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL))
\r
9769 #define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL))
\r
9770 #define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL))
\r
9771 #define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL))
\r
9772 #define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL))
\r
9773 #define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL))
\r
9774 #define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL))
\r
9775 #define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL))
\r
9776 #define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL))
\r
9777 #define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL))
\r
9778 #define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL))
\r
9779 #define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL))
\r
9780 #define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL))
\r
9781 #define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL))
\r
9782 #define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL))
\r
9783 #define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL))
\r
9784 #define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL))
\r
9785 #define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL))
\r
9786 #define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL))
\r
9787 #define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL))
\r
9788 #define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL))
\r
9789 #define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL))
\r
9790 #define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL))
\r
9791 #define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL))
\r
9792 #define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL))
\r
9793 #define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL))
\r
9794 #define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL))
\r
9795 #define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL))
\r
9796 #define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL))
\r
9797 #define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL))
\r
9798 #define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL))
\r
9799 #define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL))
\r
9800 #define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL))
\r
9801 #define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL))
\r
9802 #define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL))
\r
9803 #define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL))
\r
9804 #define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL))
\r
9805 #define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL))
\r
9806 #define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL))
\r
9807 #define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL))
\r
9808 #define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL))
\r
9809 #define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL))
\r
9810 #define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL))
\r
9811 #define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL))
\r
9812 #define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL))
\r
9813 #define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL))
\r
9814 #define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL))
\r
9815 #define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL))
\r
9816 #define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL))
\r
9817 #define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL))
\r
9818 #define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL))
\r
9819 #define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL))
\r
9820 #define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL))
\r
9821 #define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL))
\r
9822 #define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL))
\r
9823 #define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL))
\r
9824 #define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL))
\r
9825 #define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL))
\r
9826 #define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL))
\r
9827 #define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL))
\r
9828 #define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL))
\r
9829 #define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL))
\r
9830 #define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL))
\r
9831 #define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL))
\r
9832 #define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL))
\r
9833 #define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL))
\r
9834 #define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL))
\r
9835 #define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL))
\r
9836 #define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL))
\r
9837 #define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL))
\r
9838 #define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL))
\r
9839 #define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL))
\r
9840 #define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL))
\r
9841 #define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL))
\r
9842 #define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL))
\r
9843 #define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL))
\r
9844 #define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL))
\r
9845 #define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL))
\r
9846 #define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL))
\r
9847 #define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL))
\r
9848 #define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL))
\r
9849 #define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL))
\r
9850 #define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL))
\r
9851 #define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL))
\r
9852 #define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL))
\r
9853 #define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL))
\r
9854 #define bFM3_ADC0_ADCT_CT3 *((volatile unsigned int*)(0x424E068CUL))
\r
9855 #define bFM3_ADC0_ADCT_CT4 *((volatile unsigned int*)(0x424E0690UL))
\r
9856 #define bFM3_ADC0_ADCT_CT5 *((volatile unsigned int*)(0x424E0694UL))
\r
9857 #define bFM3_ADC0_ADCT_CT6 *((volatile unsigned int*)(0x424E0698UL))
\r
9858 #define bFM3_ADC0_ADCT_CT7 *((volatile unsigned int*)(0x424E069CUL))
\r
9859 #define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL))
\r
9860 #define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL))
\r
9861 #define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL))
\r
9862 #define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL))
\r
9863 #define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL))
\r
9864 #define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL))
\r
9865 #define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL))
\r
9866 #define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL))
\r
9867 #define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL))
\r
9868 #define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL))
\r
9869 #define bFM3_ADC0_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E0790UL))
\r
9870 #define bFM3_ADC0_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E0794UL))
\r
9872 /* 12-bit ADC unit 1 registers */
\r
9873 #define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL))
\r
9874 #define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL))
\r
9875 #define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL))
\r
9876 #define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL))
\r
9877 #define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL))
\r
9878 #define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL))
\r
9879 #define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL))
\r
9880 #define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL))
\r
9881 #define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL))
\r
9882 #define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL))
\r
9883 #define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL))
\r
9884 #define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL))
\r
9885 #define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL))
\r
9886 #define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL))
\r
9887 #define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL))
\r
9888 #define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL))
\r
9889 #define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL))
\r
9890 #define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL))
\r
9891 #define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL))
\r
9892 #define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL))
\r
9893 #define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL))
\r
9894 #define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL))
\r
9895 #define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL))
\r
9896 #define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL))
\r
9897 #define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL))
\r
9898 #define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL))
\r
9899 #define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL))
\r
9900 #define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL))
\r
9901 #define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL))
\r
9902 #define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL))
\r
9903 #define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL))
\r
9904 #define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL))
\r
9905 #define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL))
\r
9906 #define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL))
\r
9907 #define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL))
\r
9908 #define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL))
\r
9909 #define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL))
\r
9910 #define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL))
\r
9911 #define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL))
\r
9912 #define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL))
\r
9913 #define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL))
\r
9914 #define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL))
\r
9915 #define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL))
\r
9916 #define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL))
\r
9917 #define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL))
\r
9918 #define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL))
\r
9919 #define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL))
\r
9920 #define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL))
\r
9921 #define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL))
\r
9922 #define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL))
\r
9923 #define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL))
\r
9924 #define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL))
\r
9925 #define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL))
\r
9926 #define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL))
\r
9927 #define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL))
\r
9928 #define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL))
\r
9929 #define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL))
\r
9930 #define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL))
\r
9931 #define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL))
\r
9932 #define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL))
\r
9933 #define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL))
\r
9934 #define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL))
\r
9935 #define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL))
\r
9936 #define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL))
\r
9937 #define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL))
\r
9938 #define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL))
\r
9939 #define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL))
\r
9940 #define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL))
\r
9941 #define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL))
\r
9942 #define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL))
\r
9943 #define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL))
\r
9944 #define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL))
\r
9945 #define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL))
\r
9946 #define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL))
\r
9947 #define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL))
\r
9948 #define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL))
\r
9949 #define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL))
\r
9950 #define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL))
\r
9951 #define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL))
\r
9952 #define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL))
\r
9953 #define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL))
\r
9954 #define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL))
\r
9955 #define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL))
\r
9956 #define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL))
\r
9957 #define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL))
\r
9958 #define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL))
\r
9959 #define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL))
\r
9960 #define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL))
\r
9961 #define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL))
\r
9962 #define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL))
\r
9963 #define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL))
\r
9964 #define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL))
\r
9965 #define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL))
\r
9966 #define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL))
\r
9967 #define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL))
\r
9968 #define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL))
\r
9969 #define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL))
\r
9970 #define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL))
\r
9971 #define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL))
\r
9972 #define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL))
\r
9973 #define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL))
\r
9974 #define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL))
\r
9975 #define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL))
\r
9976 #define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL))
\r
9977 #define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL))
\r
9978 #define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL))
\r
9979 #define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL))
\r
9980 #define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL))
\r
9981 #define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL))
\r
9982 #define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL))
\r
9983 #define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL))
\r
9984 #define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL))
\r
9985 #define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL))
\r
9986 #define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL))
\r
9987 #define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL))
\r
9988 #define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL))
\r
9989 #define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL))
\r
9990 #define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL))
\r
9991 #define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL))
\r
9992 #define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL))
\r
9993 #define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL))
\r
9994 #define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL))
\r
9995 #define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL))
\r
9996 #define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL))
\r
9997 #define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL))
\r
9998 #define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL))
\r
9999 #define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL))
\r
10000 #define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL))
\r
10001 #define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL))
\r
10002 #define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL))
\r
10003 #define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL))
\r
10004 #define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL))
\r
10005 #define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL))
\r
10006 #define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL))
\r
10007 #define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL))
\r
10008 #define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL))
\r
10009 #define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL))
\r
10010 #define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL))
\r
10011 #define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL))
\r
10012 #define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL))
\r
10013 #define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL))
\r
10014 #define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL))
\r
10015 #define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL))
\r
10016 #define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL))
\r
10017 #define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL))
\r
10018 #define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL))
\r
10019 #define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL))
\r
10020 #define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL))
\r
10021 #define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL))
\r
10022 #define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL))
\r
10023 #define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL))
\r
10024 #define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL))
\r
10025 #define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL))
\r
10026 #define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL))
\r
10027 #define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL))
\r
10028 #define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL))
\r
10029 #define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL))
\r
10030 #define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL))
\r
10031 #define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL))
\r
10032 #define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL))
\r
10033 #define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL))
\r
10034 #define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL))
\r
10035 #define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL))
\r
10036 #define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL))
\r
10037 #define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL))
\r
10038 #define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL))
\r
10039 #define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL))
\r
10040 #define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL))
\r
10041 #define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL))
\r
10042 #define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL))
\r
10043 #define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL))
\r
10044 #define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL))
\r
10045 #define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL))
\r
10046 #define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL))
\r
10047 #define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL))
\r
10048 #define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL))
\r
10049 #define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL))
\r
10050 #define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL))
\r
10051 #define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL))
\r
10052 #define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL))
\r
10053 #define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL))
\r
10054 #define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL))
\r
10055 #define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL))
\r
10056 #define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL))
\r
10057 #define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL))
\r
10058 #define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL))
\r
10059 #define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL))
\r
10060 #define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL))
\r
10061 #define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL))
\r
10062 #define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL))
\r
10063 #define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL))
\r
10064 #define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL))
\r
10065 #define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL))
\r
10066 #define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL))
\r
10067 #define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL))
\r
10068 #define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL))
\r
10069 #define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL))
\r
10070 #define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL))
\r
10071 #define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL))
\r
10072 #define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL))
\r
10073 #define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL))
\r
10074 #define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL))
\r
10075 #define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL))
\r
10076 #define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL))
\r
10077 #define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL))
\r
10078 #define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL))
\r
10079 #define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL))
\r
10080 #define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL))
\r
10081 #define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL))
\r
10082 #define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL))
\r
10083 #define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL))
\r
10084 #define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL))
\r
10085 #define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL))
\r
10086 #define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL))
\r
10087 #define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL))
\r
10088 #define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL))
\r
10089 #define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL))
\r
10090 #define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL))
\r
10091 #define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL))
\r
10092 #define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL))
\r
10093 #define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL))
\r
10094 #define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL))
\r
10095 #define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL))
\r
10096 #define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL))
\r
10097 #define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL))
\r
10098 #define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL))
\r
10099 #define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL))
\r
10100 #define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL))
\r
10101 #define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL))
\r
10102 #define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL))
\r
10103 #define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL))
\r
10104 #define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL))
\r
10105 #define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL))
\r
10106 #define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL))
\r
10107 #define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL))
\r
10108 #define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL))
\r
10109 #define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL))
\r
10110 #define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL))
\r
10111 #define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL))
\r
10112 #define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL))
\r
10113 #define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL))
\r
10114 #define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL))
\r
10115 #define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL))
\r
10116 #define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL))
\r
10117 #define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL))
\r
10118 #define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL))
\r
10119 #define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL))
\r
10120 #define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL))
\r
10121 #define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL))
\r
10122 #define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL))
\r
10123 #define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL))
\r
10124 #define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL))
\r
10125 #define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL))
\r
10126 #define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL))
\r
10127 #define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL))
\r
10128 #define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL))
\r
10129 #define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL))
\r
10130 #define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL))
\r
10131 #define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL))
\r
10132 #define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL))
\r
10133 #define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL))
\r
10134 #define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL))
\r
10135 #define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL))
\r
10136 #define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL))
\r
10137 #define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL))
\r
10138 #define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL))
\r
10139 #define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL))
\r
10140 #define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL))
\r
10141 #define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL))
\r
10142 #define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL))
\r
10143 #define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL))
\r
10144 #define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL))
\r
10145 #define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL))
\r
10146 #define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL))
\r
10147 #define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL))
\r
10148 #define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL))
\r
10149 #define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL))
\r
10150 #define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL))
\r
10151 #define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL))
\r
10152 #define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL))
\r
10153 #define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL))
\r
10154 #define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL))
\r
10155 #define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL))
\r
10156 #define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL))
\r
10157 #define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL))
\r
10158 #define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL))
\r
10159 #define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL))
\r
10160 #define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL))
\r
10161 #define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL))
\r
10162 #define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL))
\r
10163 #define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL))
\r
10164 #define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL))
\r
10165 #define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL))
\r
10166 #define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL))
\r
10167 #define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL))
\r
10168 #define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL))
\r
10169 #define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL))
\r
10170 #define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL))
\r
10171 #define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL))
\r
10172 #define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL))
\r
10173 #define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL))
\r
10174 #define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL))
\r
10175 #define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL))
\r
10176 #define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL))
\r
10177 #define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL))
\r
10178 #define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL))
\r
10179 #define bFM3_ADC1_ADCT_CT3 *((volatile unsigned int*)(0x424E268CUL))
\r
10180 #define bFM3_ADC1_ADCT_CT4 *((volatile unsigned int*)(0x424E2690UL))
\r
10181 #define bFM3_ADC1_ADCT_CT5 *((volatile unsigned int*)(0x424E2694UL))
\r
10182 #define bFM3_ADC1_ADCT_CT6 *((volatile unsigned int*)(0x424E2698UL))
\r
10183 #define bFM3_ADC1_ADCT_CT7 *((volatile unsigned int*)(0x424E269CUL))
\r
10184 #define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL))
\r
10185 #define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL))
\r
10186 #define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL))
\r
10187 #define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL))
\r
10188 #define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL))
\r
10189 #define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL))
\r
10190 #define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL))
\r
10191 #define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL))
\r
10192 #define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL))
\r
10193 #define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL))
\r
10194 #define bFM3_ADC1_ADCEN_CYCLSL0 *((volatile unsigned int*)(0x424E2790UL))
\r
10195 #define bFM3_ADC1_ADCEN_CYCLSL1 *((volatile unsigned int*)(0x424E2794UL))
\r
10197 /* CR trimming registers */
\r
10198 #define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL))
\r
10199 #define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL))
\r
10200 #define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL))
\r
10201 #define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL))
\r
10202 #define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL))
\r
10203 #define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL))
\r
10204 #define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL))
\r
10205 #define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL))
\r
10206 #define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL))
\r
10207 #define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL))
\r
10209 /* External interrupt registers */
\r
10210 #define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL))
\r
10211 #define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL))
\r
10212 #define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL))
\r
10213 #define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL))
\r
10214 #define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL))
\r
10215 #define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL))
\r
10216 #define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL))
\r
10217 #define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL))
\r
10218 #define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL))
\r
10219 #define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL))
\r
10220 #define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL))
\r
10221 #define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL))
\r
10222 #define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL))
\r
10223 #define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL))
\r
10224 #define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL))
\r
10225 #define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL))
\r
10226 #define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL))
\r
10227 #define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL))
\r
10228 #define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL))
\r
10229 #define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL))
\r
10230 #define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL))
\r
10231 #define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL))
\r
10232 #define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL))
\r
10233 #define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL))
\r
10234 #define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL))
\r
10235 #define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL))
\r
10236 #define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL))
\r
10237 #define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL))
\r
10238 #define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL))
\r
10239 #define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL))
\r
10240 #define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL))
\r
10241 #define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL))
\r
10242 #define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL))
\r
10243 #define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL))
\r
10244 #define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL))
\r
10245 #define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL))
\r
10246 #define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL))
\r
10247 #define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL))
\r
10248 #define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL))
\r
10249 #define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL))
\r
10250 #define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL))
\r
10251 #define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL))
\r
10252 #define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL))
\r
10253 #define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL))
\r
10254 #define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL))
\r
10255 #define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL))
\r
10256 #define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL))
\r
10257 #define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL))
\r
10258 #define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL))
\r
10259 #define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL))
\r
10260 #define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL))
\r
10261 #define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL))
\r
10262 #define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL))
\r
10263 #define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL))
\r
10264 #define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL))
\r
10265 #define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL))
\r
10266 #define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL))
\r
10268 /* Interrupt request read registers */
\r
10269 #define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL))
\r
10270 #define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL))
\r
10271 #define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL))
\r
10272 #define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL))
\r
10273 #define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL))
\r
10274 #define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL))
\r
10275 #define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL))
\r
10276 #define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL))
\r
10277 #define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL))
\r
10278 #define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL))
\r
10279 #define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL))
\r
10280 #define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL))
\r
10281 #define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL))
\r
10282 #define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL))
\r
10283 #define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL))
\r
10284 #define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL))
\r
10285 #define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL))
\r
10286 #define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL))
\r
10287 #define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL))
\r
10288 #define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL))
\r
10289 #define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL))
\r
10290 #define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL))
\r
10291 #define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL))
\r
10292 #define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL))
\r
10293 #define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL))
\r
10294 #define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL))
\r
10295 #define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL))
\r
10296 #define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL))
\r
10297 #define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL))
\r
10298 #define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL))
\r
10299 #define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL))
\r
10300 #define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL))
\r
10301 #define bFM3_INTREQ_ODDPKS_ODDPKS0 *((volatile unsigned int*)(0x42620160UL))
\r
10302 #define bFM3_INTREQ_ODDPKS_ODDPKS1 *((volatile unsigned int*)(0x42620164UL))
\r
10303 #define bFM3_INTREQ_ODDPKS_ODDPKS2 *((volatile unsigned int*)(0x42620168UL))
\r
10304 #define bFM3_INTREQ_ODDPKS_ODDPKS3 *((volatile unsigned int*)(0x4262016CUL))
\r
10305 #define bFM3_INTREQ_ODDPKS_ODDPKS4 *((volatile unsigned int*)(0x42620170UL))
\r
10306 #define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL))
\r
10307 #define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL))
\r
10308 #define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL))
\r
10309 #define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL))
\r
10310 #define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL))
\r
10311 #define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL))
\r
10312 #define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL))
\r
10313 #define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL))
\r
10314 #define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL))
\r
10315 #define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL))
\r
10316 #define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL))
\r
10317 #define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL))
\r
10318 #define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL))
\r
10319 #define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL))
\r
10320 #define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL))
\r
10321 #define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL))
\r
10322 #define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL))
\r
10323 #define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL))
\r
10324 #define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL))
\r
10325 #define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL))
\r
10326 #define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL))
\r
10327 #define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL))
\r
10328 #define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL))
\r
10329 #define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL))
\r
10330 #define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL))
\r
10331 #define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL))
\r
10332 #define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL))
\r
10333 #define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL))
\r
10334 #define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL))
\r
10335 #define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL))
\r
10336 #define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL))
\r
10337 #define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL))
\r
10338 #define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL))
\r
10339 #define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL))
\r
10340 #define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL))
\r
10341 #define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL))
\r
10342 #define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL))
\r
10343 #define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL))
\r
10344 #define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL))
\r
10345 #define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL))
\r
10346 #define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL))
\r
10347 #define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL))
\r
10348 #define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL))
\r
10349 #define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL))
\r
10350 #define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL))
\r
10351 #define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL))
\r
10352 #define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL))
\r
10353 #define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL))
\r
10354 #define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL))
\r
10355 #define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL))
\r
10356 #define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL))
\r
10357 #define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL))
\r
10358 #define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL))
\r
10359 #define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL))
\r
10360 #define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL))
\r
10361 #define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL))
\r
10362 #define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL))
\r
10363 #define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL))
\r
10364 #define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL))
\r
10365 #define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL))
\r
10366 #define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL))
\r
10367 #define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL))
\r
10368 #define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL))
\r
10369 #define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL))
\r
10370 #define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL))
\r
10371 #define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL))
\r
10372 #define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL))
\r
10373 #define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL))
\r
10374 #define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL))
\r
10375 #define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL))
\r
10376 #define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL))
\r
10377 #define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL))
\r
10378 #define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL))
\r
10379 #define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL))
\r
10380 #define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL))
\r
10381 #define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL))
\r
10382 #define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL))
\r
10383 #define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL))
\r
10384 #define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL))
\r
10385 #define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL))
\r
10386 #define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL))
\r
10387 #define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL))
\r
10388 #define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL))
\r
10389 #define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL))
\r
10390 #define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL))
\r
10391 #define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL))
\r
10392 #define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL))
\r
10393 #define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL))
\r
10394 #define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL))
\r
10395 #define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL))
\r
10396 #define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL))
\r
10397 #define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL))
\r
10398 #define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL))
\r
10399 #define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL))
\r
10400 #define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL))
\r
10401 #define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL))
\r
10402 #define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL))
\r
10403 #define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL))
\r
10404 #define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL))
\r
10405 #define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL))
\r
10406 #define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL))
\r
10407 #define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL))
\r
10408 #define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL))
\r
10409 #define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL))
\r
10410 #define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL))
\r
10411 #define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL))
\r
10412 #define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL))
\r
10413 #define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL))
\r
10414 #define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL))
\r
10415 #define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL))
\r
10416 #define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL))
\r
10417 #define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL))
\r
10418 #define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL))
\r
10419 #define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL))
\r
10420 #define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL))
\r
10421 #define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL))
\r
10422 #define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL))
\r
10423 #define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL))
\r
10424 #define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL))
\r
10425 #define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL))
\r
10426 #define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL))
\r
10427 #define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL))
\r
10428 #define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL))
\r
10429 #define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL))
\r
10430 #define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL))
\r
10431 #define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL))
\r
10432 #define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL))
\r
10433 #define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL))
\r
10434 #define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL))
\r
10435 #define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL))
\r
10436 #define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL))
\r
10437 #define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL))
\r
10438 #define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL))
\r
10439 #define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL))
\r
10440 #define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL))
\r
10441 #define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL))
\r
10442 #define bFM3_INTREQ_IRQ35MON_USB0INT5 *((volatile unsigned int*)(0x42621414UL))
\r
10443 #define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL))
\r
10444 #define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL))
\r
10445 #define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL))
\r
10446 #define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL))
\r
10447 #define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL))
\r
10448 #define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL))
\r
10449 #define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL))
\r
10450 #define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL))
\r
10452 /* General purpose I/O registers */
\r
10453 #define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL))
\r
10454 #define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL))
\r
10455 #define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL))
\r
10456 #define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL))
\r
10457 #define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL))
\r
10458 #define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL))
\r
10459 #define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL))
\r
10460 #define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL))
\r
10461 #define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL))
\r
10462 #define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL))
\r
10463 #define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL))
\r
10464 #define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL))
\r
10465 #define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL))
\r
10466 #define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL))
\r
10467 #define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL))
\r
10468 #define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL))
\r
10469 #define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL))
\r
10470 #define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL))
\r
10471 #define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL))
\r
10472 #define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL))
\r
10473 #define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL))
\r
10474 #define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL))
\r
10475 #define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL))
\r
10476 #define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL))
\r
10477 #define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL))
\r
10478 #define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL))
\r
10479 #define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL))
\r
10480 #define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL))
\r
10481 #define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL))
\r
10482 #define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL))
\r
10483 #define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL))
\r
10484 #define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL))
\r
10485 #define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL))
\r
10486 #define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL))
\r
10487 #define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL))
\r
10488 #define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL))
\r
10489 #define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL))
\r
10490 #define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL))
\r
10491 #define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL))
\r
10492 #define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL))
\r
10493 #define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL))
\r
10494 #define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL))
\r
10495 #define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL))
\r
10496 #define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL))
\r
10497 #define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL))
\r
10498 #define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL))
\r
10499 #define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL))
\r
10500 #define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL))
\r
10501 #define bFM3_GPIO_PFRE_P0 *((volatile unsigned int*)(0x42660700UL))
\r
10502 #define bFM3_GPIO_PFRE_P2 *((volatile unsigned int*)(0x42660708UL))
\r
10503 #define bFM3_GPIO_PFRE_P3 *((volatile unsigned int*)(0x4266070CUL))
\r
10504 #define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL))
\r
10505 #define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL))
\r
10506 #define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL))
\r
10507 #define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL))
\r
10508 #define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL))
\r
10509 #define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL))
\r
10510 #define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL))
\r
10511 #define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL))
\r
10512 #define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL))
\r
10513 #define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL))
\r
10514 #define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL))
\r
10515 #define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL))
\r
10516 #define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL))
\r
10517 #define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL))
\r
10518 #define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL))
\r
10519 #define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL))
\r
10520 #define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL))
\r
10521 #define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL))
\r
10522 #define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL))
\r
10523 #define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL))
\r
10524 #define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL))
\r
10525 #define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL))
\r
10526 #define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL))
\r
10527 #define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL))
\r
10528 #define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL))
\r
10529 #define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL))
\r
10530 #define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL))
\r
10531 #define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL))
\r
10532 #define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL))
\r
10533 #define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL))
\r
10534 #define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL))
\r
10535 #define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL))
\r
10536 #define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL))
\r
10537 #define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL))
\r
10538 #define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL))
\r
10539 #define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL))
\r
10540 #define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL))
\r
10541 #define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL))
\r
10542 #define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL))
\r
10543 #define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL))
\r
10544 #define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL))
\r
10545 #define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL))
\r
10546 #define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL))
\r
10547 #define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL))
\r
10548 #define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL))
\r
10549 #define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL))
\r
10550 #define bFM3_GPIO_PCRE_P0 *((volatile unsigned int*)(0x42662700UL))
\r
10551 #define bFM3_GPIO_PCRE_P2 *((volatile unsigned int*)(0x42662708UL))
\r
10552 #define bFM3_GPIO_PCRE_P3 *((volatile unsigned int*)(0x4266270CUL))
\r
10553 #define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL))
\r
10554 #define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL))
\r
10555 #define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL))
\r
10556 #define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL))
\r
10557 #define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL))
\r
10558 #define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL))
\r
10559 #define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL))
\r
10560 #define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL))
\r
10561 #define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL))
\r
10562 #define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL))
\r
10563 #define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL))
\r
10564 #define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL))
\r
10565 #define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL))
\r
10566 #define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL))
\r
10567 #define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL))
\r
10568 #define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL))
\r
10569 #define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL))
\r
10570 #define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL))
\r
10571 #define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL))
\r
10572 #define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL))
\r
10573 #define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL))
\r
10574 #define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL))
\r
10575 #define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL))
\r
10576 #define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL))
\r
10577 #define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL))
\r
10578 #define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL))
\r
10579 #define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL))
\r
10580 #define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL))
\r
10581 #define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL))
\r
10582 #define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL))
\r
10583 #define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL))
\r
10584 #define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL))
\r
10585 #define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL))
\r
10586 #define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL))
\r
10587 #define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL))
\r
10588 #define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL))
\r
10589 #define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL))
\r
10590 #define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL))
\r
10591 #define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL))
\r
10592 #define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL))
\r
10593 #define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL))
\r
10594 #define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL))
\r
10595 #define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL))
\r
10596 #define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL))
\r
10597 #define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL))
\r
10598 #define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL))
\r
10599 #define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL))
\r
10600 #define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL))
\r
10601 #define bFM3_GPIO_DDRE_P0 *((volatile unsigned int*)(0x42664700UL))
\r
10602 #define bFM3_GPIO_DDRE_P2 *((volatile unsigned int*)(0x42664708UL))
\r
10603 #define bFM3_GPIO_DDRE_P3 *((volatile unsigned int*)(0x4266470CUL))
\r
10604 #define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL))
\r
10605 #define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL))
\r
10606 #define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL))
\r
10607 #define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL))
\r
10608 #define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL))
\r
10609 #define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL))
\r
10610 #define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL))
\r
10611 #define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL))
\r
10612 #define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL))
\r
10613 #define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL))
\r
10614 #define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL))
\r
10615 #define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL))
\r
10616 #define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL))
\r
10617 #define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL))
\r
10618 #define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL))
\r
10619 #define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL))
\r
10620 #define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL))
\r
10621 #define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL))
\r
10622 #define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL))
\r
10623 #define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL))
\r
10624 #define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL))
\r
10625 #define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL))
\r
10626 #define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL))
\r
10627 #define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL))
\r
10628 #define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL))
\r
10629 #define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL))
\r
10630 #define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL))
\r
10631 #define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL))
\r
10632 #define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL))
\r
10633 #define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL))
\r
10634 #define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL))
\r
10635 #define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL))
\r
10636 #define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL))
\r
10637 #define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL))
\r
10638 #define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL))
\r
10639 #define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL))
\r
10640 #define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL))
\r
10641 #define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL))
\r
10642 #define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL))
\r
10643 #define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL))
\r
10644 #define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL))
\r
10645 #define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL))
\r
10646 #define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL))
\r
10647 #define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL))
\r
10648 #define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL))
\r
10649 #define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL))
\r
10650 #define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL))
\r
10651 #define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL))
\r
10652 #define bFM3_GPIO_PDIRE_P0 *((volatile unsigned int*)(0x42666700UL))
\r
10653 #define bFM3_GPIO_PDIRE_P2 *((volatile unsigned int*)(0x42666708UL))
\r
10654 #define bFM3_GPIO_PDIRE_P3 *((volatile unsigned int*)(0x4266670CUL))
\r
10655 #define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL))
\r
10656 #define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL))
\r
10657 #define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL))
\r
10658 #define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL))
\r
10659 #define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL))
\r
10660 #define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL))
\r
10661 #define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL))
\r
10662 #define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL))
\r
10663 #define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL))
\r
10664 #define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL))
\r
10665 #define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL))
\r
10666 #define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL))
\r
10667 #define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL))
\r
10668 #define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL))
\r
10669 #define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL))
\r
10670 #define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL))
\r
10671 #define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL))
\r
10672 #define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL))
\r
10673 #define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL))
\r
10674 #define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL))
\r
10675 #define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL))
\r
10676 #define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL))
\r
10677 #define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL))
\r
10678 #define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL))
\r
10679 #define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL))
\r
10680 #define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL))
\r
10681 #define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL))
\r
10682 #define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL))
\r
10683 #define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL))
\r
10684 #define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL))
\r
10685 #define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL))
\r
10686 #define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL))
\r
10687 #define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL))
\r
10688 #define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL))
\r
10689 #define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL))
\r
10690 #define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL))
\r
10691 #define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL))
\r
10692 #define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL))
\r
10693 #define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL))
\r
10694 #define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL))
\r
10695 #define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL))
\r
10696 #define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL))
\r
10697 #define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL))
\r
10698 #define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL))
\r
10699 #define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL))
\r
10700 #define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL))
\r
10701 #define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL))
\r
10702 #define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL))
\r
10703 #define bFM3_GPIO_PDORE_P0 *((volatile unsigned int*)(0x42668700UL))
\r
10704 #define bFM3_GPIO_PDORE_P2 *((volatile unsigned int*)(0x42668708UL))
\r
10705 #define bFM3_GPIO_PDORE_P3 *((volatile unsigned int*)(0x4266870CUL))
\r
10706 #define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL))
\r
10707 #define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL))
\r
10708 #define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL))
\r
10709 #define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL))
\r
10710 #define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL))
\r
10711 #define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL))
\r
10712 #define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL))
\r
10713 #define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL))
\r
10714 #define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL))
\r
10715 #define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL))
\r
10716 #define bFM3_GPIO_SPSR_MAINXC *((volatile unsigned int*)(0x4266B008UL))
\r
10717 #define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL))
\r
10718 #define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL))
\r
10719 #define bFM3_GPIO_EPFR00_CROUTE0 *((volatile unsigned int*)(0x4266C004UL))
\r
10720 #define bFM3_GPIO_EPFR00_CROUTE1 *((volatile unsigned int*)(0x4266C008UL))
\r
10721 #define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL))
\r
10722 #define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL))
\r
10723 #define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL))
\r
10724 #define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL))
\r
10725 #define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL))
\r
10726 #define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL))
\r
10727 #define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL))
\r
10728 #define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL))
\r
10729 #define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL))
\r
10730 #define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL))
\r
10731 #define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL))
\r
10732 #define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL))
\r
10733 #define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL))
\r
10734 #define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL))
\r
10735 #define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL))
\r
10736 #define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL))
\r
10737 #define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL))
\r
10738 #define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL))
\r
10739 #define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL))
\r
10740 #define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL))
\r
10741 #define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL))
\r
10742 #define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL))
\r
10743 #define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL))
\r
10744 #define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL))
\r
10745 #define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL))
\r
10746 #define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL))
\r
10747 #define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL))
\r
10748 #define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL))
\r
10749 #define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL))
\r
10750 #define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL))
\r
10751 #define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL))
\r
10752 #define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL))
\r
10753 #define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL))
\r
10754 #define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL))
\r
10755 #define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL))
\r
10756 #define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL))
\r
10757 #define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL))
\r
10758 #define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL))
\r
10759 #define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL))
\r
10760 #define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL))
\r
10761 #define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL))
\r
10762 #define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL))
\r
10763 #define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL))
\r
10764 #define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL))
\r
10765 #define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL))
\r
10766 #define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL))
\r
10767 #define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL))
\r
10768 #define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL))
\r
10769 #define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL))
\r
10770 #define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL))
\r
10771 #define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL))
\r
10772 #define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL))
\r
10773 #define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL))
\r
10774 #define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL))
\r
10775 #define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL))
\r
10776 #define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL))
\r
10777 #define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL))
\r
10778 #define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL))
\r
10779 #define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL))
\r
10780 #define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL))
\r
10781 #define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL))
\r
10782 #define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL))
\r
10783 #define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL))
\r
10784 #define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL))
\r
10785 #define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL))
\r
10786 #define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL))
\r
10787 #define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL))
\r
10788 #define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL))
\r
10789 #define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL))
\r
10790 #define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL))
\r
10791 #define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL))
\r
10792 #define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL))
\r
10793 #define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL))
\r
10794 #define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL))
\r
10795 #define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL))
\r
10796 #define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL))
\r
10797 #define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL))
\r
10798 #define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL))
\r
10799 #define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL))
\r
10800 #define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL))
\r
10801 #define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL))
\r
10802 #define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL))
\r
10803 #define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL))
\r
10804 #define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL))
\r
10805 #define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL))
\r
10806 #define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL))
\r
10807 #define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL))
\r
10808 #define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL))
\r
10809 #define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL))
\r
10810 #define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL))
\r
10811 #define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL))
\r
10812 #define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL))
\r
10813 #define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL))
\r
10814 #define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL))
\r
10815 #define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL))
\r
10816 #define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL))
\r
10817 #define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL))
\r
10818 #define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL))
\r
10819 #define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL))
\r
10820 #define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL))
\r
10821 #define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL))
\r
10822 #define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL))
\r
10823 #define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL))
\r
10824 #define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL))
\r
10825 #define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL))
\r
10826 #define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL))
\r
10827 #define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL))
\r
10828 #define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL))
\r
10829 #define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL))
\r
10830 #define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL))
\r
10831 #define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL))
\r
10832 #define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL))
\r
10833 #define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL))
\r
10834 #define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL))
\r
10835 #define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL))
\r
10836 #define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL))
\r
10837 #define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL))
\r
10838 #define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL))
\r
10839 #define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL))
\r
10840 #define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL))
\r
10841 #define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL))
\r
10842 #define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL))
\r
10843 #define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL))
\r
10844 #define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL))
\r
10845 #define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL))
\r
10846 #define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL))
\r
10847 #define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL))
\r
10848 #define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL))
\r
10849 #define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL))
\r
10850 #define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL))
\r
10851 #define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL))
\r
10852 #define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL))
\r
10853 #define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL))
\r
10854 #define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL))
\r
10855 #define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL))
\r
10856 #define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL))
\r
10857 #define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL))
\r
10858 #define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL))
\r
10859 #define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL))
\r
10860 #define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL))
\r
10861 #define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL))
\r
10862 #define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL))
\r
10863 #define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL))
\r
10864 #define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL))
\r
10865 #define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL))
\r
10866 #define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL))
\r
10867 #define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL))
\r
10868 #define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL))
\r
10869 #define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL))
\r
10870 #define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL))
\r
10871 #define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL))
\r
10872 #define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL))
\r
10873 #define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL))
\r
10874 #define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL))
\r
10875 #define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL))
\r
10876 #define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL))
\r
10878 /* Low voltage detection registers */
\r
10879 #define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL))
\r
10880 #define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL))
\r
10881 #define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL))
\r
10882 #define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL))
\r
10883 #define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL))
\r
10884 #define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL))
\r
10885 #define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL))
\r
10886 #define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL))
\r
10888 /* USB clock registers */
\r
10889 #define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL))
\r
10890 #define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL))
\r
10891 #define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL))
\r
10892 #define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL))
\r
10893 #define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL))
\r
10894 #define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL))
\r
10895 #define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL))
\r
10896 #define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL))
\r
10897 #define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL))
\r
10898 #define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL))
\r
10899 #define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL))
\r
10900 #define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL))
\r
10901 #define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL))
\r
10902 #define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL))
\r
10903 #define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL))
\r
10904 #define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL))
\r
10905 #define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL))
\r
10906 #define bFM3_USBCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL))
\r
10907 #define bFM3_USBCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL))
\r
10908 #define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL))
\r
10909 #define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL))
\r
10910 #define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL))
\r
10911 #define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL))
\r
10912 #define bFM3_USBCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL))
\r
10913 #define bFM3_USBCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL))
\r
10914 #define bFM3_USBCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL))
\r
10915 #define bFM3_USBCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL))
\r
10916 #define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL))
\r
10918 /* UART asynchronous channel 0 registers */
\r
10919 #define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL))
\r
10920 #define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL))
\r
10921 #define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL))
\r
10922 #define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL))
\r
10923 #define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL))
\r
10924 #define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL))
\r
10925 #define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL))
\r
10926 #define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL))
\r
10927 #define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL))
\r
10928 #define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL))
\r
10929 #define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL))
\r
10930 #define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL))
\r
10931 #define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL))
\r
10932 #define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL))
\r
10933 #define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL))
\r
10934 #define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL))
\r
10935 #define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL))
\r
10936 #define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL))
\r
10937 #define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL))
\r
10938 #define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL))
\r
10939 #define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL))
\r
10940 #define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL))
\r
10941 #define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL))
\r
10942 #define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL))
\r
10943 #define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL))
\r
10944 #define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL))
\r
10945 #define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL))
\r
10946 #define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL))
\r
10947 #define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL))
\r
10948 #define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL))
\r
10949 #define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL))
\r
10950 #define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL))
\r
10952 /* UART synchronous channel 0 registers */
\r
10953 #define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL))
\r
10954 #define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL))
\r
10955 #define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL))
\r
10956 #define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL))
\r
10957 #define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL))
\r
10958 #define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL))
\r
10959 #define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL))
\r
10960 #define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL))
\r
10961 #define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL))
\r
10962 #define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL))
\r
10963 #define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL))
\r
10964 #define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL))
\r
10965 #define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL))
\r
10966 #define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL))
\r
10967 #define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL))
\r
10968 #define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL))
\r
10969 #define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL))
\r
10970 #define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL))
\r
10971 #define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL))
\r
10972 #define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL))
\r
10973 #define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL))
\r
10974 #define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL))
\r
10975 #define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL))
\r
10976 #define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL))
\r
10977 #define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL))
\r
10978 #define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL))
\r
10979 #define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL))
\r
10981 /* UART LIN channel 0 registers */
\r
10982 #define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL))
\r
10983 #define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL))
\r
10984 #define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL))
\r
10985 #define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL))
\r
10986 #define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL))
\r
10987 #define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL))
\r
10988 #define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL))
\r
10989 #define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL))
\r
10990 #define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL))
\r
10991 #define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL))
\r
10992 #define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL))
\r
10993 #define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL))
\r
10994 #define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL))
\r
10995 #define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL))
\r
10996 #define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL))
\r
10997 #define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL))
\r
10998 #define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL))
\r
10999 #define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL))
\r
11000 #define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL))
\r
11001 #define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL))
\r
11002 #define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL))
\r
11003 #define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL))
\r
11004 #define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL))
\r
11005 #define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL))
\r
11006 #define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL))
\r
11007 #define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL))
\r
11008 #define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL))
\r
11009 #define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL))
\r
11010 #define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL))
\r
11012 /* I2C channel 0 registers */
\r
11013 #define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL))
\r
11014 #define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL))
\r
11015 #define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL))
\r
11016 #define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL))
\r
11017 #define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL))
\r
11018 #define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL))
\r
11019 #define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL))
\r
11020 #define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL))
\r
11021 #define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL))
\r
11022 #define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL))
\r
11023 #define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL))
\r
11024 #define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL))
\r
11025 #define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL))
\r
11026 #define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL))
\r
11027 #define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL))
\r
11028 #define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL))
\r
11029 #define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL))
\r
11030 #define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL))
\r
11031 #define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL))
\r
11032 #define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL))
\r
11033 #define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL))
\r
11034 #define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL))
\r
11035 #define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL))
\r
11036 #define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL))
\r
11037 #define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL))
\r
11038 #define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL))
\r
11039 #define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL))
\r
11040 #define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL))
\r
11041 #define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL))
\r
11042 #define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL))
\r
11043 #define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL))
\r
11044 #define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL))
\r
11045 #define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL))
\r
11046 #define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL))
\r
11047 #define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL))
\r
11048 #define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL))
\r
11049 #define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL))
\r
11050 #define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL))
\r
11051 #define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL))
\r
11052 #define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL))
\r
11053 #define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL))
\r
11054 #define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL))
\r
11055 #define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL))
\r
11056 #define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL))
\r
11057 #define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL))
\r
11058 #define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL))
\r
11059 #define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL))
\r
11060 #define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL))
\r
11061 #define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL))
\r
11063 /* UART asynchronous channel 1 registers */
\r
11064 #define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL))
\r
11065 #define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL))
\r
11066 #define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL))
\r
11067 #define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL))
\r
11068 #define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL))
\r
11069 #define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL))
\r
11070 #define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL))
\r
11071 #define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL))
\r
11072 #define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL))
\r
11073 #define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL))
\r
11074 #define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL))
\r
11075 #define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL))
\r
11076 #define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL))
\r
11077 #define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL))
\r
11078 #define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL))
\r
11079 #define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL))
\r
11080 #define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL))
\r
11081 #define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL))
\r
11082 #define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL))
\r
11083 #define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL))
\r
11084 #define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL))
\r
11085 #define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL))
\r
11086 #define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL))
\r
11087 #define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL))
\r
11088 #define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL))
\r
11089 #define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL))
\r
11090 #define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL))
\r
11091 #define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL))
\r
11092 #define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL))
\r
11093 #define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL))
\r
11094 #define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL))
\r
11095 #define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL))
\r
11097 /* UART synchronous channel 1 registers */
\r
11098 #define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL))
\r
11099 #define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL))
\r
11100 #define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL))
\r
11101 #define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL))
\r
11102 #define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL))
\r
11103 #define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL))
\r
11104 #define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL))
\r
11105 #define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL))
\r
11106 #define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL))
\r
11107 #define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL))
\r
11108 #define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL))
\r
11109 #define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL))
\r
11110 #define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL))
\r
11111 #define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL))
\r
11112 #define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL))
\r
11113 #define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL))
\r
11114 #define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL))
\r
11115 #define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL))
\r
11116 #define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL))
\r
11117 #define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL))
\r
11118 #define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL))
\r
11119 #define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL))
\r
11120 #define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL))
\r
11121 #define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL))
\r
11122 #define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL))
\r
11123 #define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL))
\r
11124 #define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL))
\r
11126 /* UART LIN channel 1 registers */
\r
11127 #define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL))
\r
11128 #define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL))
\r
11129 #define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL))
\r
11130 #define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL))
\r
11131 #define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL))
\r
11132 #define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL))
\r
11133 #define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL))
\r
11134 #define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL))
\r
11135 #define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL))
\r
11136 #define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL))
\r
11137 #define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL))
\r
11138 #define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL))
\r
11139 #define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL))
\r
11140 #define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL))
\r
11141 #define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL))
\r
11142 #define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL))
\r
11143 #define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL))
\r
11144 #define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL))
\r
11145 #define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL))
\r
11146 #define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL))
\r
11147 #define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL))
\r
11148 #define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL))
\r
11149 #define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL))
\r
11150 #define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL))
\r
11151 #define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL))
\r
11152 #define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL))
\r
11153 #define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL))
\r
11154 #define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL))
\r
11155 #define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL))
\r
11157 /* I2C channel 1 registers */
\r
11158 #define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL))
\r
11159 #define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL))
\r
11160 #define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL))
\r
11161 #define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL))
\r
11162 #define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL))
\r
11163 #define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL))
\r
11164 #define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL))
\r
11165 #define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL))
\r
11166 #define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL))
\r
11167 #define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL))
\r
11168 #define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL))
\r
11169 #define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL))
\r
11170 #define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL))
\r
11171 #define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL))
\r
11172 #define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL))
\r
11173 #define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL))
\r
11174 #define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL))
\r
11175 #define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL))
\r
11176 #define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL))
\r
11177 #define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL))
\r
11178 #define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL))
\r
11179 #define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL))
\r
11180 #define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL))
\r
11181 #define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL))
\r
11182 #define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL))
\r
11183 #define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL))
\r
11184 #define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL))
\r
11185 #define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL))
\r
11186 #define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL))
\r
11187 #define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL))
\r
11188 #define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL))
\r
11189 #define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL))
\r
11190 #define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL))
\r
11191 #define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL))
\r
11192 #define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL))
\r
11193 #define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL))
\r
11194 #define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL))
\r
11195 #define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL))
\r
11196 #define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL))
\r
11197 #define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL))
\r
11198 #define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL))
\r
11199 #define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL))
\r
11200 #define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL))
\r
11201 #define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL))
\r
11202 #define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL))
\r
11203 #define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL))
\r
11204 #define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL))
\r
11205 #define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL))
\r
11206 #define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL))
\r
11208 /* UART asynchronous channel 2 registers */
\r
11209 #define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL))
\r
11210 #define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL))
\r
11211 #define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL))
\r
11212 #define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL))
\r
11213 #define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL))
\r
11214 #define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL))
\r
11215 #define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL))
\r
11216 #define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL))
\r
11217 #define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL))
\r
11218 #define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL))
\r
11219 #define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL))
\r
11220 #define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL))
\r
11221 #define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL))
\r
11222 #define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL))
\r
11223 #define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL))
\r
11224 #define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL))
\r
11225 #define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL))
\r
11226 #define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL))
\r
11227 #define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL))
\r
11228 #define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL))
\r
11229 #define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL))
\r
11230 #define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL))
\r
11231 #define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL))
\r
11232 #define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL))
\r
11233 #define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL))
\r
11234 #define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL))
\r
11235 #define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL))
\r
11236 #define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL))
\r
11237 #define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL))
\r
11238 #define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL))
\r
11239 #define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL))
\r
11240 #define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL))
\r
11242 /* UART synchronous channel 2 registers */
\r
11243 #define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL))
\r
11244 #define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL))
\r
11245 #define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL))
\r
11246 #define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL))
\r
11247 #define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL))
\r
11248 #define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL))
\r
11249 #define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL))
\r
11250 #define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL))
\r
11251 #define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL))
\r
11252 #define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL))
\r
11253 #define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL))
\r
11254 #define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL))
\r
11255 #define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL))
\r
11256 #define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL))
\r
11257 #define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL))
\r
11258 #define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL))
\r
11259 #define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL))
\r
11260 #define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL))
\r
11261 #define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL))
\r
11262 #define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL))
\r
11263 #define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL))
\r
11264 #define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL))
\r
11265 #define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL))
\r
11266 #define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL))
\r
11267 #define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL))
\r
11268 #define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL))
\r
11269 #define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL))
\r
11271 /* UART LIN channel 2 registers */
\r
11272 #define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL))
\r
11273 #define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL))
\r
11274 #define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL))
\r
11275 #define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL))
\r
11276 #define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL))
\r
11277 #define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL))
\r
11278 #define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL))
\r
11279 #define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL))
\r
11280 #define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL))
\r
11281 #define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL))
\r
11282 #define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL))
\r
11283 #define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL))
\r
11284 #define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL))
\r
11285 #define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL))
\r
11286 #define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL))
\r
11287 #define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL))
\r
11288 #define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL))
\r
11289 #define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL))
\r
11290 #define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL))
\r
11291 #define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL))
\r
11292 #define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL))
\r
11293 #define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL))
\r
11294 #define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL))
\r
11295 #define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL))
\r
11296 #define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL))
\r
11297 #define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL))
\r
11298 #define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL))
\r
11299 #define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL))
\r
11300 #define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL))
\r
11302 /* I2C channel 2 registers */
\r
11303 #define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL))
\r
11304 #define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL))
\r
11305 #define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL))
\r
11306 #define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL))
\r
11307 #define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL))
\r
11308 #define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL))
\r
11309 #define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL))
\r
11310 #define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL))
\r
11311 #define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL))
\r
11312 #define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL))
\r
11313 #define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL))
\r
11314 #define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL))
\r
11315 #define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL))
\r
11316 #define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL))
\r
11317 #define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL))
\r
11318 #define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL))
\r
11319 #define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL))
\r
11320 #define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL))
\r
11321 #define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL))
\r
11322 #define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL))
\r
11323 #define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL))
\r
11324 #define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL))
\r
11325 #define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL))
\r
11326 #define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL))
\r
11327 #define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL))
\r
11328 #define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL))
\r
11329 #define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL))
\r
11330 #define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL))
\r
11331 #define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL))
\r
11332 #define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL))
\r
11333 #define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL))
\r
11334 #define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL))
\r
11335 #define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL))
\r
11336 #define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL))
\r
11337 #define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL))
\r
11338 #define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL))
\r
11339 #define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL))
\r
11340 #define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL))
\r
11341 #define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL))
\r
11342 #define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL))
\r
11343 #define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL))
\r
11344 #define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL))
\r
11345 #define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL))
\r
11346 #define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL))
\r
11347 #define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL))
\r
11348 #define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL))
\r
11349 #define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL))
\r
11350 #define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL))
\r
11351 #define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL))
\r
11353 /* UART asynchronous channel 3 registers */
\r
11354 #define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL))
\r
11355 #define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL))
\r
11356 #define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL))
\r
11357 #define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL))
\r
11358 #define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL))
\r
11359 #define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL))
\r
11360 #define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL))
\r
11361 #define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL))
\r
11362 #define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL))
\r
11363 #define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL))
\r
11364 #define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL))
\r
11365 #define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL))
\r
11366 #define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL))
\r
11367 #define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL))
\r
11368 #define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL))
\r
11369 #define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL))
\r
11370 #define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL))
\r
11371 #define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL))
\r
11372 #define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL))
\r
11373 #define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL))
\r
11374 #define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL))
\r
11375 #define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL))
\r
11376 #define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL))
\r
11377 #define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL))
\r
11378 #define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL))
\r
11379 #define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL))
\r
11380 #define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL))
\r
11381 #define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL))
\r
11382 #define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL))
\r
11383 #define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL))
\r
11384 #define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL))
\r
11385 #define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL))
\r
11387 /* UART synchronous channel 3 registers */
\r
11388 #define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL))
\r
11389 #define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL))
\r
11390 #define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL))
\r
11391 #define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL))
\r
11392 #define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL))
\r
11393 #define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL))
\r
11394 #define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL))
\r
11395 #define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL))
\r
11396 #define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL))
\r
11397 #define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL))
\r
11398 #define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL))
\r
11399 #define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL))
\r
11400 #define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL))
\r
11401 #define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL))
\r
11402 #define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL))
\r
11403 #define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL))
\r
11404 #define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL))
\r
11405 #define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL))
\r
11406 #define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL))
\r
11407 #define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL))
\r
11408 #define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL))
\r
11409 #define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL))
\r
11410 #define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL))
\r
11411 #define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL))
\r
11412 #define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL))
\r
11413 #define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL))
\r
11414 #define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL))
\r
11416 /* UART LIN channel 3 registers */
\r
11417 #define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL))
\r
11418 #define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL))
\r
11419 #define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL))
\r
11420 #define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL))
\r
11421 #define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL))
\r
11422 #define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL))
\r
11423 #define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL))
\r
11424 #define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL))
\r
11425 #define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL))
\r
11426 #define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL))
\r
11427 #define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL))
\r
11428 #define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL))
\r
11429 #define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL))
\r
11430 #define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL))
\r
11431 #define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL))
\r
11432 #define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL))
\r
11433 #define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL))
\r
11434 #define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL))
\r
11435 #define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL))
\r
11436 #define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL))
\r
11437 #define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL))
\r
11438 #define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL))
\r
11439 #define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL))
\r
11440 #define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL))
\r
11441 #define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL))
\r
11442 #define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL))
\r
11443 #define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL))
\r
11444 #define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL))
\r
11445 #define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL))
\r
11447 /* I2C channel 3 registers */
\r
11448 #define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL))
\r
11449 #define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL))
\r
11450 #define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL))
\r
11451 #define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL))
\r
11452 #define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL))
\r
11453 #define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL))
\r
11454 #define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL))
\r
11455 #define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL))
\r
11456 #define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL))
\r
11457 #define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL))
\r
11458 #define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL))
\r
11459 #define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL))
\r
11460 #define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL))
\r
11461 #define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL))
\r
11462 #define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL))
\r
11463 #define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL))
\r
11464 #define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL))
\r
11465 #define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL))
\r
11466 #define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL))
\r
11467 #define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL))
\r
11468 #define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL))
\r
11469 #define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL))
\r
11470 #define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL))
\r
11471 #define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL))
\r
11472 #define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL))
\r
11473 #define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL))
\r
11474 #define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL))
\r
11475 #define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL))
\r
11476 #define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL))
\r
11477 #define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL))
\r
11478 #define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL))
\r
11479 #define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL))
\r
11480 #define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL))
\r
11481 #define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL))
\r
11482 #define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL))
\r
11483 #define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL))
\r
11484 #define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL))
\r
11485 #define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL))
\r
11486 #define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL))
\r
11487 #define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL))
\r
11488 #define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL))
\r
11489 #define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL))
\r
11490 #define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL))
\r
11491 #define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL))
\r
11492 #define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL))
\r
11493 #define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL))
\r
11494 #define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL))
\r
11495 #define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL))
\r
11496 #define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL))
\r
11498 /* UART asynchronous channel 4 registers */
\r
11499 #define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL))
\r
11500 #define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL))
\r
11501 #define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL))
\r
11502 #define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL))
\r
11503 #define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL))
\r
11504 #define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL))
\r
11505 #define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL))
\r
11506 #define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL))
\r
11507 #define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL))
\r
11508 #define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL))
\r
11509 #define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL))
\r
11510 #define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL))
\r
11511 #define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL))
\r
11512 #define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL))
\r
11513 #define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL))
\r
11514 #define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL))
\r
11515 #define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL))
\r
11516 #define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL))
\r
11517 #define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL))
\r
11518 #define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL))
\r
11519 #define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL))
\r
11520 #define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL))
\r
11521 #define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL))
\r
11522 #define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL))
\r
11523 #define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL))
\r
11524 #define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL))
\r
11525 #define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL))
\r
11526 #define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL))
\r
11527 #define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL))
\r
11528 #define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL))
\r
11529 #define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL))
\r
11530 #define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL))
\r
11531 #define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11532 #define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11533 #define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11534 #define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11535 #define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11536 #define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11537 #define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11538 #define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11539 #define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11540 #define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11541 #define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11542 #define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11543 #define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11544 #define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11545 #define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11546 #define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11547 #define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11548 #define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11549 #define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11550 #define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11551 #define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11552 #define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11553 #define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11554 #define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11555 #define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11556 #define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11557 #define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11558 #define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11559 #define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11560 #define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11561 #define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11562 #define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11563 #define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11564 #define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11565 #define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11566 #define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11567 #define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11568 #define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11569 #define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11570 #define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11571 #define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11572 #define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11573 #define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11574 #define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11575 #define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11576 #define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11577 #define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11578 #define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11579 #define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11580 #define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11581 #define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11582 #define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11583 #define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11584 #define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11585 #define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11586 #define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11587 #define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11588 #define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11589 #define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11590 #define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11592 /* UART synchronous channel 4 registers */
\r
11593 #define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL))
\r
11594 #define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL))
\r
11595 #define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL))
\r
11596 #define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL))
\r
11597 #define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL))
\r
11598 #define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL))
\r
11599 #define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL))
\r
11600 #define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL))
\r
11601 #define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL))
\r
11602 #define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL))
\r
11603 #define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL))
\r
11604 #define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL))
\r
11605 #define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL))
\r
11606 #define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL))
\r
11607 #define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL))
\r
11608 #define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL))
\r
11609 #define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL))
\r
11610 #define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL))
\r
11611 #define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL))
\r
11612 #define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL))
\r
11613 #define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL))
\r
11614 #define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL))
\r
11615 #define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL))
\r
11616 #define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL))
\r
11617 #define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL))
\r
11618 #define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL))
\r
11619 #define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL))
\r
11620 #define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11621 #define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11622 #define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11623 #define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11624 #define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11625 #define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11626 #define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11627 #define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11628 #define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11629 #define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11630 #define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11631 #define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11632 #define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11633 #define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11634 #define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11635 #define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11636 #define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11637 #define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11638 #define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11639 #define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11640 #define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11641 #define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11642 #define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11643 #define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11644 #define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11645 #define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11646 #define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11647 #define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11648 #define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11649 #define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11650 #define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11651 #define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11652 #define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11653 #define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11654 #define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11655 #define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11656 #define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11657 #define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11658 #define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11659 #define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11660 #define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11661 #define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11662 #define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11663 #define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11664 #define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11665 #define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11666 #define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11667 #define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11668 #define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11669 #define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11670 #define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11671 #define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11672 #define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11673 #define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11674 #define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11675 #define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11676 #define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11677 #define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11678 #define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11679 #define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11681 /* UART LIN channel 4 registers */
\r
11682 #define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL))
\r
11683 #define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL))
\r
11684 #define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL))
\r
11685 #define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL))
\r
11686 #define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL))
\r
11687 #define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL))
\r
11688 #define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL))
\r
11689 #define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL))
\r
11690 #define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL))
\r
11691 #define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL))
\r
11692 #define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL))
\r
11693 #define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL))
\r
11694 #define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL))
\r
11695 #define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL))
\r
11696 #define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL))
\r
11697 #define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL))
\r
11698 #define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL))
\r
11699 #define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL))
\r
11700 #define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL))
\r
11701 #define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL))
\r
11702 #define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL))
\r
11703 #define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL))
\r
11704 #define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL))
\r
11705 #define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL))
\r
11706 #define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL))
\r
11707 #define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL))
\r
11708 #define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL))
\r
11709 #define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL))
\r
11710 #define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL))
\r
11711 #define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11712 #define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11713 #define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11714 #define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11715 #define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11716 #define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11717 #define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11718 #define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11719 #define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11720 #define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11721 #define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11722 #define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11723 #define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11724 #define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11725 #define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11726 #define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11727 #define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11728 #define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11729 #define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11730 #define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11731 #define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11732 #define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11733 #define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11734 #define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11735 #define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11736 #define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11737 #define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11738 #define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11739 #define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11740 #define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11741 #define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11742 #define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11743 #define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11744 #define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11745 #define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11746 #define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11747 #define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11748 #define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11749 #define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11750 #define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11751 #define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11752 #define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11753 #define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11754 #define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11755 #define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11756 #define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11757 #define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11758 #define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11759 #define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11760 #define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11761 #define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11762 #define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11763 #define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11764 #define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11765 #define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11766 #define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11767 #define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11768 #define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11769 #define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11770 #define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11772 /* I2C channel 4 registers */
\r
11773 #define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL))
\r
11774 #define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL))
\r
11775 #define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL))
\r
11776 #define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL))
\r
11777 #define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL))
\r
11778 #define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL))
\r
11779 #define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL))
\r
11780 #define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL))
\r
11781 #define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL))
\r
11782 #define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL))
\r
11783 #define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL))
\r
11784 #define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL))
\r
11785 #define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL))
\r
11786 #define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL))
\r
11787 #define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL))
\r
11788 #define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL))
\r
11789 #define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL))
\r
11790 #define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL))
\r
11791 #define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL))
\r
11792 #define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL))
\r
11793 #define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL))
\r
11794 #define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL))
\r
11795 #define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL))
\r
11796 #define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL))
\r
11797 #define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL))
\r
11798 #define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL))
\r
11799 #define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL))
\r
11800 #define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL))
\r
11801 #define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL))
\r
11802 #define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL))
\r
11803 #define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL))
\r
11804 #define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL))
\r
11805 #define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL))
\r
11806 #define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL))
\r
11807 #define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL))
\r
11808 #define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL))
\r
11809 #define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL))
\r
11810 #define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL))
\r
11811 #define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL))
\r
11812 #define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL))
\r
11813 #define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL))
\r
11814 #define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL))
\r
11815 #define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL))
\r
11816 #define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL))
\r
11817 #define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL))
\r
11818 #define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL))
\r
11819 #define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL))
\r
11820 #define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL))
\r
11821 #define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL))
\r
11822 #define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11823 #define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11824 #define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11825 #define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11826 #define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11827 #define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11828 #define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11829 #define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11830 #define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11831 #define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11832 #define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11833 #define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11834 #define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11835 #define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11836 #define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL))
\r
11837 #define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL))
\r
11838 #define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL))
\r
11839 #define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL))
\r
11840 #define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL))
\r
11841 #define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL))
\r
11842 #define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL))
\r
11843 #define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL))
\r
11844 #define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL))
\r
11845 #define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL))
\r
11846 #define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL))
\r
11847 #define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL))
\r
11848 #define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL))
\r
11849 #define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL))
\r
11850 #define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11851 #define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11852 #define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11853 #define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11854 #define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11855 #define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11856 #define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11857 #define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11858 #define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11859 #define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11860 #define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11861 #define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11862 #define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11863 #define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11864 #define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11865 #define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11866 #define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL))
\r
11867 #define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL))
\r
11868 #define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL))
\r
11869 #define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL))
\r
11870 #define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL))
\r
11871 #define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL))
\r
11872 #define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL))
\r
11873 #define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL))
\r
11874 #define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL))
\r
11875 #define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL))
\r
11876 #define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL))
\r
11877 #define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL))
\r
11878 #define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL))
\r
11879 #define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL))
\r
11880 #define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL))
\r
11881 #define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL))
\r
11883 /* UART asynchronous channel 5 registers */
\r
11884 #define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL))
\r
11885 #define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL))
\r
11886 #define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL))
\r
11887 #define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL))
\r
11888 #define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL))
\r
11889 #define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL))
\r
11890 #define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL))
\r
11891 #define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL))
\r
11892 #define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL))
\r
11893 #define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL))
\r
11894 #define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL))
\r
11895 #define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL))
\r
11896 #define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL))
\r
11897 #define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL))
\r
11898 #define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL))
\r
11899 #define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL))
\r
11900 #define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL))
\r
11901 #define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL))
\r
11902 #define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL))
\r
11903 #define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL))
\r
11904 #define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL))
\r
11905 #define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL))
\r
11906 #define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL))
\r
11907 #define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL))
\r
11908 #define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL))
\r
11909 #define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL))
\r
11910 #define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL))
\r
11911 #define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL))
\r
11912 #define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL))
\r
11913 #define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL))
\r
11914 #define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL))
\r
11915 #define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL))
\r
11916 #define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
11917 #define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
11918 #define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
11919 #define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
11920 #define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
11921 #define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
11922 #define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
11923 #define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
11924 #define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
11925 #define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
11926 #define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
11927 #define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
11928 #define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
11929 #define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
11930 #define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
11931 #define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
11932 #define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
11933 #define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
11934 #define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
11935 #define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
11936 #define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
11937 #define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
11938 #define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
11939 #define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
11940 #define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
11941 #define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
11942 #define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
11943 #define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
11944 #define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
11945 #define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
11946 #define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
11947 #define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
11948 #define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
11949 #define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
11950 #define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
11951 #define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
11952 #define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
11953 #define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
11954 #define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
11955 #define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
11956 #define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
11957 #define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
11958 #define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
11959 #define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
11960 #define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
11961 #define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
11962 #define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
11963 #define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
11964 #define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
11965 #define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
11966 #define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
11967 #define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
11968 #define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
11969 #define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
11970 #define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
11971 #define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
11972 #define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
11973 #define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
11974 #define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
11975 #define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
11977 /* UART synchronous channel 5 registers */
\r
11978 #define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL))
\r
11979 #define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL))
\r
11980 #define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL))
\r
11981 #define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL))
\r
11982 #define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL))
\r
11983 #define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL))
\r
11984 #define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL))
\r
11985 #define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL))
\r
11986 #define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL))
\r
11987 #define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL))
\r
11988 #define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL))
\r
11989 #define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL))
\r
11990 #define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL))
\r
11991 #define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL))
\r
11992 #define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL))
\r
11993 #define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL))
\r
11994 #define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL))
\r
11995 #define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL))
\r
11996 #define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL))
\r
11997 #define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL))
\r
11998 #define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL))
\r
11999 #define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL))
\r
12000 #define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL))
\r
12001 #define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL))
\r
12002 #define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL))
\r
12003 #define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL))
\r
12004 #define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL))
\r
12005 #define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
12006 #define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
12007 #define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
12008 #define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
12009 #define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
12010 #define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
12011 #define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
12012 #define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
12013 #define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
12014 #define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
12015 #define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
12016 #define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
12017 #define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
12018 #define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
12019 #define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
12020 #define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
12021 #define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
12022 #define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
12023 #define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
12024 #define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
12025 #define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
12026 #define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
12027 #define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
12028 #define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
12029 #define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
12030 #define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
12031 #define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
12032 #define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
12033 #define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
12034 #define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
12035 #define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
12036 #define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
12037 #define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
12038 #define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
12039 #define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
12040 #define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
12041 #define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
12042 #define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
12043 #define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
12044 #define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
12045 #define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
12046 #define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
12047 #define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
12048 #define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
12049 #define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
12050 #define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
12051 #define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
12052 #define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
12053 #define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
12054 #define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
12055 #define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
12056 #define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
12057 #define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
12058 #define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
12059 #define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
12060 #define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
12061 #define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
12062 #define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
12063 #define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
12064 #define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
12066 /* UART LIN channel 5 registers */
\r
12067 #define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL))
\r
12068 #define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL))
\r
12069 #define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL))
\r
12070 #define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL))
\r
12071 #define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL))
\r
12072 #define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL))
\r
12073 #define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL))
\r
12074 #define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL))
\r
12075 #define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL))
\r
12076 #define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL))
\r
12077 #define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL))
\r
12078 #define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL))
\r
12079 #define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL))
\r
12080 #define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL))
\r
12081 #define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL))
\r
12082 #define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL))
\r
12083 #define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL))
\r
12084 #define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL))
\r
12085 #define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL))
\r
12086 #define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL))
\r
12087 #define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL))
\r
12088 #define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL))
\r
12089 #define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL))
\r
12090 #define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL))
\r
12091 #define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL))
\r
12092 #define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL))
\r
12093 #define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL))
\r
12094 #define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL))
\r
12095 #define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL))
\r
12096 #define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
12097 #define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
12098 #define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
12099 #define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
12100 #define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
12101 #define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
12102 #define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
12103 #define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
12104 #define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
12105 #define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
12106 #define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
12107 #define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
12108 #define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
12109 #define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
12110 #define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
12111 #define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
12112 #define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
12113 #define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
12114 #define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
12115 #define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
12116 #define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
12117 #define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
12118 #define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
12119 #define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
12120 #define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
12121 #define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
12122 #define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
12123 #define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
12124 #define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
12125 #define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
12126 #define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
12127 #define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
12128 #define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
12129 #define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
12130 #define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
12131 #define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
12132 #define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
12133 #define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
12134 #define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
12135 #define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
12136 #define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
12137 #define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
12138 #define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
12139 #define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
12140 #define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
12141 #define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
12142 #define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
12143 #define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
12144 #define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
12145 #define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
12146 #define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
12147 #define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
12148 #define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
12149 #define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
12150 #define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
12151 #define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
12152 #define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
12153 #define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
12154 #define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
12155 #define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
12157 /* I2C channel 5 registers */
\r
12158 #define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL))
\r
12159 #define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL))
\r
12160 #define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL))
\r
12161 #define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL))
\r
12162 #define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL))
\r
12163 #define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL))
\r
12164 #define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL))
\r
12165 #define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL))
\r
12166 #define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL))
\r
12167 #define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL))
\r
12168 #define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL))
\r
12169 #define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL))
\r
12170 #define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL))
\r
12171 #define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL))
\r
12172 #define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL))
\r
12173 #define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL))
\r
12174 #define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL))
\r
12175 #define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL))
\r
12176 #define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL))
\r
12177 #define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL))
\r
12178 #define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL))
\r
12179 #define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL))
\r
12180 #define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL))
\r
12181 #define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL))
\r
12182 #define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL))
\r
12183 #define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL))
\r
12184 #define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL))
\r
12185 #define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL))
\r
12186 #define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL))
\r
12187 #define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL))
\r
12188 #define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL))
\r
12189 #define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL))
\r
12190 #define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL))
\r
12191 #define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL))
\r
12192 #define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL))
\r
12193 #define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL))
\r
12194 #define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL))
\r
12195 #define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL))
\r
12196 #define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL))
\r
12197 #define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL))
\r
12198 #define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL))
\r
12199 #define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL))
\r
12200 #define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL))
\r
12201 #define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL))
\r
12202 #define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL))
\r
12203 #define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL))
\r
12204 #define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL))
\r
12205 #define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL))
\r
12206 #define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL))
\r
12207 #define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
12208 #define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
12209 #define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
12210 #define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
12211 #define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
12212 #define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
12213 #define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
12214 #define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
12215 #define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
12216 #define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
12217 #define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
12218 #define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
12219 #define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
12220 #define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
12221 #define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL))
\r
12222 #define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL))
\r
12223 #define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL))
\r
12224 #define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL))
\r
12225 #define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL))
\r
12226 #define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL))
\r
12227 #define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL))
\r
12228 #define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL))
\r
12229 #define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL))
\r
12230 #define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL))
\r
12231 #define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL))
\r
12232 #define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL))
\r
12233 #define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL))
\r
12234 #define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL))
\r
12235 #define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
12236 #define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
12237 #define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
12238 #define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
12239 #define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
12240 #define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
12241 #define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
12242 #define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
12243 #define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
12244 #define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
12245 #define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
12246 #define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
12247 #define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
12248 #define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
12249 #define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
12250 #define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
12251 #define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL))
\r
12252 #define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL))
\r
12253 #define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL))
\r
12254 #define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL))
\r
12255 #define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL))
\r
12256 #define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL))
\r
12257 #define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL))
\r
12258 #define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL))
\r
12259 #define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL))
\r
12260 #define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL))
\r
12261 #define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL))
\r
12262 #define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL))
\r
12263 #define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL))
\r
12264 #define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL))
\r
12265 #define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL))
\r
12266 #define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL))
\r
12268 /* UART asynchronous channel 6 registers */
\r
12269 #define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL))
\r
12270 #define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL))
\r
12271 #define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL))
\r
12272 #define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL))
\r
12273 #define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL))
\r
12274 #define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL))
\r
12275 #define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL))
\r
12276 #define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL))
\r
12277 #define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL))
\r
12278 #define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL))
\r
12279 #define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL))
\r
12280 #define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL))
\r
12281 #define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL))
\r
12282 #define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL))
\r
12283 #define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL))
\r
12284 #define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL))
\r
12285 #define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL))
\r
12286 #define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL))
\r
12287 #define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL))
\r
12288 #define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL))
\r
12289 #define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL))
\r
12290 #define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL))
\r
12291 #define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL))
\r
12292 #define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL))
\r
12293 #define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL))
\r
12294 #define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL))
\r
12295 #define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL))
\r
12296 #define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL))
\r
12297 #define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL))
\r
12298 #define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL))
\r
12299 #define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL))
\r
12300 #define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL))
\r
12301 #define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12302 #define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12303 #define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12304 #define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12305 #define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12306 #define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12307 #define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12308 #define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12309 #define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12310 #define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12311 #define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12312 #define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12313 #define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12314 #define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12315 #define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12316 #define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12317 #define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12318 #define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12319 #define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12320 #define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12321 #define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12322 #define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12323 #define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12324 #define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12325 #define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12326 #define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12327 #define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12328 #define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12329 #define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12330 #define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12331 #define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12332 #define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12333 #define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12334 #define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12335 #define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12336 #define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12337 #define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12338 #define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12339 #define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12340 #define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12341 #define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12342 #define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12343 #define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12344 #define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12345 #define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12346 #define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12347 #define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12348 #define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12349 #define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12350 #define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12351 #define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12352 #define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12353 #define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12354 #define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12355 #define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12356 #define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12357 #define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12358 #define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12359 #define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12360 #define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12362 /* UART synchronous channel 6 registers */
\r
12363 #define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL))
\r
12364 #define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL))
\r
12365 #define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL))
\r
12366 #define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL))
\r
12367 #define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL))
\r
12368 #define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL))
\r
12369 #define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL))
\r
12370 #define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL))
\r
12371 #define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL))
\r
12372 #define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL))
\r
12373 #define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL))
\r
12374 #define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL))
\r
12375 #define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL))
\r
12376 #define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL))
\r
12377 #define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL))
\r
12378 #define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL))
\r
12379 #define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL))
\r
12380 #define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL))
\r
12381 #define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL))
\r
12382 #define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL))
\r
12383 #define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL))
\r
12384 #define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL))
\r
12385 #define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL))
\r
12386 #define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL))
\r
12387 #define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL))
\r
12388 #define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL))
\r
12389 #define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL))
\r
12390 #define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12391 #define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12392 #define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12393 #define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12394 #define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12395 #define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12396 #define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12397 #define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12398 #define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12399 #define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12400 #define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12401 #define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12402 #define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12403 #define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12404 #define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12405 #define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12406 #define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12407 #define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12408 #define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12409 #define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12410 #define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12411 #define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12412 #define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12413 #define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12414 #define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12415 #define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12416 #define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12417 #define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12418 #define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12419 #define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12420 #define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12421 #define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12422 #define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12423 #define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12424 #define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12425 #define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12426 #define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12427 #define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12428 #define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12429 #define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12430 #define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12431 #define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12432 #define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12433 #define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12434 #define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12435 #define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12436 #define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12437 #define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12438 #define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12439 #define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12440 #define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12441 #define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12442 #define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12443 #define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12444 #define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12445 #define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12446 #define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12447 #define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12448 #define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12449 #define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12451 /* UART LIN channel 6 registers */
\r
12452 #define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL))
\r
12453 #define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL))
\r
12454 #define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL))
\r
12455 #define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL))
\r
12456 #define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL))
\r
12457 #define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL))
\r
12458 #define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL))
\r
12459 #define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL))
\r
12460 #define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL))
\r
12461 #define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL))
\r
12462 #define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL))
\r
12463 #define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL))
\r
12464 #define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL))
\r
12465 #define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL))
\r
12466 #define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL))
\r
12467 #define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL))
\r
12468 #define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL))
\r
12469 #define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL))
\r
12470 #define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL))
\r
12471 #define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL))
\r
12472 #define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL))
\r
12473 #define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL))
\r
12474 #define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL))
\r
12475 #define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL))
\r
12476 #define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL))
\r
12477 #define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL))
\r
12478 #define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL))
\r
12479 #define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL))
\r
12480 #define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL))
\r
12481 #define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12482 #define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12483 #define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12484 #define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12485 #define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12486 #define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12487 #define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12488 #define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12489 #define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12490 #define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12491 #define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12492 #define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12493 #define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12494 #define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12495 #define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12496 #define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12497 #define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12498 #define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12499 #define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12500 #define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12501 #define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12502 #define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12503 #define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12504 #define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12505 #define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12506 #define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12507 #define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12508 #define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12509 #define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12510 #define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12511 #define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12512 #define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12513 #define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12514 #define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12515 #define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12516 #define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12517 #define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12518 #define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12519 #define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12520 #define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12521 #define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12522 #define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12523 #define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12524 #define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12525 #define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12526 #define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12527 #define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12528 #define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12529 #define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12530 #define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12531 #define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12532 #define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12533 #define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12534 #define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12535 #define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12536 #define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12537 #define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12538 #define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12539 #define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12540 #define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12542 /* I2C channel 6 registers */
\r
12543 #define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL))
\r
12544 #define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL))
\r
12545 #define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL))
\r
12546 #define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL))
\r
12547 #define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL))
\r
12548 #define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL))
\r
12549 #define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL))
\r
12550 #define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL))
\r
12551 #define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL))
\r
12552 #define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL))
\r
12553 #define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL))
\r
12554 #define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL))
\r
12555 #define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL))
\r
12556 #define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL))
\r
12557 #define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL))
\r
12558 #define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL))
\r
12559 #define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL))
\r
12560 #define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL))
\r
12561 #define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL))
\r
12562 #define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL))
\r
12563 #define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL))
\r
12564 #define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL))
\r
12565 #define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL))
\r
12566 #define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL))
\r
12567 #define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL))
\r
12568 #define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL))
\r
12569 #define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL))
\r
12570 #define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL))
\r
12571 #define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL))
\r
12572 #define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL))
\r
12573 #define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL))
\r
12574 #define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL))
\r
12575 #define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL))
\r
12576 #define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL))
\r
12577 #define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL))
\r
12578 #define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL))
\r
12579 #define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL))
\r
12580 #define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL))
\r
12581 #define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL))
\r
12582 #define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL))
\r
12583 #define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL))
\r
12584 #define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL))
\r
12585 #define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL))
\r
12586 #define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL))
\r
12587 #define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL))
\r
12588 #define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL))
\r
12589 #define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL))
\r
12590 #define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL))
\r
12591 #define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL))
\r
12592 #define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12593 #define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12594 #define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12595 #define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12596 #define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12597 #define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12598 #define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12599 #define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12600 #define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12601 #define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12602 #define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12603 #define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12604 #define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12605 #define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12606 #define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL))
\r
12607 #define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL))
\r
12608 #define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL))
\r
12609 #define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL))
\r
12610 #define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL))
\r
12611 #define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL))
\r
12612 #define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL))
\r
12613 #define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL))
\r
12614 #define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL))
\r
12615 #define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL))
\r
12616 #define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL))
\r
12617 #define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL))
\r
12618 #define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL))
\r
12619 #define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL))
\r
12620 #define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12621 #define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12622 #define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12623 #define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12624 #define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12625 #define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12626 #define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12627 #define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12628 #define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12629 #define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12630 #define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12631 #define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12632 #define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12633 #define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12634 #define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12635 #define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12636 #define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL))
\r
12637 #define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL))
\r
12638 #define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL))
\r
12639 #define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL))
\r
12640 #define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL))
\r
12641 #define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL))
\r
12642 #define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL))
\r
12643 #define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL))
\r
12644 #define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL))
\r
12645 #define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL))
\r
12646 #define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL))
\r
12647 #define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL))
\r
12648 #define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL))
\r
12649 #define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL))
\r
12650 #define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL))
\r
12651 #define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL))
\r
12653 /* UART asynchronous channel 7 registers */
\r
12654 #define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL))
\r
12655 #define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL))
\r
12656 #define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL))
\r
12657 #define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL))
\r
12658 #define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL))
\r
12659 #define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL))
\r
12660 #define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL))
\r
12661 #define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL))
\r
12662 #define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL))
\r
12663 #define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL))
\r
12664 #define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL))
\r
12665 #define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL))
\r
12666 #define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL))
\r
12667 #define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL))
\r
12668 #define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL))
\r
12669 #define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL))
\r
12670 #define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL))
\r
12671 #define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL))
\r
12672 #define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL))
\r
12673 #define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL))
\r
12674 #define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL))
\r
12675 #define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL))
\r
12676 #define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL))
\r
12677 #define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL))
\r
12678 #define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL))
\r
12679 #define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL))
\r
12680 #define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL))
\r
12681 #define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL))
\r
12682 #define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL))
\r
12683 #define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL))
\r
12684 #define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL))
\r
12685 #define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL))
\r
12686 #define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12687 #define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12688 #define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12689 #define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12690 #define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12691 #define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12692 #define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12693 #define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12694 #define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12695 #define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12696 #define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12697 #define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12698 #define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12699 #define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12700 #define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12701 #define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12702 #define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12703 #define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12704 #define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12705 #define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12706 #define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12707 #define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12708 #define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12709 #define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12710 #define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12711 #define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12712 #define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12713 #define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12714 #define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
12715 #define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
12716 #define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
12717 #define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
12718 #define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
12719 #define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
12720 #define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
12721 #define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
12722 #define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
12723 #define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
12724 #define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
12725 #define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
12726 #define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
12727 #define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
12728 #define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
12729 #define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
12730 #define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
12731 #define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
12732 #define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
12733 #define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
12734 #define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
12735 #define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
12736 #define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
12737 #define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
12738 #define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
12739 #define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
12740 #define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
12741 #define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
12742 #define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
12743 #define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
12744 #define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
12745 #define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
12747 /* UART synchronous channel 7 registers */
\r
12748 #define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL))
\r
12749 #define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL))
\r
12750 #define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL))
\r
12751 #define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL))
\r
12752 #define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL))
\r
12753 #define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL))
\r
12754 #define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL))
\r
12755 #define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL))
\r
12756 #define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL))
\r
12757 #define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL))
\r
12758 #define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL))
\r
12759 #define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL))
\r
12760 #define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL))
\r
12761 #define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL))
\r
12762 #define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL))
\r
12763 #define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL))
\r
12764 #define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL))
\r
12765 #define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL))
\r
12766 #define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL))
\r
12767 #define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL))
\r
12768 #define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL))
\r
12769 #define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL))
\r
12770 #define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL))
\r
12771 #define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL))
\r
12772 #define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL))
\r
12773 #define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL))
\r
12774 #define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL))
\r
12775 #define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12776 #define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12777 #define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12778 #define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12779 #define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12780 #define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12781 #define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12782 #define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12783 #define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12784 #define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12785 #define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12786 #define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12787 #define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12788 #define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12789 #define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12790 #define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12791 #define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12792 #define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12793 #define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12794 #define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12795 #define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12796 #define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12797 #define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12798 #define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12799 #define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12800 #define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12801 #define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12802 #define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12803 #define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
12804 #define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
12805 #define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
12806 #define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
12807 #define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
12808 #define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
12809 #define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
12810 #define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
12811 #define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
12812 #define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
12813 #define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
12814 #define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
12815 #define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
12816 #define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
12817 #define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
12818 #define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
12819 #define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
12820 #define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
12821 #define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
12822 #define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
12823 #define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
12824 #define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
12825 #define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
12826 #define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
12827 #define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
12828 #define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
12829 #define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
12830 #define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
12831 #define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
12832 #define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
12833 #define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
12834 #define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
12836 /* UART LIN channel 7 registers */
\r
12837 #define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL))
\r
12838 #define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL))
\r
12839 #define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL))
\r
12840 #define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL))
\r
12841 #define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL))
\r
12842 #define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL))
\r
12843 #define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL))
\r
12844 #define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL))
\r
12845 #define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL))
\r
12846 #define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL))
\r
12847 #define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL))
\r
12848 #define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL))
\r
12849 #define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL))
\r
12850 #define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL))
\r
12851 #define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL))
\r
12852 #define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL))
\r
12853 #define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL))
\r
12854 #define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL))
\r
12855 #define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL))
\r
12856 #define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL))
\r
12857 #define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL))
\r
12858 #define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL))
\r
12859 #define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL))
\r
12860 #define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL))
\r
12861 #define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL))
\r
12862 #define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL))
\r
12863 #define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL))
\r
12864 #define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL))
\r
12865 #define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL))
\r
12866 #define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12867 #define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12868 #define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12869 #define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12870 #define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12871 #define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12872 #define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12873 #define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12874 #define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12875 #define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12876 #define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12877 #define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12878 #define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12879 #define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12880 #define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12881 #define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12882 #define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12883 #define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12884 #define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12885 #define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12886 #define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12887 #define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12888 #define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12889 #define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12890 #define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12891 #define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12892 #define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12893 #define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12894 #define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
12895 #define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
12896 #define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
12897 #define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
12898 #define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
12899 #define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
12900 #define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
12901 #define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
12902 #define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
12903 #define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
12904 #define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
12905 #define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
12906 #define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
12907 #define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
12908 #define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
12909 #define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
12910 #define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
12911 #define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
12912 #define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
12913 #define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
12914 #define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
12915 #define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
12916 #define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
12917 #define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
12918 #define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
12919 #define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
12920 #define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
12921 #define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
12922 #define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
12923 #define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
12924 #define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
12925 #define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
12927 /* I2C channel 7 registers */
\r
12928 #define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL))
\r
12929 #define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL))
\r
12930 #define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL))
\r
12931 #define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL))
\r
12932 #define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL))
\r
12933 #define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL))
\r
12934 #define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL))
\r
12935 #define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL))
\r
12936 #define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL))
\r
12937 #define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL))
\r
12938 #define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL))
\r
12939 #define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL))
\r
12940 #define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL))
\r
12941 #define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL))
\r
12942 #define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL))
\r
12943 #define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL))
\r
12944 #define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL))
\r
12945 #define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL))
\r
12946 #define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL))
\r
12947 #define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL))
\r
12948 #define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL))
\r
12949 #define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL))
\r
12950 #define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL))
\r
12951 #define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL))
\r
12952 #define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL))
\r
12953 #define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL))
\r
12954 #define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL))
\r
12955 #define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL))
\r
12956 #define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL))
\r
12957 #define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL))
\r
12958 #define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL))
\r
12959 #define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL))
\r
12960 #define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL))
\r
12961 #define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL))
\r
12962 #define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL))
\r
12963 #define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL))
\r
12964 #define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL))
\r
12965 #define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL))
\r
12966 #define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL))
\r
12967 #define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL))
\r
12968 #define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL))
\r
12969 #define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL))
\r
12970 #define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL))
\r
12971 #define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL))
\r
12972 #define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL))
\r
12973 #define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL))
\r
12974 #define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL))
\r
12975 #define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL))
\r
12976 #define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL))
\r
12977 #define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12978 #define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12979 #define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12980 #define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12981 #define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12982 #define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12983 #define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12984 #define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12985 #define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
12986 #define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
12987 #define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
12988 #define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
12989 #define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
12990 #define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
12991 #define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL))
\r
12992 #define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL))
\r
12993 #define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL))
\r
12994 #define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL))
\r
12995 #define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL))
\r
12996 #define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL))
\r
12997 #define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL))
\r
12998 #define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL))
\r
12999 #define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL))
\r
13000 #define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL))
\r
13001 #define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL))
\r
13002 #define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL))
\r
13003 #define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL))
\r
13004 #define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL))
\r
13005 #define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
13006 #define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
13007 #define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
13008 #define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
13009 #define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
13010 #define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
13011 #define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
13012 #define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
13013 #define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
13014 #define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
13015 #define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
13016 #define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
13017 #define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
13018 #define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
13019 #define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
13020 #define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
13021 #define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL))
\r
13022 #define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL))
\r
13023 #define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL))
\r
13024 #define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL))
\r
13025 #define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL))
\r
13026 #define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL))
\r
13027 #define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL))
\r
13028 #define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL))
\r
13029 #define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL))
\r
13030 #define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL))
\r
13031 #define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL))
\r
13032 #define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL))
\r
13033 #define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL))
\r
13034 #define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL))
\r
13035 #define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL))
\r
13036 #define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL))
\r
13038 /* CRC registers */
\r
13039 #define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL))
\r
13040 #define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL))
\r
13041 #define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL))
\r
13042 #define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL))
\r
13043 #define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL))
\r
13044 #define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL))
\r
13045 #define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL))
\r
13047 /* Watch counter registers */
\r
13048 #define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL))
\r
13049 #define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL))
\r
13050 #define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL))
\r
13051 #define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL))
\r
13052 #define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL))
\r
13053 #define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL))
\r
13054 #define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL))
\r
13055 #define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL))
\r
13056 #define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL))
\r
13057 #define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL))
\r
13058 #define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL))
\r
13059 #define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL))
\r
13060 #define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL))
\r
13061 #define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL))
\r
13062 #define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL))
\r
13063 #define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL))
\r
13064 #define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL))
\r
13065 #define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL))
\r
13066 #define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL))
\r
13067 #define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL))
\r
13068 #define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL))
\r
13069 #define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL))
\r
13071 /* USB channel 0 registers */
\r
13072 #define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL))
\r
13073 #define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL))
\r
13074 #define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL))
\r
13075 #define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL))
\r
13076 #define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL))
\r
13077 #define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL))
\r
13078 #define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL))
\r
13079 #define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL))
\r
13080 #define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL))
\r
13081 #define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL))
\r
13082 #define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL))
\r
13083 #define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL))
\r
13084 #define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL))
\r
13085 #define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL))
\r
13086 #define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL))
\r
13087 #define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL))
\r
13088 #define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL))
\r
13089 #define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL))
\r
13090 #define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL))
\r
13091 #define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL))
\r
13092 #define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL))
\r
13093 #define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL))
\r
13094 #define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL))
\r
13095 #define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL))
\r
13096 #define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL))
\r
13097 #define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL))
\r
13098 #define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL))
\r
13099 #define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL))
\r
13100 #define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL))
\r
13101 #define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL))
\r
13102 #define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL))
\r
13103 #define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL))
\r
13104 #define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL))
\r
13105 #define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL))
\r
13106 #define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL))
\r
13107 #define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL))
\r
13108 #define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL))
\r
13109 #define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL))
\r
13110 #define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL))
\r
13111 #define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL))
\r
13112 #define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL))
\r
13113 #define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL))
\r
13114 #define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL))
\r
13115 #define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL))
\r
13116 #define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL))
\r
13117 #define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL))
\r
13118 #define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL))
\r
13119 #define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL))
\r
13120 #define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL))
\r
13121 #define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL))
\r
13122 #define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL))
\r
13123 #define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL))
\r
13124 #define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL))
\r
13125 #define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL))
\r
13126 #define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL))
\r
13127 #define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL))
\r
13128 #define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL))
\r
13129 #define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL))
\r
13130 #define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL))
\r
13131 #define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL))
\r
13132 #define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL))
\r
13133 #define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL))
\r
13134 #define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL))
\r
13135 #define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL))
\r
13136 #define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL))
\r
13137 #define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL))
\r
13138 #define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL))
\r
13139 #define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL))
\r
13140 #define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL))
\r
13141 #define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL))
\r
13142 #define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL))
\r
13143 #define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL))
\r
13144 #define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL))
\r
13145 #define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL))
\r
13146 #define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL))
\r
13147 #define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL))
\r
13148 #define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL))
\r
13149 #define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL))
\r
13150 #define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL))
\r
13151 #define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL))
\r
13152 #define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL))
\r
13153 #define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL))
\r
13154 #define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL))
\r
13155 #define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL))
\r
13156 #define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL))
\r
13157 #define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL))
\r
13158 #define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL))
\r
13159 #define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL))
\r
13160 #define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL))
\r
13161 #define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL))
\r
13162 #define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL))
\r
13163 #define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL))
\r
13164 #define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL))
\r
13165 #define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL))
\r
13166 #define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL))
\r
13167 #define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL))
\r
13168 #define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL))
\r
13169 #define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL))
\r
13170 #define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL))
\r
13171 #define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL))
\r
13172 #define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL))
\r
13173 #define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL))
\r
13174 #define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL))
\r
13175 #define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL))
\r
13176 #define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL))
\r
13177 #define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL))
\r
13178 #define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL))
\r
13179 #define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL))
\r
13180 #define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL))
\r
13181 #define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL))
\r
13182 #define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL))
\r
13183 #define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL))
\r
13184 #define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL))
\r
13185 #define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL))
\r
13186 #define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL))
\r
13187 #define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL))
\r
13188 #define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL))
\r
13189 #define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL))
\r
13190 #define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL))
\r
13191 #define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL))
\r
13192 #define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL))
\r
13193 #define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL))
\r
13194 #define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL))
\r
13195 #define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL))
\r
13196 #define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL))
\r
13197 #define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL))
\r
13198 #define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL))
\r
13199 #define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL))
\r
13200 #define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL))
\r
13201 #define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL))
\r
13202 #define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL))
\r
13203 #define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL))
\r
13204 #define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL))
\r
13205 #define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL))
\r
13206 #define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL))
\r
13207 #define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL))
\r
13208 #define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL))
\r
13209 #define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL))
\r
13210 #define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL))
\r
13211 #define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL))
\r
13212 #define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL))
\r
13213 #define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL))
\r
13214 #define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL))
\r
13215 #define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL))
\r
13216 #define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL))
\r
13217 #define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL))
\r
13218 #define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL))
\r
13219 #define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL))
\r
13220 #define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL))
\r
13221 #define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL))
\r
13222 #define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL))
\r
13223 #define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL))
\r
13224 #define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL))
\r
13225 #define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL))
\r
13226 #define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL))
\r
13227 #define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL))
\r
13228 #define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL))
\r
13229 #define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL))
\r
13230 #define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL))
\r
13231 #define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL))
\r
13232 #define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL))
\r
13233 #define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL))
\r
13234 #define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL))
\r
13235 #define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL))
\r
13236 #define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL))
\r
13237 #define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL))
\r
13238 #define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL))
\r
13239 #define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL))
\r
13240 #define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL))
\r
13241 #define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL))
\r
13242 #define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL))
\r
13243 #define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL))
\r
13244 #define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL))
\r
13245 #define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL))
\r
13246 #define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL))
\r
13247 #define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL))
\r
13248 #define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL))
\r
13249 #define bFM3_USB0_EP1C_PKS18 *((volatile unsigned int*)(0x42842520UL))
\r
13250 #define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL))
\r
13251 #define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL))
\r
13252 #define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL))
\r
13253 #define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL))
\r
13254 #define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL))
\r
13255 #define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL))
\r
13256 #define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL))
\r
13257 #define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL))
\r
13258 #define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL))
\r
13259 #define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL))
\r
13260 #define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL))
\r
13261 #define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL))
\r
13262 #define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL))
\r
13263 #define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL))
\r
13264 #define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL))
\r
13265 #define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL))
\r
13266 #define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL))
\r
13267 #define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL))
\r
13268 #define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL))
\r
13269 #define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL))
\r
13270 #define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL))
\r
13271 #define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL))
\r
13272 #define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL))
\r
13273 #define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL))
\r
13274 #define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL))
\r
13275 #define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL))
\r
13276 #define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL))
\r
13277 #define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL))
\r
13278 #define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL))
\r
13279 #define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL))
\r
13280 #define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL))
\r
13281 #define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL))
\r
13282 #define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL))
\r
13283 #define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL))
\r
13284 #define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL))
\r
13285 #define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL))
\r
13286 #define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL))
\r
13287 #define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL))
\r
13288 #define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL))
\r
13289 #define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL))
\r
13290 #define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL))
\r
13291 #define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL))
\r
13292 #define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL))
\r
13293 #define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL))
\r
13294 #define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL))
\r
13295 #define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL))
\r
13296 #define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL))
\r
13297 #define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL))
\r
13298 #define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL))
\r
13299 #define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL))
\r
13300 #define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL))
\r
13301 #define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL))
\r
13302 #define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL))
\r
13303 #define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL))
\r
13304 #define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL))
\r
13305 #define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL))
\r
13306 #define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL))
\r
13307 #define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL))
\r
13308 #define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL))
\r
13309 #define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL))
\r
13310 #define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL))
\r
13311 #define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL))
\r
13312 #define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL))
\r
13313 #define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL))
\r
13314 #define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL))
\r
13315 #define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL))
\r
13316 #define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL))
\r
13317 #define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL))
\r
13318 #define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL))
\r
13319 #define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL))
\r
13320 #define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL))
\r
13321 #define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL))
\r
13322 #define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL))
\r
13323 #define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL))
\r
13324 #define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL))
\r
13325 #define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL))
\r
13326 #define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL))
\r
13327 #define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL))
\r
13328 #define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL))
\r
13329 #define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL))
\r
13330 #define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL))
\r
13331 #define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL))
\r
13332 #define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL))
\r
13333 #define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL))
\r
13334 #define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL))
\r
13335 #define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL))
\r
13336 #define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL))
\r
13337 #define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL))
\r
13338 #define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL))
\r
13339 #define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL))
\r
13340 #define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL))
\r
13341 #define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL))
\r
13342 #define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL))
\r
13343 #define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL))
\r
13344 #define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL))
\r
13345 #define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL))
\r
13346 #define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL))
\r
13347 #define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL))
\r
13348 #define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL))
\r
13349 #define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL))
\r
13350 #define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL))
\r
13351 #define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL))
\r
13352 #define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL))
\r
13353 #define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL))
\r
13354 #define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL))
\r
13355 #define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL))
\r
13356 #define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL))
\r
13357 #define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL))
\r
13358 #define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL))
\r
13359 #define bFM3_USB0_EP1S_SIZE18 *((volatile unsigned int*)(0x428429A0UL))
\r
13360 #define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL))
\r
13361 #define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL))
\r
13362 #define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL))
\r
13363 #define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL))
\r
13364 #define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL))
\r
13365 #define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL))
\r
13366 #define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL))
\r
13367 #define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL))
\r
13368 #define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL))
\r
13369 #define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL))
\r
13370 #define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL))
\r
13371 #define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL))
\r
13372 #define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL))
\r
13373 #define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL))
\r
13374 #define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL))
\r
13375 #define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL))
\r
13376 #define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL))
\r
13377 #define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL))
\r
13378 #define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL))
\r
13379 #define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL))
\r
13380 #define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL))
\r
13381 #define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL))
\r
13382 #define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL))
\r
13383 #define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL))
\r
13384 #define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL))
\r
13385 #define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL))
\r
13386 #define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL))
\r
13387 #define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL))
\r
13388 #define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL))
\r
13389 #define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL))
\r
13390 #define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL))
\r
13391 #define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL))
\r
13392 #define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL))
\r
13393 #define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL))
\r
13394 #define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL))
\r
13395 #define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL))
\r
13396 #define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL))
\r
13397 #define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL))
\r
13398 #define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL))
\r
13399 #define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL))
\r
13400 #define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL))
\r
13401 #define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL))
\r
13402 #define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL))
\r
13403 #define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL))
\r
13404 #define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL))
\r
13405 #define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL))
\r
13406 #define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL))
\r
13407 #define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL))
\r
13408 #define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL))
\r
13409 #define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL))
\r
13410 #define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL))
\r
13411 #define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL))
\r
13412 #define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL))
\r
13413 #define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL))
\r
13414 #define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL))
\r
13415 #define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL))
\r
13416 #define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL))
\r
13417 #define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL))
\r
13419 /* DMA controller */
\r
13420 #define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL))
\r
13421 #define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL))
\r
13422 #define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL))
\r
13423 #define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL))
\r
13424 #define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL))
\r
13425 #define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL))
\r
13426 #define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL))
\r
13427 #define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL))
\r
13428 #define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL))
\r
13429 #define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL))
\r
13430 #define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL))
\r
13431 #define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL))
\r
13432 #define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL))
\r
13433 #define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL))
\r
13434 #define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL))
\r
13435 #define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL))
\r
13436 #define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL))
\r
13437 #define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL))
\r
13438 #define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL))
\r
13439 #define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL))
\r
13440 #define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL))
\r
13441 #define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL))
\r
13442 #define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL))
\r
13443 #define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL))
\r
13444 #define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL))
\r
13445 #define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL))
\r
13446 #define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL))
\r
13447 #define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL))
\r
13448 #define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL))
\r
13449 #define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL))
\r
13450 #define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL))
\r
13451 #define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL))
\r
13452 #define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL))
\r
13453 #define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL))
\r
13454 #define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL))
\r
13455 #define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL))
\r
13456 #define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL))
\r
13457 #define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL))
\r
13458 #define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL))
\r
13459 #define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL))
\r
13460 #define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL))
\r
13461 #define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL))
\r
13462 #define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL))
\r
13463 #define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL))
\r
13464 #define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL))
\r
13465 #define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL))
\r
13466 #define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL))
\r
13467 #define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL))
\r
13468 #define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL))
\r
13469 #define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL))
\r
13470 #define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL))
\r
13471 #define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL))
\r
13472 #define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL))
\r
13473 #define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL))
\r
13474 #define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL))
\r
13475 #define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL))
\r
13476 #define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL))
\r
13477 #define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL))
\r
13478 #define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL))
\r
13479 #define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL))
\r
13480 #define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL))
\r
13481 #define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL))
\r
13482 #define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL))
\r
13483 #define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL))
\r
13484 #define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL))
\r
13485 #define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL))
\r
13486 #define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL))
\r
13487 #define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL))
\r
13488 #define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL))
\r
13489 #define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL))
\r
13490 #define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL))
\r
13491 #define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL))
\r
13492 #define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL))
\r
13493 #define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL))
\r
13494 #define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL))
\r
13495 #define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL))
\r
13496 #define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL))
\r
13497 #define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL))
\r
13498 #define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL))
\r
13499 #define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL))
\r
13500 #define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL))
\r
13501 #define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL))
\r
13502 #define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL))
\r
13503 #define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL))
\r
13504 #define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL))
\r
13505 #define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL))
\r
13506 #define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL))
\r
13507 #define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL))
\r
13508 #define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL))
\r
13509 #define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL))
\r
13510 #define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL))
\r
13511 #define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL))
\r
13512 #define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL))
\r
13513 #define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL))
\r
13514 #define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL))
\r
13515 #define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL))
\r
13516 #define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL))
\r
13517 #define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL))
\r
13518 #define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL))
\r
13519 #define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL))
\r
13520 #define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL))
\r
13521 #define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL))
\r
13522 #define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL))
\r
13523 #define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL))
\r
13524 #define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL))
\r
13525 #define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL))
\r
13526 #define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL))
\r
13527 #define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL))
\r
13528 #define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL))
\r
13529 #define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL))
\r
13530 #define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL))
\r
13531 #define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL))
\r
13532 #define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL))
\r
13533 #define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL))
\r
13534 #define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL))
\r
13535 #define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL))
\r
13536 #define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL))
\r
13537 #define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL))
\r
13538 #define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL))
\r
13539 #define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL))
\r
13540 #define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL))
\r
13541 #define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL))
\r
13542 #define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL))
\r
13543 #define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL))
\r
13544 #define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL))
\r
13545 #define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL))
\r
13546 #define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL))
\r
13547 #define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL))
\r
13548 #define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL))
\r
13549 #define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL))
\r
13550 #define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL))
\r
13551 #define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL))
\r
13552 #define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL))
\r
13553 #define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL))
\r
13554 #define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL))
\r
13555 #define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL))
\r
13556 #define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL))
\r
13557 #define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL))
\r
13558 #define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL))
\r
13559 #define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL))
\r
13560 #define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL))
\r
13561 #define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL))
\r
13562 #define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL))
\r
13563 #define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL))
\r
13564 #define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL))
\r
13565 #define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL))
\r
13566 #define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL))
\r
13567 #define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL))
\r
13568 #define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL))
\r
13569 #define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL))
\r
13570 #define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL))
\r
13571 #define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL))
\r
13572 #define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL))
\r
13573 #define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL))
\r
13574 #define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL))
\r
13575 #define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL))
\r
13576 #define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL))
\r
13577 #define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL))
\r
13578 #define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL))
\r
13579 #define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL))
\r
13580 #define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL))
\r
13581 #define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL))
\r
13582 #define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL))
\r
13583 #define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL))
\r
13584 #define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL))
\r
13585 #define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL))
\r
13586 #define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL))
\r
13587 #define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL))
\r
13588 #define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL))
\r
13589 #define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL))
\r
13590 #define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL))
\r
13591 #define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL))
\r
13592 #define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL))
\r
13593 #define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL))
\r
13594 #define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL))
\r
13595 #define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL))
\r
13596 #define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL))
\r
13597 #define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL))
\r
13598 #define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL))
\r
13599 #define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL))
\r
13600 #define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL))
\r
13601 #define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL))
\r
13602 #define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL))
\r
13603 #define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL))
\r
13604 #define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL))
\r
13605 #define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL))
\r
13606 #define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL))
\r
13607 #define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL))
\r
13608 #define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL))
\r
13609 #define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL))
\r
13610 #define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL))
\r
13611 #define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL))
\r
13612 #define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL))
\r
13613 #define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL))
\r
13614 #define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL))
\r
13615 #define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL))
\r
13616 #define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL))
\r
13617 #define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL))
\r
13618 #define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL))
\r
13619 #define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL))
\r
13620 #define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL))
\r
13621 #define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL))
\r
13622 #define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL))
\r
13623 #define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL))
\r
13624 #define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL))
\r
13625 #define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL))
\r
13626 #define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL))
\r
13627 #define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL))
\r
13628 #define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL))
\r
13629 #define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL))
\r
13630 #define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL))
\r
13631 #define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL))
\r
13632 #define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL))
\r
13633 #define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL))
\r
13634 #define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL))
\r
13635 #define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL))
\r
13636 #define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL))
\r
13637 #define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL))
\r
13638 #define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL))
\r
13639 #define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL))
\r
13640 #define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL))
\r
13641 #define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL))
\r
13642 #define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL))
\r
13643 #define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL))
\r
13644 #define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL))
\r
13645 #define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL))
\r
13646 #define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL))
\r
13647 #define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL))
\r
13648 #define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL))
\r
13649 #define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL))
\r
13650 #define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL))
\r
13651 #define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL))
\r
13652 #define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL))
\r
13653 #define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL))
\r
13654 #define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL))
\r
13655 #define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL))
\r
13656 #define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL))
\r
13657 #define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL))
\r
13658 #define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL))
\r
13659 #define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL))
\r
13660 #define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL))
\r
13661 #define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL))
\r
13662 #define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL))
\r
13663 #define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL))
\r
13664 #define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL))
\r
13665 #define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL))
\r
13666 #define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL))
\r
13667 #define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL))
\r
13668 #define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL))
\r
13669 #define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL))
\r
13670 #define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL))
\r
13671 #define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL))
\r
13672 #define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL))
\r
13673 #define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL))
\r
13674 #define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL))
\r
13675 #define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL))
\r
13676 #define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL))
\r
13677 #define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL))
\r
13678 #define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL))
\r
13679 #define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL))
\r
13680 #define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL))
\r
13681 #define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL))
\r
13682 #define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL))
\r
13683 #define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL))
\r
13684 #define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL))
\r
13685 #define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL))
\r
13686 #define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL))
\r
13687 #define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL))
\r
13688 #define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL))
\r
13689 #define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL))
\r
13690 #define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL))
\r
13691 #define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL))
\r
13692 #define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL))
\r
13693 #define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL))
\r
13694 #define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL))
\r
13695 #define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL))
\r
13696 #define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL))
\r
13697 #define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL))
\r
13698 #define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL))
\r
13699 #define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL))
\r
13700 #define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL))
\r
13701 #define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL))
\r
13702 #define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL))
\r
13703 #define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL))
\r
13704 #define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL))
\r
13705 #define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL))
\r
13706 #define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL))
\r
13707 #define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL))
\r
13708 #define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL))
\r
13709 #define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL))
\r
13710 #define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL))
\r
13711 #define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL))
\r
13712 #define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL))
\r
13713 #define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL))
\r
13714 #define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL))
\r
13715 #define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL))
\r
13716 #define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL))
\r
13717 #define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL))
\r
13718 #define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL))
\r
13719 #define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL))
\r
13720 #define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL))
\r
13721 #define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL))
\r
13722 #define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL))
\r
13723 #define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL))
\r
13724 #define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL))
\r
13725 #define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL))
\r
13726 #define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL))
\r
13727 #define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL))
\r
13728 #define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL))
\r
13729 #define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL))
\r
13730 #define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL))
\r
13731 #define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL))
\r
13732 #define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL))
\r
13733 #define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL))
\r
13734 #define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL))
\r
13735 #define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL))
\r
13736 #define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL))
\r
13737 #define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL))
\r
13738 #define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL))
\r
13739 #define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL))
\r
13740 #define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL))
\r
13741 #define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL))
\r
13742 #define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL))
\r
13743 #define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL))
\r
13744 #define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL))
\r
13745 #define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL))
\r
13746 #define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL))
\r
13747 #define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL))
\r
13748 #define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL))
\r
13749 #define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL))
\r
13750 #define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL))
\r
13751 #define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL))
\r
13752 #define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL))
\r
13753 #define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL))
\r
13754 #define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL))
\r
13755 #define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL))
\r
13756 #define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL))
\r
13757 #define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL))
\r
13758 #define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL))
\r
13759 #define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL))
\r
13760 #define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL))
\r
13761 #define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL))
\r
13762 #define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL))
\r
13763 #define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL))
\r
13764 #define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL))
\r
13765 #define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL))
\r
13766 #define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL))
\r
13767 #define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL))
\r
13768 #define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL))
\r
13769 #define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL))
\r
13770 #define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL))
\r
13771 #define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL))
\r
13772 #define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL))
\r
13773 #define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL))
\r
13774 #define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL))
\r
13775 #define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL))
\r
13776 #define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL))
\r
13777 #define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL))
\r
13778 #define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL))
\r
13780 #ifdef __cplusplus
\r
13784 #endif /* _MB9AF314L_H_ */
\r
projects / freertos / blob