1 /************************************************************************/
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2 /* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
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4 /* The following software deliverable is intended for and must only be */
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5 /* used for reference and in an evaluation laboratory environment. */
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6 /* It is provided on an as-is basis without charge and is subject to */
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8 /* It is the user's obligation to fully test the software in its */
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9 /* environment and to ensure proper functionality, qualification and */
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10 /* compliance with component specifications. */
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12 /* In the event the software deliverable includes the use of open */
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13 /* source components, the provisions of the governing open source */
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14 /* license agreement shall apply with respect to such software */
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16 /* FSEU does not warrant that the deliverables do not infringe any */
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17 /* third party intellectual property right (IPR). In the event that */
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18 /* the deliverables infringe a third party IPR it is the sole */
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19 /* responsibility of the customer to obtain necessary licenses to */
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20 /* continue the usage of the deliverable. */
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22 /* To the maximum extent permitted by applicable law FSEU disclaims all */
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23 /* warranties, whether express or implied, in particular, but not */
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24 /* limited to, warranties of merchantability and fitness for a */
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25 /* particular purpose for which the deliverable is not designated. */
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27 /* To the maximum extent permitted by applicable law, FSEU's liability */
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28 /* is restricted to intentional misconduct and gross negligence. */
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29 /* FSEU is not liable for consequential damages. */
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32 /************************************************************************/
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35 #include "mb9bf506n.h"
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37 /*--------------------- Clock Configuration ----------------------------------*/
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39 // <e0> Clock Configuration
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40 // <h> System Clock Configuration
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41 // <o1.1> SCM_CTL.MOSCE: Main clock oscillation enable
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42 // <o2.0..3> CSW_TMR.MOWT: Main clock stabilization wait time
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43 // <i> Default: ~ 500 ns
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60 // <o1.3> SCM_CTL.SOSCE: Sub clock oscillation enable
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61 // <o2.4..6> CSW_TMR.SOWT: SOWT: Sub clock stabilization wait time
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62 // <i> Default: ~ 31.19 ms
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71 // <e1.4> SCM_CTL.PLLE: PLL oscillation enable
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72 // <i> fPLLO Max = 120MHz, CLKPLL Min = 60MHz
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73 // <i> CLKPLL = (CLKMO / PLLK) * PLLN
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74 // <o4.4..7> PLL_CTL1.PLLK: PLL input clock frequency division
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76 // <o5.0..4> PLL_CTL1.PLLN: PLL feedback frequency division
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78 // <o4.0..3> PLL_CTL1.PLLM: PLL VCO clock frequency division
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80 // <o3.0..2> PSW_TMR.POWT: PLL clock stabilization wait time
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81 // <i> Default: ~ 128 us
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91 // <o1.5..7> SCM_CTL.RCS: Master clock switch control
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92 // <i> Default: Master Clock = CLKHC
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93 // <0=> Master Clock = CLKHC
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94 // <1=> Master Clock = CLKMO
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95 // <2=> Master Clock = CLKPLL
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96 // <4=> Master Clock = CLKLC
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97 // <5=> Master Clock = CLKSO
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100 // <h> Base Clock Prescaler
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101 // <o6.0..2> BSC_PSR.BSR: Base clock frequency division
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102 // <i> Default: HCLK = Master Clock
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103 // <i> HCLK Max = 80MHz
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104 // <0=> HCLK = Master Clock
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105 // <1=> HCLK = Master Clock / 2
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106 // <2=> HCLK = Master Clock / 3
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107 // <3=> HCLK = Master Clock / 4
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108 // <4=> HCLK = Master Clock / 6
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109 // <5=> HCLK = Master Clock / 8
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110 // <6=> HCLK = Master Clock / 16
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113 // <h> APB0 Prescaler
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114 // <o7.0..1> APBC0_PSR.APBC0: APB0 bus clock frequency division
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115 // <i> PCLK0 Max = 40MHz
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116 // <i> Default: PCLK0 = HCLK
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117 // <0=> PCLK0 = HCLK
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118 // <1=> PCLK0 = HCLK / 2
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119 // <2=> PCLK0 = HCLK / 4
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120 // <3=> PCLK0 = HCLK / 8
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123 // <h> APB1 Prescaler
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124 // <o8.0..1> APBC1_PSR.APBC1: APB1 bus clock frequency
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125 // <i> PCLK1 Max = 40MHz
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126 // <i> Default: PCLK1 = HCLK
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127 // <0=> PCLK1 = HCLK
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128 // <1=> PCLK1 = HCLK / 2
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129 // <2=> PCLK1 = HCLK / 4
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130 // <3=> PCLK1 = HCLK / 8
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131 // <o8.7> APBC1_PSR.APBC1EN: APB1 clock enable
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134 // <h> APB2 Prescaler
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135 // <o9.0..1> APBC2_PSR.APBC2: APB2 bus clock frequency
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136 // <i> PCLK2 Max = 40MHz
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137 // <i> Default: PCLK2 = HCLK
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138 // <0=> PCLK2 = HCLK
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139 // <1=> PCLK2 = HCLK / 2
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140 // <2=> PCLK2 = HCLK / 4
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141 // <3=> PCLK2 = HCLK / 8
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142 // <o9.7> APBC2_PSR.APBC2EN: APB2 clock enable
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145 // <h> SW Watchdog Clock Prescaler
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146 // <o10.0..1>SWC_PSR.SWDS: Software watchdog clock frequency division
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147 // <i> Default: SWDGOGCLK = PCLK0
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148 // <0=> SWDGOGCLK = PCLK0
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149 // <1=> SWDGOGCLK = PCLK0 / 2
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150 // <2=> SWDGOGCLK = PCLK0 / 4
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151 // <3=> SWDGOGCLK = PCLK0 / 8
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154 // <h> Trace Clock Prescaler
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155 // <o11.0> TTC_PSR.TTC: Trace clock frequency division
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156 // <i> Default: TPIUCLK = HCLK
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157 // <0=> TPIUCLK = HCLK
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158 // <1=> TPIUCLK = HCLK / 2
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163 #define CLOCK_SETUP 1
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164 #define SCM_CTL_Val 0x00000052
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165 #define CSW_TMR_Val 0x0000005C
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166 #define PSW_TMR_Val 0x00000000
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167 #define PLL_CTL1_Val 0x00000000
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168 #define PLL_CTL2_Val 0x00000013
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169 #define BSC_PSR_Val 0x00000000
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170 #define APBC0_PSR_Val 0x00000001
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171 #define APBC1_PSR_Val 0x00000082
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172 #define APBC2_PSR_Val 0x00000081
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173 #define SWC_PSR_Val 0x00000003
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174 #define TTC_PSR_Val 0x00000000
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176 /*--------------------- WatchDog Configuration -------------------------------*/
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178 // <o0.0> HW Watchdog disable
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180 #define HWWD_DISABLE 0x00000001
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183 //-------- <<< end of configuration section >>> ------------------------------
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186 /*----------------------------------------------------------------------------
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187 Check the register settings
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188 *----------------------------------------------------------------------------*/
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189 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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190 #define CHECK_RSVD(val, mask) (val & mask)
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192 /* Clock Configuration -------------------------------------------------------*/
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193 #if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
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194 #error "SCM_CTL: Invalid values of reserved bits!"
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197 #if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
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198 #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
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201 #if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
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202 #error "CSW_TMR: Invalid values of reserved bits!"
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205 #if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
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206 #if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
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207 #error "PSW_TMR: Invalid values of reserved bits!"
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210 #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
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211 #error "PLL_CTL1: Invalid values of reserved bits!"
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214 #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000001F))
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215 #error "PLL_CTL2: Invalid values of reserved bits!"
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219 #if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
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220 #error "BSC_PSR: Invalid values of reserved bits!"
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223 #if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
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224 #error "APBC0_PSR: Invalid values of reserved bits!"
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227 #if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
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228 #error "APBC1_PSR: Invalid values of reserved bits!"
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231 #if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
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232 #error "APBC2_PSR: Invalid values of reserved bits!"
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235 #if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
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236 #error "SWC_PSR: Invalid values of reserved bits!"
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239 #if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
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240 #error "TTC_PSR: Invalid values of reserved bits!"
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244 /*----------------------------------------------------------------------------
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246 *----------------------------------------------------------------------------*/
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248 /*----------------------------------------------------------------------------
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250 *----------------------------------------------------------------------------*/
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251 #define __CLKMO ( 4000000UL) /* External 4MHz Crystal */
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252 #define __CLKSO ( 32768UL) /* External 32KHz Crystal */
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253 #define __CLKHC ( 4000000UL) /* Internal 4MHz RC Oscillator */
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254 #define __CLKLC ( 100000UL) /* Internal 100KHz RC Oscillator */
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257 /* CLKPLL = (CLKMO / PLLK) * PLLN */
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258 #define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
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259 #define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1)
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260 #define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
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262 /* Determine core clock frequency according to settings */
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263 #if (((SCM_CTL_Val >> 5) & 0x07) == 0)
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264 #define __MASTERCLK (__CLKHC)
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265 #elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
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266 #define __MASTERCLK (__CLKMO)
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267 #elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
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268 #define __MASTERCLK (__PLLCLK)
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269 #elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
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270 #define __MASTERCLK (__CLKLC)
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271 #elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
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272 #define __MASTERCLK (__CLKSO)
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274 #define __MASTERCLK (0UL)
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277 #if ((BSC_PSR_Val & 0x07) == 0)
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278 #define __HCLK (__MASTERCLK / 1)
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279 #elif ((BSC_PSR_Val & 0x07) == 1)
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280 #define __HCLK (__MASTERCLK / 2)
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281 #elif ((BSC_PSR_Val & 0x07) == 2)
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282 #define __HCLK (__MASTERCLK / 3)
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283 #elif ((BSC_PSR_Val & 0x07) == 3)
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284 #define __HCLK (__MASTERCLK / 4)
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285 #elif ((BSC_PSR_Val & 0x07) == 4)
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286 #define __HCLK (__MASTERCLK / 6)
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287 #elif ((BSC_PSR_Val & 0x07) == 5)
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288 #define __HCLK (__MASTERCLK / 8)
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289 #elif ((BSC_PSR_Val & 0x07) == 6)
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290 #define __HCLK (__MASTERCLK /16)
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292 #define __HCLK (0UL)
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297 /*----------------------------------------------------------------------------
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298 Clock Variable definitions
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299 *----------------------------------------------------------------------------*/
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300 uint32_t SystemCoreClock = __HCLK; /*!< System Clock Frequency (Core Clock)*/
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304 * Retrieve the system core clock
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309 * @brief retrieve system core clock from register settings.
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311 void SystemCoreClockUpdate (void) {
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312 uint32_t masterClk;
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313 uint32_t u32RegisterRead;
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315 switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
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316 case 0: /* internal High-speed Cr osc. */
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317 masterClk = __CLKHC;
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320 case 1: /* external main osc. */
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321 masterClk = __CLKMO;
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324 case 2: /* PLL clock */
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325 u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
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326 masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
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329 case 4: /* internal Low-speed CR osc. */
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330 masterClk = __CLKLC;
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333 case 5: /* external Sub osc. */
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334 masterClk = __CLKSO;
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342 switch (FM3_CRG->BSC_PSR & 0x07) {
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344 SystemCoreClock = masterClk;
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348 SystemCoreClock = masterClk / 2;
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352 SystemCoreClock = masterClk / 3;
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356 SystemCoreClock = masterClk / 4;
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360 SystemCoreClock = masterClk / 6;
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364 SystemCoreClock = masterClk /8;
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368 SystemCoreClock = masterClk /16;
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372 SystemCoreClock = 0Ul;
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379 * Set CR Trimming Data
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384 * @brief Update CR trimming with Flash
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387 static void CrtrimSet(void)
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389 /* CR Trimming Data */
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390 if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
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392 /* UnLock (MCR_FTRM) */
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393 FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
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395 FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
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396 /* Lock (MCR_FTRM) */
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397 FM3_CRTRIM->MCR_RLR = 0x00000000;
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402 * Initialize the system
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407 * @brief Setup the microcontroller system.
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408 * Initialize the System.
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410 void SystemInit (void) {
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412 uint32_t u32RegisterRead;
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414 #if (HWWD_DISABLE) /* HW Watchdog Disable */
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415 FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
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416 FM3_HWWDT->WDG_LCK = 0xE5331AAE;
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417 FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
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420 #if (CLOCK_SETUP) /* Clock Setup */
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421 FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
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422 FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
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423 FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
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424 FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
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425 FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
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426 FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
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428 FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
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429 if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
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430 FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
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431 while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
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433 if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
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434 FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
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435 while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
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438 FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
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439 FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
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440 FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
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441 if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
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442 FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
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443 while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
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446 FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
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449 u32RegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
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450 }while ((FM3_CRG->SCM_STR & 0xE0) != u32RegisterRead);
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