2 ******************************************************************************
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3 * @file stm32f10x_tim.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the TIM firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_tim.h"
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23 #include "stm32f10x_rcc.h"
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25 /** @addtogroup STM32F10x_StdPeriph_Driver
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30 * @brief TIM driver modules
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34 /** @defgroup TIM_Private_TypesDefinitions
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42 /** @defgroup TIM_Private_Defines
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46 /* ---------------------- TIM registers bit mask ------------------------ */
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47 #define SMCR_ETR_Mask ((uint16_t)0x00FF)
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48 #define CCMR_Offset ((uint16_t)0x0018)
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49 #define CCER_CCE_Set ((uint16_t)0x0001)
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50 #define CCER_CCNE_Set ((uint16_t)0x0004)
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56 /** @defgroup TIM_Private_Macros
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64 /** @defgroup TIM_Private_Variables
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72 /** @defgroup TIM_Private_FunctionPrototypes
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76 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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77 uint16_t TIM_ICFilter);
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78 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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79 uint16_t TIM_ICFilter);
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80 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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81 uint16_t TIM_ICFilter);
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82 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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83 uint16_t TIM_ICFilter);
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88 /** @defgroup TIM_Private_Macros
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96 /** @defgroup TIM_Private_Variables
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104 /** @defgroup TIM_Private_FunctionPrototypes
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112 /** @defgroup TIM_Private_Functions
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117 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
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118 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
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121 void TIM_DeInit(TIM_TypeDef* TIMx)
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123 /* Check the parameters */
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124 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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128 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
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129 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
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131 else if (TIMx == TIM2)
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133 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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134 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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136 else if (TIMx == TIM3)
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138 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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139 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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141 else if (TIMx == TIM4)
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143 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
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144 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
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146 else if (TIMx == TIM5)
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148 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
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149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
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151 else if (TIMx == TIM6)
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153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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154 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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156 else if (TIMx == TIM7)
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158 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
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159 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
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161 else if (TIMx == TIM8)
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163 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
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164 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
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166 else if (TIMx == TIM9)
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168 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
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169 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
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171 else if (TIMx == TIM10)
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173 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
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174 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
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176 else if (TIMx == TIM11)
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178 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
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179 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
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181 else if (TIMx == TIM12)
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183 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
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184 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
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186 else if (TIMx == TIM13)
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188 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
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189 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
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191 else if (TIMx == TIM14)
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193 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
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194 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
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196 else if (TIMx == TIM15)
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198 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
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199 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
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201 else if (TIMx == TIM16)
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203 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
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204 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
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210 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
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211 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
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217 * @brief Initializes the TIMx Time Base Unit peripheral according to
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218 * the specified parameters in the TIM_TimeBaseInitStruct.
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219 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
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220 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
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221 * structure that contains the configuration information for the specified TIM peripheral.
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224 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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226 uint16_t tmpcr1 = 0;
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228 /* Check the parameters */
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229 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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230 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
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231 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
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233 tmpcr1 = TIMx->CR1;
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235 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
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236 (TIMx == TIM4) || (TIMx == TIM5))
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238 /* Select the Counter Mode */
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239 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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240 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
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243 if((TIMx != TIM6) && (TIMx != TIM7))
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245 /* Set the clock division */
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246 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
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247 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
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250 TIMx->CR1 = tmpcr1;
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252 /* Set the Autoreload value */
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253 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
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255 /* Set the Prescaler value */
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256 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
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258 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
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260 /* Set the Repetition Counter value */
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261 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
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264 /* Generate an update event to reload the Prescaler and the Repetition counter
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265 values immediately */
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266 TIMx->EGR = TIM_PSCReloadMode_Immediate;
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270 * @brief Initializes the TIMx Channel1 according to the specified
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271 * parameters in the TIM_OCInitStruct.
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272 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
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273 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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274 * that contains the configuration information for the specified TIM peripheral.
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277 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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279 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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281 /* Check the parameters */
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282 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
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283 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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284 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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285 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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286 /* Disable the Channel 1: Reset the CC1E Bit */
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287 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
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288 /* Get the TIMx CCER register value */
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289 tmpccer = TIMx->CCER;
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290 /* Get the TIMx CR2 register value */
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291 tmpcr2 = TIMx->CR2;
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293 /* Get the TIMx CCMR1 register value */
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294 tmpccmrx = TIMx->CCMR1;
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296 /* Reset the Output Compare Mode Bits */
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297 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
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298 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
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300 /* Select the Output Compare Mode */
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301 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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303 /* Reset the Output Polarity level */
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304 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
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305 /* Set the Output Compare Polarity */
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306 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
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308 /* Set the Output State */
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309 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
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311 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
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312 (TIMx == TIM16)|| (TIMx == TIM17))
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314 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
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315 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
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316 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
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317 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
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319 /* Reset the Output N Polarity level */
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320 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
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321 /* Set the Output N Polarity */
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322 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
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324 /* Reset the Output N State */
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325 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
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326 /* Set the Output N State */
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327 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
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329 /* Reset the Ouput Compare and Output Compare N IDLE State */
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330 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
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331 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
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333 /* Set the Output Idle state */
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334 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
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335 /* Set the Output N Idle state */
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336 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
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338 /* Write to TIMx CR2 */
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339 TIMx->CR2 = tmpcr2;
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341 /* Write to TIMx CCMR1 */
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342 TIMx->CCMR1 = tmpccmrx;
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344 /* Set the Capture Compare Register value */
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345 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
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347 /* Write to TIMx CCER */
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348 TIMx->CCER = tmpccer;
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352 * @brief Initializes the TIMx Channel2 according to the specified
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353 * parameters in the TIM_OCInitStruct.
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354 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
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355 * the TIM peripheral.
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356 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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357 * that contains the configuration information for the specified TIM peripheral.
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360 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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362 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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364 /* Check the parameters */
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365 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
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366 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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367 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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368 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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369 /* Disable the Channel 2: Reset the CC2E Bit */
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370 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
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372 /* Get the TIMx CCER register value */
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373 tmpccer = TIMx->CCER;
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374 /* Get the TIMx CR2 register value */
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375 tmpcr2 = TIMx->CR2;
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377 /* Get the TIMx CCMR1 register value */
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378 tmpccmrx = TIMx->CCMR1;
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380 /* Reset the Output Compare mode and Capture/Compare selection Bits */
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381 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
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382 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
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384 /* Select the Output Compare Mode */
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385 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
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387 /* Reset the Output Polarity level */
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388 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
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389 /* Set the Output Compare Polarity */
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390 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
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392 /* Set the Output State */
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393 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
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395 if((TIMx == TIM1) || (TIMx == TIM8))
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397 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
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398 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
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399 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
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400 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
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402 /* Reset the Output N Polarity level */
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403 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
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404 /* Set the Output N Polarity */
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405 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
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407 /* Reset the Output N State */
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408 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
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409 /* Set the Output N State */
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410 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
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412 /* Reset the Ouput Compare and Output Compare N IDLE State */
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413 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
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414 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
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416 /* Set the Output Idle state */
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417 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
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418 /* Set the Output N Idle state */
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419 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
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421 /* Write to TIMx CR2 */
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422 TIMx->CR2 = tmpcr2;
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424 /* Write to TIMx CCMR1 */
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425 TIMx->CCMR1 = tmpccmrx;
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427 /* Set the Capture Compare Register value */
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428 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
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430 /* Write to TIMx CCER */
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431 TIMx->CCER = tmpccer;
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435 * @brief Initializes the TIMx Channel3 according to the specified
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436 * parameters in the TIM_OCInitStruct.
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437 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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438 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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439 * that contains the configuration information for the specified TIM peripheral.
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442 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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444 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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446 /* Check the parameters */
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447 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
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448 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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449 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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450 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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451 /* Disable the Channel 2: Reset the CC2E Bit */
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452 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
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454 /* Get the TIMx CCER register value */
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455 tmpccer = TIMx->CCER;
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456 /* Get the TIMx CR2 register value */
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457 tmpcr2 = TIMx->CR2;
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459 /* Get the TIMx CCMR2 register value */
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460 tmpccmrx = TIMx->CCMR2;
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462 /* Reset the Output Compare mode and Capture/Compare selection Bits */
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463 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
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464 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
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465 /* Select the Output Compare Mode */
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466 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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468 /* Reset the Output Polarity level */
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469 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
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470 /* Set the Output Compare Polarity */
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471 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
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473 /* Set the Output State */
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474 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
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476 if((TIMx == TIM1) || (TIMx == TIM8))
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478 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
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479 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
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480 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
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481 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
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483 /* Reset the Output N Polarity level */
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484 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
\r
485 /* Set the Output N Polarity */
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486 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
\r
487 /* Reset the Output N State */
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488 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
\r
490 /* Set the Output N State */
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491 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
\r
492 /* Reset the Ouput Compare and Output Compare N IDLE State */
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493 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
\r
494 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
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495 /* Set the Output Idle state */
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496 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
\r
497 /* Set the Output N Idle state */
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498 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
\r
500 /* Write to TIMx CR2 */
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501 TIMx->CR2 = tmpcr2;
\r
503 /* Write to TIMx CCMR2 */
\r
504 TIMx->CCMR2 = tmpccmrx;
\r
506 /* Set the Capture Compare Register value */
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507 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
\r
509 /* Write to TIMx CCER */
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510 TIMx->CCER = tmpccer;
\r
514 * @brief Initializes the TIMx Channel4 according to the specified
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515 * parameters in the TIM_OCInitStruct.
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516 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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517 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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518 * that contains the configuration information for the specified TIM peripheral.
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521 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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523 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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525 /* Check the parameters */
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526 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
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527 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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528 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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529 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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530 /* Disable the Channel 2: Reset the CC4E Bit */
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531 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
\r
533 /* Get the TIMx CCER register value */
\r
534 tmpccer = TIMx->CCER;
\r
535 /* Get the TIMx CR2 register value */
\r
536 tmpcr2 = TIMx->CR2;
\r
538 /* Get the TIMx CCMR2 register value */
\r
539 tmpccmrx = TIMx->CCMR2;
\r
541 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
542 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
\r
543 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
\r
545 /* Select the Output Compare Mode */
\r
546 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\r
548 /* Reset the Output Polarity level */
\r
549 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
\r
550 /* Set the Output Compare Polarity */
\r
551 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
\r
553 /* Set the Output State */
\r
554 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
\r
556 if((TIMx == TIM1) || (TIMx == TIM8))
\r
558 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
\r
559 /* Reset the Ouput Compare IDLE State */
\r
560 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
\r
561 /* Set the Output Idle state */
\r
562 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
\r
564 /* Write to TIMx CR2 */
\r
565 TIMx->CR2 = tmpcr2;
\r
567 /* Write to TIMx CCMR2 */
\r
568 TIMx->CCMR2 = tmpccmrx;
\r
570 /* Set the Capture Compare Register value */
\r
571 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
\r
573 /* Write to TIMx CCER */
\r
574 TIMx->CCER = tmpccer;
\r
578 * @brief Initializes the TIM peripheral according to the specified
\r
579 * parameters in the TIM_ICInitStruct.
\r
580 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
581 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
582 * that contains the configuration information for the specified TIM peripheral.
\r
585 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
587 /* Check the parameters */
\r
588 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
\r
589 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
\r
590 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
\r
591 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
\r
593 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
\r
594 (TIMx == TIM4) ||(TIMx == TIM5))
\r
596 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
\r
600 assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
\r
602 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
604 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
605 /* TI1 Configuration */
\r
606 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
607 TIM_ICInitStruct->TIM_ICSelection,
\r
608 TIM_ICInitStruct->TIM_ICFilter);
\r
609 /* Set the Input Capture Prescaler value */
\r
610 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
612 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
\r
614 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
615 /* TI2 Configuration */
\r
616 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
617 TIM_ICInitStruct->TIM_ICSelection,
\r
618 TIM_ICInitStruct->TIM_ICFilter);
\r
619 /* Set the Input Capture Prescaler value */
\r
620 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
622 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
\r
624 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
625 /* TI3 Configuration */
\r
626 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
627 TIM_ICInitStruct->TIM_ICSelection,
\r
628 TIM_ICInitStruct->TIM_ICFilter);
\r
629 /* Set the Input Capture Prescaler value */
\r
630 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
634 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
635 /* TI4 Configuration */
\r
636 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
637 TIM_ICInitStruct->TIM_ICSelection,
\r
638 TIM_ICInitStruct->TIM_ICFilter);
\r
639 /* Set the Input Capture Prescaler value */
\r
640 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
645 * @brief Configures the TIM peripheral according to the specified
\r
646 * parameters in the TIM_ICInitStruct to measure an external PWM signal.
\r
647 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
648 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
649 * that contains the configuration information for the specified TIM peripheral.
\r
652 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
654 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
\r
655 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
\r
656 /* Check the parameters */
\r
657 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
658 /* Select the Opposite Input Polarity */
\r
659 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
\r
661 icoppositepolarity = TIM_ICPolarity_Falling;
\r
665 icoppositepolarity = TIM_ICPolarity_Rising;
\r
667 /* Select the Opposite Input */
\r
668 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
\r
670 icoppositeselection = TIM_ICSelection_IndirectTI;
\r
674 icoppositeselection = TIM_ICSelection_DirectTI;
\r
676 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
678 /* TI1 Configuration */
\r
679 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
680 TIM_ICInitStruct->TIM_ICFilter);
\r
681 /* Set the Input Capture Prescaler value */
\r
682 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
683 /* TI2 Configuration */
\r
684 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
685 /* Set the Input Capture Prescaler value */
\r
686 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
690 /* TI2 Configuration */
\r
691 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
692 TIM_ICInitStruct->TIM_ICFilter);
\r
693 /* Set the Input Capture Prescaler value */
\r
694 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
695 /* TI1 Configuration */
\r
696 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
697 /* Set the Input Capture Prescaler value */
\r
698 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
703 * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
\r
704 * the OSSR State and the AOE(automatic output enable).
\r
705 * @param TIMx: where x can be 1 or 8 to select the TIM
\r
706 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
\r
707 * contains the BDTR Register configuration information for the TIM peripheral.
\r
710 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
\r
712 /* Check the parameters */
\r
713 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
714 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
\r
715 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
\r
716 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
\r
717 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
\r
718 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
\r
719 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
\r
720 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
\r
721 the OSSI State, the dead time value and the Automatic Output Enable Bit */
\r
722 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
\r
723 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
\r
724 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
\r
725 TIM_BDTRInitStruct->TIM_AutomaticOutput;
\r
729 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
\r
730 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
\r
731 * structure which will be initialized.
\r
734 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
\r
736 /* Set the default configuration */
\r
737 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
\r
738 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
\r
739 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
\r
740 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
\r
741 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
\r
745 * @brief Fills each TIM_OCInitStruct member with its default value.
\r
746 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
\r
750 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
752 /* Set the default configuration */
\r
753 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
\r
754 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
\r
755 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
\r
756 TIM_OCInitStruct->TIM_Pulse = 0x0000;
\r
757 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
\r
758 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
\r
759 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
\r
760 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
\r
764 * @brief Fills each TIM_ICInitStruct member with its default value.
\r
765 * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
\r
769 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
771 /* Set the default configuration */
\r
772 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
\r
773 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
\r
774 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
\r
775 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
\r
776 TIM_ICInitStruct->TIM_ICFilter = 0x00;
\r
780 * @brief Fills each TIM_BDTRInitStruct member with its default value.
\r
781 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
\r
782 * will be initialized.
\r
785 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
\r
787 /* Set the default configuration */
\r
788 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
\r
789 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
\r
790 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
\r
791 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
\r
792 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
\r
793 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
\r
794 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
\r
798 * @brief Enables or disables the specified TIM peripheral.
\r
799 * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
\r
800 * @param NewState: new state of the TIMx peripheral.
\r
801 * This parameter can be: ENABLE or DISABLE.
\r
804 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
806 /* Check the parameters */
\r
807 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
808 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
810 if (NewState != DISABLE)
\r
812 /* Enable the TIM Counter */
\r
813 TIMx->CR1 |= TIM_CR1_CEN;
\r
817 /* Disable the TIM Counter */
\r
818 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
\r
823 * @brief Enables or disables the TIM peripheral Main Outputs.
\r
824 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
\r
825 * @param NewState: new state of the TIM peripheral Main Outputs.
\r
826 * This parameter can be: ENABLE or DISABLE.
\r
829 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
831 /* Check the parameters */
\r
832 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
833 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
834 if (NewState != DISABLE)
\r
836 /* Enable the TIM Main Output */
\r
837 TIMx->BDTR |= TIM_BDTR_MOE;
\r
841 /* Disable the TIM Main Output */
\r
842 TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
\r
847 * @brief Enables or disables the specified TIM interrupts.
\r
848 * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
\r
849 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
\r
850 * This parameter can be any combination of the following values:
\r
851 * @arg TIM_IT_Update: TIM update Interrupt source
\r
852 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
853 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
854 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
855 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
856 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
857 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
858 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
860 * - TIM6 and TIM7 can only generate an update interrupt.
\r
861 * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
\r
862 * TIM_IT_CC2 or TIM_IT_Trigger.
\r
863 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
\r
864 * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
\r
865 * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
\r
866 * @param NewState: new state of the TIM interrupts.
\r
867 * This parameter can be: ENABLE or DISABLE.
\r
870 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
\r
872 /* Check the parameters */
\r
873 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
874 assert_param(IS_TIM_IT(TIM_IT));
\r
875 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
877 if (NewState != DISABLE)
\r
879 /* Enable the Interrupt sources */
\r
880 TIMx->DIER |= TIM_IT;
\r
884 /* Disable the Interrupt sources */
\r
885 TIMx->DIER &= (uint16_t)~TIM_IT;
\r
890 * @brief Configures the TIMx event to be generate by software.
\r
891 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
892 * @param TIM_EventSource: specifies the event source.
\r
893 * This parameter can be one or more of the following values:
\r
894 * @arg TIM_EventSource_Update: Timer update Event source
\r
895 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
\r
896 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
\r
897 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
\r
898 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
\r
899 * @arg TIM_EventSource_COM: Timer COM event source
\r
900 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
\r
901 * @arg TIM_EventSource_Break: Timer Break event source
\r
903 * - TIM6 and TIM7 can only generate an update event.
\r
904 * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
\r
907 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
\r
909 /* Check the parameters */
\r
910 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
911 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
\r
913 /* Set the event sources */
\r
914 TIMx->EGR = TIM_EventSource;
\r
918 * @brief Configures the TIMx
\92s DMA interface.
\r
919 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
\r
920 * the TIM peripheral.
\r
921 * @param TIM_DMABase: DMA Base address.
\r
922 * This parameter can be one of the following values:
\r
923 * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
\r
924 * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
\r
925 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
\r
926 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
\r
927 * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
\r
928 * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
\r
930 * @param TIM_DMABurstLength: DMA Burst length.
\r
931 * This parameter can be one value between:
\r
932 * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
\r
935 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
\r
937 /* Check the parameters */
\r
938 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
939 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
\r
940 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
\r
941 /* Set the DMA Base and the DMA Burst Length */
\r
942 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
\r
946 * @brief Enables or disables the TIMx
\92s DMA Requests.
\r
947 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
\r
948 * to select the TIM peripheral.
\r
949 * @param TIM_DMASource: specifies the DMA Request sources.
\r
950 * This parameter can be any combination of the following values:
\r
951 * @arg TIM_DMA_Update: TIM update Interrupt source
\r
952 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
953 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
954 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
955 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
956 * @arg TIM_DMA_COM: TIM Commutation DMA source
\r
957 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
\r
958 * @param NewState: new state of the DMA Request sources.
\r
959 * This parameter can be: ENABLE or DISABLE.
\r
962 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
\r
964 /* Check the parameters */
\r
965 assert_param(IS_TIM_LIST9_PERIPH(TIMx));
\r
966 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
\r
967 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
969 if (NewState != DISABLE)
\r
971 /* Enable the DMA sources */
\r
972 TIMx->DIER |= TIM_DMASource;
\r
976 /* Disable the DMA sources */
\r
977 TIMx->DIER &= (uint16_t)~TIM_DMASource;
\r
982 * @brief Configures the TIMx interrnal Clock
\r
983 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
\r
984 * to select the TIM peripheral.
\r
987 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
\r
989 /* Check the parameters */
\r
990 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
991 /* Disable slave mode to clock the prescaler directly with the internal clock */
\r
992 TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
996 * @brief Configures the TIMx Internal Trigger as External Clock
\r
997 * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
\r
998 * @param TIM_ITRSource: Trigger source.
\r
999 * This parameter can be one of the following values:
\r
1000 * @param TIM_TS_ITR0: Internal Trigger 0
\r
1001 * @param TIM_TS_ITR1: Internal Trigger 1
\r
1002 * @param TIM_TS_ITR2: Internal Trigger 2
\r
1003 * @param TIM_TS_ITR3: Internal Trigger 3
\r
1006 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
1008 /* Check the parameters */
\r
1009 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1010 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
1011 /* Select the Internal Trigger */
\r
1012 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
\r
1013 /* Select the External clock mode1 */
\r
1014 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
1018 * @brief Configures the TIMx Trigger as External Clock
\r
1019 * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
\r
1020 * @param TIM_TIxExternalCLKSource: Trigger source.
\r
1021 * This parameter can be one of the following values:
\r
1022 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
\r
1023 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
\r
1024 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
\r
1025 * @param TIM_ICPolarity: specifies the TIx Polarity.
\r
1026 * This parameter can be one of the following values:
\r
1027 * @arg TIM_ICPolarity_Rising
\r
1028 * @arg TIM_ICPolarity_Falling
\r
1029 * @param ICFilter : specifies the filter value.
\r
1030 * This parameter must be a value between 0x0 and 0xF.
\r
1033 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
\r
1034 uint16_t TIM_ICPolarity, uint16_t ICFilter)
\r
1036 /* Check the parameters */
\r
1037 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1038 assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
\r
1039 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
\r
1040 assert_param(IS_TIM_IC_FILTER(ICFilter));
\r
1041 /* Configure the Timer Input Clock Source */
\r
1042 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
\r
1044 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
1048 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
1050 /* Select the Trigger source */
\r
1051 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
\r
1052 /* Select the External clock mode1 */
\r
1053 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
1057 * @brief Configures the External clock Mode1
\r
1058 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1059 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
1060 * This parameter can be one of the following values:
\r
1061 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
1062 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
1063 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
1064 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
1065 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
1066 * This parameter can be one of the following values:
\r
1067 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
1068 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
1069 * @param ExtTRGFilter: External Trigger Filter.
\r
1070 * This parameter must be a value between 0x00 and 0x0F
\r
1073 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
1074 uint16_t ExtTRGFilter)
\r
1076 uint16_t tmpsmcr = 0;
\r
1077 /* Check the parameters */
\r
1078 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1079 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
1080 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
1081 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
1082 /* Configure the ETR Clock source */
\r
1083 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
1085 /* Get the TIMx SMCR register value */
\r
1086 tmpsmcr = TIMx->SMCR;
\r
1087 /* Reset the SMS Bits */
\r
1088 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
1089 /* Select the External clock mode1 */
\r
1090 tmpsmcr |= TIM_SlaveMode_External1;
\r
1091 /* Select the Trigger selection : ETRF */
\r
1092 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
1093 tmpsmcr |= TIM_TS_ETRF;
\r
1094 /* Write to TIMx SMCR */
\r
1095 TIMx->SMCR = tmpsmcr;
\r
1099 * @brief Configures the External clock Mode2
\r
1100 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1101 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
1102 * This parameter can be one of the following values:
\r
1103 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
1104 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
1105 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
1106 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
1107 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
1108 * This parameter can be one of the following values:
\r
1109 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
1110 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
1111 * @param ExtTRGFilter: External Trigger Filter.
\r
1112 * This parameter must be a value between 0x00 and 0x0F
\r
1115 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
1116 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
\r
1118 /* Check the parameters */
\r
1119 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1120 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
1121 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
1122 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
1123 /* Configure the ETR Clock source */
\r
1124 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
1125 /* Enable the External clock mode2 */
\r
1126 TIMx->SMCR |= TIM_SMCR_ECE;
\r
1130 * @brief Configures the TIMx External Trigger (ETR).
\r
1131 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1132 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
1133 * This parameter can be one of the following values:
\r
1134 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
1135 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
1136 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
1137 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
1138 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
1139 * This parameter can be one of the following values:
\r
1140 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
1141 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
1142 * @param ExtTRGFilter: External Trigger Filter.
\r
1143 * This parameter must be a value between 0x00 and 0x0F
\r
1146 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
1147 uint16_t ExtTRGFilter)
\r
1149 uint16_t tmpsmcr = 0;
\r
1150 /* Check the parameters */
\r
1151 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1152 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
1153 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
1154 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
1155 tmpsmcr = TIMx->SMCR;
\r
1156 /* Reset the ETR Bits */
\r
1157 tmpsmcr &= SMCR_ETR_Mask;
\r
1158 /* Set the Prescaler, the Filter value and the Polarity */
\r
1159 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
\r
1160 /* Write to TIMx SMCR */
\r
1161 TIMx->SMCR = tmpsmcr;
\r
1165 * @brief Configures the TIMx Prescaler.
\r
1166 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
1167 * @param Prescaler: specifies the Prescaler Register value
\r
1168 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
\r
1169 * This parameter can be one of the following values:
\r
1170 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
\r
1171 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
\r
1174 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
\r
1176 /* Check the parameters */
\r
1177 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1178 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
\r
1179 /* Set the Prescaler value */
\r
1180 TIMx->PSC = Prescaler;
\r
1181 /* Set or reset the UG Bit */
\r
1182 TIMx->EGR = TIM_PSCReloadMode;
\r
1186 * @brief Specifies the TIMx Counter Mode to be used.
\r
1187 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1188 * @param TIM_CounterMode: specifies the Counter Mode to be used
\r
1189 * This parameter can be one of the following values:
\r
1190 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
\r
1191 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
\r
1192 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
\r
1193 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
\r
1194 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
\r
1197 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
\r
1199 uint16_t tmpcr1 = 0;
\r
1200 /* Check the parameters */
\r
1201 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1202 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
\r
1203 tmpcr1 = TIMx->CR1;
\r
1204 /* Reset the CMS and DIR Bits */
\r
1205 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
\r
1206 /* Set the Counter Mode */
\r
1207 tmpcr1 |= TIM_CounterMode;
\r
1208 /* Write to TIMx CR1 register */
\r
1209 TIMx->CR1 = tmpcr1;
\r
1213 * @brief Selects the Input Trigger source
\r
1214 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
1215 * @param TIM_InputTriggerSource: The Input Trigger source.
\r
1216 * This parameter can be one of the following values:
\r
1217 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
1218 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
1219 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
1220 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
1221 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
\r
1222 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
\r
1223 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
\r
1224 * @arg TIM_TS_ETRF: External Trigger input
\r
1227 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
1229 uint16_t tmpsmcr = 0;
\r
1230 /* Check the parameters */
\r
1231 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1232 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
1233 /* Get the TIMx SMCR register value */
\r
1234 tmpsmcr = TIMx->SMCR;
\r
1235 /* Reset the TS Bits */
\r
1236 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
1237 /* Set the Input Trigger source */
\r
1238 tmpsmcr |= TIM_InputTriggerSource;
\r
1239 /* Write to TIMx SMCR */
\r
1240 TIMx->SMCR = tmpsmcr;
\r
1244 * @brief Configures the TIMx Encoder Interface.
\r
1245 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1246 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
\r
1247 * This parameter can be one of the following values:
\r
1248 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
\r
1249 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
\r
1250 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
\r
1251 * on the level of the other input.
\r
1252 * @param TIM_IC1Polarity: specifies the IC1 Polarity
\r
1253 * This parmeter can be one of the following values:
\r
1254 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
1255 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
1256 * @param TIM_IC2Polarity: specifies the IC2 Polarity
\r
1257 * This parmeter can be one of the following values:
\r
1258 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
1259 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
1262 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
\r
1263 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
\r
1265 uint16_t tmpsmcr = 0;
\r
1266 uint16_t tmpccmr1 = 0;
\r
1267 uint16_t tmpccer = 0;
\r
1269 /* Check the parameters */
\r
1270 assert_param(IS_TIM_LIST5_PERIPH(TIMx));
\r
1271 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
\r
1272 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
\r
1273 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
\r
1275 /* Get the TIMx SMCR register value */
\r
1276 tmpsmcr = TIMx->SMCR;
\r
1278 /* Get the TIMx CCMR1 register value */
\r
1279 tmpccmr1 = TIMx->CCMR1;
\r
1281 /* Get the TIMx CCER register value */
\r
1282 tmpccer = TIMx->CCER;
\r
1284 /* Set the encoder Mode */
\r
1285 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
1286 tmpsmcr |= TIM_EncoderMode;
\r
1288 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
\r
1289 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
\r
1290 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
\r
1292 /* Set the TI1 and the TI2 Polarities */
\r
1293 tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
\r
1294 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
\r
1296 /* Write to TIMx SMCR */
\r
1297 TIMx->SMCR = tmpsmcr;
\r
1298 /* Write to TIMx CCMR1 */
\r
1299 TIMx->CCMR1 = tmpccmr1;
\r
1300 /* Write to TIMx CCER */
\r
1301 TIMx->CCER = tmpccer;
\r
1305 * @brief Forces the TIMx output 1 waveform to active or inactive level.
\r
1306 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
1307 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1308 * This parameter can be one of the following values:
\r
1309 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
\r
1310 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
\r
1313 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1315 uint16_t tmpccmr1 = 0;
\r
1316 /* Check the parameters */
\r
1317 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
1318 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1319 tmpccmr1 = TIMx->CCMR1;
\r
1320 /* Reset the OC1M Bits */
\r
1321 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
\r
1322 /* Configure The Forced output Mode */
\r
1323 tmpccmr1 |= TIM_ForcedAction;
\r
1324 /* Write to TIMx CCMR1 register */
\r
1325 TIMx->CCMR1 = tmpccmr1;
\r
1329 * @brief Forces the TIMx output 2 waveform to active or inactive level.
\r
1330 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
1331 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1332 * This parameter can be one of the following values:
\r
1333 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
\r
1334 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
\r
1337 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1339 uint16_t tmpccmr1 = 0;
\r
1340 /* Check the parameters */
\r
1341 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1342 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1343 tmpccmr1 = TIMx->CCMR1;
\r
1344 /* Reset the OC2M Bits */
\r
1345 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
\r
1346 /* Configure The Forced output Mode */
\r
1347 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1348 /* Write to TIMx CCMR1 register */
\r
1349 TIMx->CCMR1 = tmpccmr1;
\r
1353 * @brief Forces the TIMx output 3 waveform to active or inactive level.
\r
1354 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1355 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1356 * This parameter can be one of the following values:
\r
1357 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
\r
1358 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
\r
1361 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1363 uint16_t tmpccmr2 = 0;
\r
1364 /* Check the parameters */
\r
1365 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1366 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1367 tmpccmr2 = TIMx->CCMR2;
\r
1368 /* Reset the OC1M Bits */
\r
1369 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
\r
1370 /* Configure The Forced output Mode */
\r
1371 tmpccmr2 |= TIM_ForcedAction;
\r
1372 /* Write to TIMx CCMR2 register */
\r
1373 TIMx->CCMR2 = tmpccmr2;
\r
1377 * @brief Forces the TIMx output 4 waveform to active or inactive level.
\r
1378 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1379 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1380 * This parameter can be one of the following values:
\r
1381 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
\r
1382 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
\r
1385 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1387 uint16_t tmpccmr2 = 0;
\r
1388 /* Check the parameters */
\r
1389 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1390 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1391 tmpccmr2 = TIMx->CCMR2;
\r
1392 /* Reset the OC2M Bits */
\r
1393 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
\r
1394 /* Configure The Forced output Mode */
\r
1395 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1396 /* Write to TIMx CCMR2 register */
\r
1397 TIMx->CCMR2 = tmpccmr2;
\r
1401 * @brief Enables or disables TIMx peripheral Preload register on ARR.
\r
1402 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
1403 * @param NewState: new state of the TIMx peripheral Preload register
\r
1404 * This parameter can be: ENABLE or DISABLE.
\r
1407 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1409 /* Check the parameters */
\r
1410 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1411 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1412 if (NewState != DISABLE)
\r
1414 /* Set the ARR Preload Bit */
\r
1415 TIMx->CR1 |= TIM_CR1_ARPE;
\r
1419 /* Reset the ARR Preload Bit */
\r
1420 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
\r
1425 * @brief Selects the TIM peripheral Commutation event.
\r
1426 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
\r
1427 * @param NewState: new state of the Commutation event.
\r
1428 * This parameter can be: ENABLE or DISABLE.
\r
1431 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1433 /* Check the parameters */
\r
1434 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1435 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1436 if (NewState != DISABLE)
\r
1438 /* Set the COM Bit */
\r
1439 TIMx->CR2 |= TIM_CR2_CCUS;
\r
1443 /* Reset the COM Bit */
\r
1444 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
\r
1449 * @brief Selects the TIMx peripheral Capture Compare DMA source.
\r
1450 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
\r
1451 * the TIM peripheral.
\r
1452 * @param NewState: new state of the Capture Compare DMA source
\r
1453 * This parameter can be: ENABLE or DISABLE.
\r
1456 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1458 /* Check the parameters */
\r
1459 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
1460 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1461 if (NewState != DISABLE)
\r
1463 /* Set the CCDS Bit */
\r
1464 TIMx->CR2 |= TIM_CR2_CCDS;
\r
1468 /* Reset the CCDS Bit */
\r
1469 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
\r
1474 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
\r
1475 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
\r
1476 * to select the TIMx peripheral
\r
1477 * @param NewState: new state of the Capture Compare Preload Control bit
\r
1478 * This parameter can be: ENABLE or DISABLE.
\r
1481 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1483 /* Check the parameters */
\r
1484 assert_param(IS_TIM_LIST5_PERIPH(TIMx));
\r
1485 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1486 if (NewState != DISABLE)
\r
1488 /* Set the CCPC Bit */
\r
1489 TIMx->CR2 |= TIM_CR2_CCPC;
\r
1493 /* Reset the CCPC Bit */
\r
1494 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
\r
1499 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
\r
1500 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
1501 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1502 * This parameter can be one of the following values:
\r
1503 * @arg TIM_OCPreload_Enable
\r
1504 * @arg TIM_OCPreload_Disable
\r
1507 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1509 uint16_t tmpccmr1 = 0;
\r
1510 /* Check the parameters */
\r
1511 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
1512 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1513 tmpccmr1 = TIMx->CCMR1;
\r
1514 /* Reset the OC1PE Bit */
\r
1515 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
\r
1516 /* Enable or Disable the Output Compare Preload feature */
\r
1517 tmpccmr1 |= TIM_OCPreload;
\r
1518 /* Write to TIMx CCMR1 register */
\r
1519 TIMx->CCMR1 = tmpccmr1;
\r
1523 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
\r
1524 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
\r
1525 * the TIM peripheral.
\r
1526 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1527 * This parameter can be one of the following values:
\r
1528 * @arg TIM_OCPreload_Enable
\r
1529 * @arg TIM_OCPreload_Disable
\r
1532 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1534 uint16_t tmpccmr1 = 0;
\r
1535 /* Check the parameters */
\r
1536 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1537 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1538 tmpccmr1 = TIMx->CCMR1;
\r
1539 /* Reset the OC2PE Bit */
\r
1540 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
\r
1541 /* Enable or Disable the Output Compare Preload feature */
\r
1542 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
\r
1543 /* Write to TIMx CCMR1 register */
\r
1544 TIMx->CCMR1 = tmpccmr1;
\r
1548 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
\r
1549 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1550 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1551 * This parameter can be one of the following values:
\r
1552 * @arg TIM_OCPreload_Enable
\r
1553 * @arg TIM_OCPreload_Disable
\r
1556 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1558 uint16_t tmpccmr2 = 0;
\r
1559 /* Check the parameters */
\r
1560 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1561 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1562 tmpccmr2 = TIMx->CCMR2;
\r
1563 /* Reset the OC3PE Bit */
\r
1564 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
\r
1565 /* Enable or Disable the Output Compare Preload feature */
\r
1566 tmpccmr2 |= TIM_OCPreload;
\r
1567 /* Write to TIMx CCMR2 register */
\r
1568 TIMx->CCMR2 = tmpccmr2;
\r
1572 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
\r
1573 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1574 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1575 * This parameter can be one of the following values:
\r
1576 * @arg TIM_OCPreload_Enable
\r
1577 * @arg TIM_OCPreload_Disable
\r
1580 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1582 uint16_t tmpccmr2 = 0;
\r
1583 /* Check the parameters */
\r
1584 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1585 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1586 tmpccmr2 = TIMx->CCMR2;
\r
1587 /* Reset the OC4PE Bit */
\r
1588 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
\r
1589 /* Enable or Disable the Output Compare Preload feature */
\r
1590 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
\r
1591 /* Write to TIMx CCMR2 register */
\r
1592 TIMx->CCMR2 = tmpccmr2;
\r
1596 * @brief Configures the TIMx Output Compare 1 Fast feature.
\r
1597 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
1598 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1599 * This parameter can be one of the following values:
\r
1600 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1601 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1604 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1606 uint16_t tmpccmr1 = 0;
\r
1607 /* Check the parameters */
\r
1608 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
1609 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1610 /* Get the TIMx CCMR1 register value */
\r
1611 tmpccmr1 = TIMx->CCMR1;
\r
1612 /* Reset the OC1FE Bit */
\r
1613 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
\r
1614 /* Enable or Disable the Output Compare Fast Bit */
\r
1615 tmpccmr1 |= TIM_OCFast;
\r
1616 /* Write to TIMx CCMR1 */
\r
1617 TIMx->CCMR1 = tmpccmr1;
\r
1621 * @brief Configures the TIMx Output Compare 2 Fast feature.
\r
1622 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
\r
1623 * the TIM peripheral.
\r
1624 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1625 * This parameter can be one of the following values:
\r
1626 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1627 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1630 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1632 uint16_t tmpccmr1 = 0;
\r
1633 /* Check the parameters */
\r
1634 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1635 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1636 /* Get the TIMx CCMR1 register value */
\r
1637 tmpccmr1 = TIMx->CCMR1;
\r
1638 /* Reset the OC2FE Bit */
\r
1639 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
\r
1640 /* Enable or Disable the Output Compare Fast Bit */
\r
1641 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
\r
1642 /* Write to TIMx CCMR1 */
\r
1643 TIMx->CCMR1 = tmpccmr1;
\r
1647 * @brief Configures the TIMx Output Compare 3 Fast feature.
\r
1648 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1649 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1650 * This parameter can be one of the following values:
\r
1651 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1652 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1655 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1657 uint16_t tmpccmr2 = 0;
\r
1658 /* Check the parameters */
\r
1659 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1660 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1661 /* Get the TIMx CCMR2 register value */
\r
1662 tmpccmr2 = TIMx->CCMR2;
\r
1663 /* Reset the OC3FE Bit */
\r
1664 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
\r
1665 /* Enable or Disable the Output Compare Fast Bit */
\r
1666 tmpccmr2 |= TIM_OCFast;
\r
1667 /* Write to TIMx CCMR2 */
\r
1668 TIMx->CCMR2 = tmpccmr2;
\r
1672 * @brief Configures the TIMx Output Compare 4 Fast feature.
\r
1673 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1674 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1675 * This parameter can be one of the following values:
\r
1676 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1677 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1680 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1682 uint16_t tmpccmr2 = 0;
\r
1683 /* Check the parameters */
\r
1684 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1685 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1686 /* Get the TIMx CCMR2 register value */
\r
1687 tmpccmr2 = TIMx->CCMR2;
\r
1688 /* Reset the OC4FE Bit */
\r
1689 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
\r
1690 /* Enable or Disable the Output Compare Fast Bit */
\r
1691 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
\r
1692 /* Write to TIMx CCMR2 */
\r
1693 TIMx->CCMR2 = tmpccmr2;
\r
1697 * @brief Clears or safeguards the OCREF1 signal on an external event
\r
1698 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1699 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1700 * This parameter can be one of the following values:
\r
1701 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1702 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1705 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1707 uint16_t tmpccmr1 = 0;
\r
1708 /* Check the parameters */
\r
1709 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1710 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1712 tmpccmr1 = TIMx->CCMR1;
\r
1714 /* Reset the OC1CE Bit */
\r
1715 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
\r
1716 /* Enable or Disable the Output Compare Clear Bit */
\r
1717 tmpccmr1 |= TIM_OCClear;
\r
1718 /* Write to TIMx CCMR1 register */
\r
1719 TIMx->CCMR1 = tmpccmr1;
\r
1723 * @brief Clears or safeguards the OCREF2 signal on an external event
\r
1724 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1725 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1726 * This parameter can be one of the following values:
\r
1727 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1728 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1731 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1733 uint16_t tmpccmr1 = 0;
\r
1734 /* Check the parameters */
\r
1735 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1736 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1737 tmpccmr1 = TIMx->CCMR1;
\r
1738 /* Reset the OC2CE Bit */
\r
1739 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
\r
1740 /* Enable or Disable the Output Compare Clear Bit */
\r
1741 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
\r
1742 /* Write to TIMx CCMR1 register */
\r
1743 TIMx->CCMR1 = tmpccmr1;
\r
1747 * @brief Clears or safeguards the OCREF3 signal on an external event
\r
1748 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1749 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1750 * This parameter can be one of the following values:
\r
1751 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1752 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1755 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1757 uint16_t tmpccmr2 = 0;
\r
1758 /* Check the parameters */
\r
1759 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1760 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1761 tmpccmr2 = TIMx->CCMR2;
\r
1762 /* Reset the OC3CE Bit */
\r
1763 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
\r
1764 /* Enable or Disable the Output Compare Clear Bit */
\r
1765 tmpccmr2 |= TIM_OCClear;
\r
1766 /* Write to TIMx CCMR2 register */
\r
1767 TIMx->CCMR2 = tmpccmr2;
\r
1771 * @brief Clears or safeguards the OCREF4 signal on an external event
\r
1772 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1773 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1774 * This parameter can be one of the following values:
\r
1775 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1776 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1779 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1781 uint16_t tmpccmr2 = 0;
\r
1782 /* Check the parameters */
\r
1783 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1784 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1785 tmpccmr2 = TIMx->CCMR2;
\r
1786 /* Reset the OC4CE Bit */
\r
1787 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
\r
1788 /* Enable or Disable the Output Compare Clear Bit */
\r
1789 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
\r
1790 /* Write to TIMx CCMR2 register */
\r
1791 TIMx->CCMR2 = tmpccmr2;
\r
1795 * @brief Configures the TIMx channel 1 polarity.
\r
1796 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
1797 * @param TIM_OCPolarity: specifies the OC1 Polarity
\r
1798 * This parmeter can be one of the following values:
\r
1799 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1800 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1803 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1805 uint16_t tmpccer = 0;
\r
1806 /* Check the parameters */
\r
1807 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
1808 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1809 tmpccer = TIMx->CCER;
\r
1810 /* Set or Reset the CC1P Bit */
\r
1811 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
\r
1812 tmpccer |= TIM_OCPolarity;
\r
1813 /* Write to TIMx CCER register */
\r
1814 TIMx->CCER = tmpccer;
\r
1818 * @brief Configures the TIMx Channel 1N polarity.
\r
1819 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
\r
1820 * @param TIM_OCNPolarity: specifies the OC1N Polarity
\r
1821 * This parmeter can be one of the following values:
\r
1822 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1823 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1826 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1828 uint16_t tmpccer = 0;
\r
1829 /* Check the parameters */
\r
1830 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1831 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1833 tmpccer = TIMx->CCER;
\r
1834 /* Set or Reset the CC1NP Bit */
\r
1835 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
\r
1836 tmpccer |= TIM_OCNPolarity;
\r
1837 /* Write to TIMx CCER register */
\r
1838 TIMx->CCER = tmpccer;
\r
1842 * @brief Configures the TIMx channel 2 polarity.
\r
1843 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
1844 * @param TIM_OCPolarity: specifies the OC2 Polarity
\r
1845 * This parmeter can be one of the following values:
\r
1846 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1847 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1850 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1852 uint16_t tmpccer = 0;
\r
1853 /* Check the parameters */
\r
1854 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
1855 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1856 tmpccer = TIMx->CCER;
\r
1857 /* Set or Reset the CC2P Bit */
\r
1858 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
\r
1859 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
\r
1860 /* Write to TIMx CCER register */
\r
1861 TIMx->CCER = tmpccer;
\r
1865 * @brief Configures the TIMx Channel 2N polarity.
\r
1866 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
\r
1867 * @param TIM_OCNPolarity: specifies the OC2N Polarity
\r
1868 * This parmeter can be one of the following values:
\r
1869 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1870 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1873 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1875 uint16_t tmpccer = 0;
\r
1876 /* Check the parameters */
\r
1877 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1878 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1880 tmpccer = TIMx->CCER;
\r
1881 /* Set or Reset the CC2NP Bit */
\r
1882 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
\r
1883 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
\r
1884 /* Write to TIMx CCER register */
\r
1885 TIMx->CCER = tmpccer;
\r
1889 * @brief Configures the TIMx channel 3 polarity.
\r
1890 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1891 * @param TIM_OCPolarity: specifies the OC3 Polarity
\r
1892 * This parmeter can be one of the following values:
\r
1893 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1894 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1897 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1899 uint16_t tmpccer = 0;
\r
1900 /* Check the parameters */
\r
1901 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1902 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1903 tmpccer = TIMx->CCER;
\r
1904 /* Set or Reset the CC3P Bit */
\r
1905 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
\r
1906 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
\r
1907 /* Write to TIMx CCER register */
\r
1908 TIMx->CCER = tmpccer;
\r
1912 * @brief Configures the TIMx Channel 3N polarity.
\r
1913 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
\r
1914 * @param TIM_OCNPolarity: specifies the OC3N Polarity
\r
1915 * This parmeter can be one of the following values:
\r
1916 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1917 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1920 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1922 uint16_t tmpccer = 0;
\r
1924 /* Check the parameters */
\r
1925 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1926 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1928 tmpccer = TIMx->CCER;
\r
1929 /* Set or Reset the CC3NP Bit */
\r
1930 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
\r
1931 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
\r
1932 /* Write to TIMx CCER register */
\r
1933 TIMx->CCER = tmpccer;
\r
1937 * @brief Configures the TIMx channel 4 polarity.
\r
1938 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1939 * @param TIM_OCPolarity: specifies the OC4 Polarity
\r
1940 * This parmeter can be one of the following values:
\r
1941 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1942 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1945 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1947 uint16_t tmpccer = 0;
\r
1948 /* Check the parameters */
\r
1949 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1950 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1951 tmpccer = TIMx->CCER;
\r
1952 /* Set or Reset the CC4P Bit */
\r
1953 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
\r
1954 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
\r
1955 /* Write to TIMx CCER register */
\r
1956 TIMx->CCER = tmpccer;
\r
1960 * @brief Enables or disables the TIM Capture Compare Channel x.
\r
1961 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
1962 * @param TIM_Channel: specifies the TIM Channel
\r
1963 * This parmeter can be one of the following values:
\r
1964 * @arg TIM_Channel_1: TIM Channel 1
\r
1965 * @arg TIM_Channel_2: TIM Channel 2
\r
1966 * @arg TIM_Channel_3: TIM Channel 3
\r
1967 * @arg TIM_Channel_4: TIM Channel 4
\r
1968 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
\r
1969 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
\r
1972 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
\r
1976 /* Check the parameters */
\r
1977 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
1978 assert_param(IS_TIM_CHANNEL(TIM_Channel));
\r
1979 assert_param(IS_TIM_CCX(TIM_CCx));
\r
1981 tmp = CCER_CCE_Set << TIM_Channel;
\r
1983 /* Reset the CCxE Bit */
\r
1984 TIMx->CCER &= (uint16_t)~ tmp;
\r
1986 /* Set or reset the CCxE Bit */
\r
1987 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
\r
1991 * @brief Enables or disables the TIM Capture Compare Channel xN.
\r
1992 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
\r
1993 * @param TIM_Channel: specifies the TIM Channel
\r
1994 * This parmeter can be one of the following values:
\r
1995 * @arg TIM_Channel_1: TIM Channel 1
\r
1996 * @arg TIM_Channel_2: TIM Channel 2
\r
1997 * @arg TIM_Channel_3: TIM Channel 3
\r
1998 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
\r
1999 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
\r
2002 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
\r
2006 /* Check the parameters */
\r
2007 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2008 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
\r
2009 assert_param(IS_TIM_CCXN(TIM_CCxN));
\r
2011 tmp = CCER_CCNE_Set << TIM_Channel;
\r
2013 /* Reset the CCxNE Bit */
\r
2014 TIMx->CCER &= (uint16_t) ~tmp;
\r
2016 /* Set or reset the CCxNE Bit */
\r
2017 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
\r
2021 * @brief Selects the TIM Ouput Compare Mode.
\r
2022 * @note This function disables the selected channel before changing the Ouput
\r
2024 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
\r
2025 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
2026 * @param TIM_Channel: specifies the TIM Channel
\r
2027 * This parmeter can be one of the following values:
\r
2028 * @arg TIM_Channel_1: TIM Channel 1
\r
2029 * @arg TIM_Channel_2: TIM Channel 2
\r
2030 * @arg TIM_Channel_3: TIM Channel 3
\r
2031 * @arg TIM_Channel_4: TIM Channel 4
\r
2032 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
\r
2033 * This paramter can be one of the following values:
\r
2034 * @arg TIM_OCMode_Timing
\r
2035 * @arg TIM_OCMode_Active
\r
2036 * @arg TIM_OCMode_Toggle
\r
2037 * @arg TIM_OCMode_PWM1
\r
2038 * @arg TIM_OCMode_PWM2
\r
2039 * @arg TIM_ForcedAction_Active
\r
2040 * @arg TIM_ForcedAction_InActive
\r
2043 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
\r
2046 uint16_t tmp1 = 0;
\r
2048 /* Check the parameters */
\r
2049 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
2050 assert_param(IS_TIM_CHANNEL(TIM_Channel));
\r
2051 assert_param(IS_TIM_OCM(TIM_OCMode));
\r
2053 tmp = (uint32_t) TIMx;
\r
2054 tmp += CCMR_Offset;
\r
2056 tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
\r
2058 /* Disable the Channel: Reset the CCxE Bit */
\r
2059 TIMx->CCER &= (uint16_t) ~tmp1;
\r
2061 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
\r
2063 tmp += (TIM_Channel>>1);
\r
2065 /* Reset the OCxM bits in the CCMRx register */
\r
2066 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
\r
2068 /* Configure the OCxM bits in the CCMRx register */
\r
2069 *(__IO uint32_t *) tmp |= TIM_OCMode;
\r
2073 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
\r
2075 /* Reset the OCxM bits in the CCMRx register */
\r
2076 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
\r
2078 /* Configure the OCxM bits in the CCMRx register */
\r
2079 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
\r
2084 * @brief Enables or Disables the TIMx Update event.
\r
2085 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2086 * @param NewState: new state of the TIMx UDIS bit
\r
2087 * This parameter can be: ENABLE or DISABLE.
\r
2090 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2092 /* Check the parameters */
\r
2093 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2094 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2095 if (NewState != DISABLE)
\r
2097 /* Set the Update Disable Bit */
\r
2098 TIMx->CR1 |= TIM_CR1_UDIS;
\r
2102 /* Reset the Update Disable Bit */
\r
2103 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
\r
2108 * @brief Configures the TIMx Update Request Interrupt source.
\r
2109 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2110 * @param TIM_UpdateSource: specifies the Update source.
\r
2111 * This parameter can be one of the following values:
\r
2112 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
\r
2113 or the setting of UG bit, or an update generation
\r
2114 through the slave mode controller.
\r
2115 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
\r
2118 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
\r
2120 /* Check the parameters */
\r
2121 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2122 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
\r
2123 if (TIM_UpdateSource != TIM_UpdateSource_Global)
\r
2125 /* Set the URS Bit */
\r
2126 TIMx->CR1 |= TIM_CR1_URS;
\r
2130 /* Reset the URS Bit */
\r
2131 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
\r
2136 * @brief Enables or disables the TIMx
\92s Hall sensor interface.
\r
2137 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2138 * @param NewState: new state of the TIMx Hall sensor interface.
\r
2139 * This parameter can be: ENABLE or DISABLE.
\r
2142 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2144 /* Check the parameters */
\r
2145 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2146 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2147 if (NewState != DISABLE)
\r
2149 /* Set the TI1S Bit */
\r
2150 TIMx->CR2 |= TIM_CR2_TI1S;
\r
2154 /* Reset the TI1S Bit */
\r
2155 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
\r
2160 * @brief Selects the TIMx
\92s One Pulse Mode.
\r
2161 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2162 * @param TIM_OPMode: specifies the OPM Mode to be used.
\r
2163 * This parameter can be one of the following values:
\r
2164 * @arg TIM_OPMode_Single
\r
2165 * @arg TIM_OPMode_Repetitive
\r
2168 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
\r
2170 /* Check the parameters */
\r
2171 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2172 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
\r
2173 /* Reset the OPM Bit */
\r
2174 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
\r
2175 /* Configure the OPM Mode */
\r
2176 TIMx->CR1 |= TIM_OPMode;
\r
2180 * @brief Selects the TIMx Trigger Output Mode.
\r
2181 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2182 * @param TIM_TRGOSource: specifies the Trigger Output source.
\r
2183 * This paramter can be one of the following values:
\r
2186 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
\r
2187 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
\r
2188 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
\r
2190 * - For all TIMx except TIM6 and TIM7
\r
2191 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
\r
2192 * is to be set, as soon as a capture or compare match occurs (TRGO).
\r
2193 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
\r
2194 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
\r
2195 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
\r
2196 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
\r
2200 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
\r
2202 /* Check the parameters */
\r
2203 assert_param(IS_TIM_LIST7_PERIPH(TIMx));
\r
2204 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
\r
2205 /* Reset the MMS Bits */
\r
2206 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
\r
2207 /* Select the TRGO source */
\r
2208 TIMx->CR2 |= TIM_TRGOSource;
\r
2212 * @brief Selects the TIMx Slave Mode.
\r
2213 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2214 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
\r
2215 * This paramter can be one of the following values:
\r
2216 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
\r
2217 * the counter and triggers an update of the registers.
\r
2218 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
\r
2219 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
\r
2220 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
\r
2223 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
\r
2225 /* Check the parameters */
\r
2226 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2227 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
\r
2228 /* Reset the SMS Bits */
\r
2229 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
\r
2230 /* Select the Slave Mode */
\r
2231 TIMx->SMCR |= TIM_SlaveMode;
\r
2235 * @brief Sets or Resets the TIMx Master/Slave Mode.
\r
2236 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2237 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
\r
2238 * This paramter can be one of the following values:
\r
2239 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
\r
2240 * and its slaves (through TRGO).
\r
2241 * @arg TIM_MasterSlaveMode_Disable: No action
\r
2244 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
\r
2246 /* Check the parameters */
\r
2247 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2248 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
\r
2249 /* Reset the MSM Bit */
\r
2250 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
\r
2252 /* Set or Reset the MSM Bit */
\r
2253 TIMx->SMCR |= TIM_MasterSlaveMode;
\r
2257 * @brief Sets the TIMx Counter Register value
\r
2258 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2259 * @param Counter: specifies the Counter register new value.
\r
2262 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
\r
2264 /* Check the parameters */
\r
2265 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2266 /* Set the Counter Register value */
\r
2267 TIMx->CNT = Counter;
\r
2271 * @brief Sets the TIMx Autoreload Register value
\r
2272 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2273 * @param Autoreload: specifies the Autoreload register new value.
\r
2276 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
\r
2278 /* Check the parameters */
\r
2279 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2280 /* Set the Autoreload Register value */
\r
2281 TIMx->ARR = Autoreload;
\r
2285 * @brief Sets the TIMx Capture Compare1 Register value
\r
2286 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
2287 * @param Compare1: specifies the Capture Compare1 register new value.
\r
2290 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
\r
2292 /* Check the parameters */
\r
2293 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
2294 /* Set the Capture Compare1 Register value */
\r
2295 TIMx->CCR1 = Compare1;
\r
2299 * @brief Sets the TIMx Capture Compare2 Register value
\r
2300 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2301 * @param Compare2: specifies the Capture Compare2 register new value.
\r
2304 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
\r
2306 /* Check the parameters */
\r
2307 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2308 /* Set the Capture Compare2 Register value */
\r
2309 TIMx->CCR2 = Compare2;
\r
2313 * @brief Sets the TIMx Capture Compare3 Register value
\r
2314 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2315 * @param Compare3: specifies the Capture Compare3 register new value.
\r
2318 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
\r
2320 /* Check the parameters */
\r
2321 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2322 /* Set the Capture Compare3 Register value */
\r
2323 TIMx->CCR3 = Compare3;
\r
2327 * @brief Sets the TIMx Capture Compare4 Register value
\r
2328 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2329 * @param Compare4: specifies the Capture Compare4 register new value.
\r
2332 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
\r
2334 /* Check the parameters */
\r
2335 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2336 /* Set the Capture Compare4 Register value */
\r
2337 TIMx->CCR4 = Compare4;
\r
2341 * @brief Sets the TIMx Input Capture 1 prescaler.
\r
2342 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
2343 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
\r
2344 * This parameter can be one of the following values:
\r
2345 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2346 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2347 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2348 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2351 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2353 /* Check the parameters */
\r
2354 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
2355 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2356 /* Reset the IC1PSC Bits */
\r
2357 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
\r
2358 /* Set the IC1PSC value */
\r
2359 TIMx->CCMR1 |= TIM_ICPSC;
\r
2363 * @brief Sets the TIMx Input Capture 2 prescaler.
\r
2364 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2365 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
\r
2366 * This parameter can be one of the following values:
\r
2367 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2368 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2369 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2370 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2373 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2375 /* Check the parameters */
\r
2376 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2377 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2378 /* Reset the IC2PSC Bits */
\r
2379 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
\r
2380 /* Set the IC2PSC value */
\r
2381 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
\r
2385 * @brief Sets the TIMx Input Capture 3 prescaler.
\r
2386 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2387 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
\r
2388 * This parameter can be one of the following values:
\r
2389 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2390 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2391 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2392 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2395 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2397 /* Check the parameters */
\r
2398 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2399 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2400 /* Reset the IC3PSC Bits */
\r
2401 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
\r
2402 /* Set the IC3PSC value */
\r
2403 TIMx->CCMR2 |= TIM_ICPSC;
\r
2407 * @brief Sets the TIMx Input Capture 4 prescaler.
\r
2408 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2409 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
\r
2410 * This parameter can be one of the following values:
\r
2411 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2412 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2413 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2414 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2417 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2419 /* Check the parameters */
\r
2420 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2421 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2422 /* Reset the IC4PSC Bits */
\r
2423 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
\r
2424 /* Set the IC4PSC value */
\r
2425 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
\r
2429 * @brief Sets the TIMx Clock Division value.
\r
2430 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select
\r
2431 * the TIM peripheral.
\r
2432 * @param TIM_CKD: specifies the clock division value.
\r
2433 * This parameter can be one of the following value:
\r
2434 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
\r
2435 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
\r
2436 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
\r
2439 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
\r
2441 /* Check the parameters */
\r
2442 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
2443 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
\r
2444 /* Reset the CKD Bits */
\r
2445 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
\r
2446 /* Set the CKD value */
\r
2447 TIMx->CR1 |= TIM_CKD;
\r
2451 * @brief Gets the TIMx Input Capture 1 value.
\r
2452 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
2453 * @retval Capture Compare 1 Register value.
\r
2455 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
\r
2457 /* Check the parameters */
\r
2458 assert_param(IS_TIM_LIST8_PERIPH(TIMx));
\r
2459 /* Get the Capture 1 Register value */
\r
2460 return TIMx->CCR1;
\r
2464 * @brief Gets the TIMx Input Capture 2 value.
\r
2465 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2466 * @retval Capture Compare 2 Register value.
\r
2468 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
\r
2470 /* Check the parameters */
\r
2471 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2472 /* Get the Capture 2 Register value */
\r
2473 return TIMx->CCR2;
\r
2477 * @brief Gets the TIMx Input Capture 3 value.
\r
2478 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2479 * @retval Capture Compare 3 Register value.
\r
2481 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
\r
2483 /* Check the parameters */
\r
2484 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2485 /* Get the Capture 3 Register value */
\r
2486 return TIMx->CCR3;
\r
2490 * @brief Gets the TIMx Input Capture 4 value.
\r
2491 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2492 * @retval Capture Compare 4 Register value.
\r
2494 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
\r
2496 /* Check the parameters */
\r
2497 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2498 /* Get the Capture 4 Register value */
\r
2499 return TIMx->CCR4;
\r
2503 * @brief Gets the TIMx Counter value.
\r
2504 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2505 * @retval Counter Register value.
\r
2507 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
\r
2509 /* Check the parameters */
\r
2510 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2511 /* Get the Counter Register value */
\r
2516 * @brief Gets the TIMx Prescaler value.
\r
2517 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2518 * @retval Prescaler Register value.
\r
2520 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
\r
2522 /* Check the parameters */
\r
2523 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2524 /* Get the Prescaler Register value */
\r
2529 * @brief Checks whether the specified TIM flag is set or not.
\r
2530 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2531 * @param TIM_FLAG: specifies the flag to check.
\r
2532 * This parameter can be one of the following values:
\r
2533 * @arg TIM_FLAG_Update: TIM update Flag
\r
2534 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2535 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2536 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2537 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2538 * @arg TIM_FLAG_COM: TIM Commutation Flag
\r
2539 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2540 * @arg TIM_FLAG_Break: TIM Break Flag
\r
2541 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2542 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2543 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2544 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2546 * - TIM6 and TIM7 can have only one update flag.
\r
2547 * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
\r
2548 * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
\r
2549 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
\r
2550 * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
\r
2551 * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
\r
2552 * @retval The new state of TIM_FLAG (SET or RESET).
\r
2554 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2556 ITStatus bitstatus = RESET;
\r
2557 /* Check the parameters */
\r
2558 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2559 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
\r
2561 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
\r
2567 bitstatus = RESET;
\r
2573 * @brief Clears the TIMx's pending flags.
\r
2574 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2575 * @param TIM_FLAG: specifies the flag bit to clear.
\r
2576 * This parameter can be any combination of the following values:
\r
2577 * @arg TIM_FLAG_Update: TIM update Flag
\r
2578 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2579 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2580 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2581 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2582 * @arg TIM_FLAG_COM: TIM Commutation Flag
\r
2583 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2584 * @arg TIM_FLAG_Break: TIM Break Flag
\r
2585 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2586 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2587 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2588 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2590 * - TIM6 and TIM7 can have only one update flag.
\r
2591 * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
\r
2592 * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
\r
2593 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
\r
2594 * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
\r
2595 * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
\r
2598 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2600 /* Check the parameters */
\r
2601 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2602 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
\r
2604 /* Clear the flags */
\r
2605 TIMx->SR = (uint16_t)~TIM_FLAG;
\r
2609 * @brief Checks whether the TIM interrupt has occurred or not.
\r
2610 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2611 * @param TIM_IT: specifies the TIM interrupt source to check.
\r
2612 * This parameter can be one of the following values:
\r
2613 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2614 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2615 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2616 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2617 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2618 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2619 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2620 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2622 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2623 * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
\r
2624 * TIM_IT_CC2 or TIM_IT_Trigger.
\r
2625 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
\r
2626 * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
\r
2627 * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
\r
2628 * @retval The new state of the TIM_IT(SET or RESET).
\r
2630 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2632 ITStatus bitstatus = RESET;
\r
2633 uint16_t itstatus = 0x0, itenable = 0x0;
\r
2634 /* Check the parameters */
\r
2635 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2636 assert_param(IS_TIM_GET_IT(TIM_IT));
\r
2638 itstatus = TIMx->SR & TIM_IT;
\r
2640 itenable = TIMx->DIER & TIM_IT;
\r
2641 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
\r
2647 bitstatus = RESET;
\r
2653 * @brief Clears the TIMx's interrupt pending bits.
\r
2654 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
\r
2655 * @param TIM_IT: specifies the pending bit to clear.
\r
2656 * This parameter can be any combination of the following values:
\r
2657 * @arg TIM_IT_Update: TIM1 update Interrupt source
\r
2658 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2659 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2660 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2661 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2662 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2663 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2664 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2666 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2667 * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
\r
2668 * TIM_IT_CC2 or TIM_IT_Trigger.
\r
2669 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
\r
2670 * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
\r
2671 * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
\r
2674 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2676 /* Check the parameters */
\r
2677 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2678 assert_param(IS_TIM_IT(TIM_IT));
\r
2679 /* Clear the IT pending Bit */
\r
2680 TIMx->SR = (uint16_t)~TIM_IT;
\r
2684 * @brief Configure the TI1 as Input.
\r
2685 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
\r
2686 * @param TIM_ICPolarity : The Input Polarity.
\r
2687 * This parameter can be one of the following values:
\r
2688 * @arg TIM_ICPolarity_Rising
\r
2689 * @arg TIM_ICPolarity_Falling
\r
2690 * @param TIM_ICSelection: specifies the input to be used.
\r
2691 * This parameter can be one of the following values:
\r
2692 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
\r
2693 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
\r
2694 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
\r
2695 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2696 * This parameter must be a value between 0x00 and 0x0F.
\r
2699 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2700 uint16_t TIM_ICFilter)
\r
2702 uint16_t tmpccmr1 = 0, tmpccer = 0;
\r
2703 /* Disable the Channel 1: Reset the CC1E Bit */
\r
2704 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
\r
2705 tmpccmr1 = TIMx->CCMR1;
\r
2706 tmpccer = TIMx->CCER;
\r
2707 /* Select the Input and set the filter */
\r
2708 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
\r
2709 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2711 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
\r
2712 (TIMx == TIM4) ||(TIMx == TIM5))
\r
2714 /* Select the Polarity and set the CC1E Bit */
\r
2715 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
\r
2716 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
\r
2720 /* Select the Polarity and set the CC1E Bit */
\r
2721 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
\r
2722 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
\r
2725 /* Write to TIMx CCMR1 and CCER registers */
\r
2726 TIMx->CCMR1 = tmpccmr1;
\r
2727 TIMx->CCER = tmpccer;
\r
2731 * @brief Configure the TI2 as Input.
\r
2732 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
\r
2733 * @param TIM_ICPolarity : The Input Polarity.
\r
2734 * This parameter can be one of the following values:
\r
2735 * @arg TIM_ICPolarity_Rising
\r
2736 * @arg TIM_ICPolarity_Falling
\r
2737 * @param TIM_ICSelection: specifies the input to be used.
\r
2738 * This parameter can be one of the following values:
\r
2739 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
\r
2740 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
\r
2741 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
\r
2742 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2743 * This parameter must be a value between 0x00 and 0x0F.
\r
2746 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2747 uint16_t TIM_ICFilter)
\r
2749 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
\r
2750 /* Disable the Channel 2: Reset the CC2E Bit */
\r
2751 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
\r
2752 tmpccmr1 = TIMx->CCMR1;
\r
2753 tmpccer = TIMx->CCER;
\r
2754 tmp = (uint16_t)(TIM_ICPolarity << 4);
\r
2755 /* Select the Input and set the filter */
\r
2756 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
\r
2757 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
\r
2758 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
\r
2760 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
\r
2761 (TIMx == TIM4) ||(TIMx == TIM5))
\r
2763 /* Select the Polarity and set the CC2E Bit */
\r
2764 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
\r
2765 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
\r
2769 /* Select the Polarity and set the CC2E Bit */
\r
2770 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
\r
2771 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
\r
2774 /* Write to TIMx CCMR1 and CCER registers */
\r
2775 TIMx->CCMR1 = tmpccmr1 ;
\r
2776 TIMx->CCER = tmpccer;
\r
2780 * @brief Configure the TI3 as Input.
\r
2781 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2782 * @param TIM_ICPolarity : The Input Polarity.
\r
2783 * This parameter can be one of the following values:
\r
2784 * @arg TIM_ICPolarity_Rising
\r
2785 * @arg TIM_ICPolarity_Falling
\r
2786 * @param TIM_ICSelection: specifies the input to be used.
\r
2787 * This parameter can be one of the following values:
\r
2788 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
\r
2789 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
\r
2790 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
\r
2791 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2792 * This parameter must be a value between 0x00 and 0x0F.
\r
2795 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2796 uint16_t TIM_ICFilter)
\r
2798 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2799 /* Disable the Channel 3: Reset the CC3E Bit */
\r
2800 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
\r
2801 tmpccmr2 = TIMx->CCMR2;
\r
2802 tmpccer = TIMx->CCER;
\r
2803 tmp = (uint16_t)(TIM_ICPolarity << 8);
\r
2804 /* Select the Input and set the filter */
\r
2805 tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
\r
2806 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2808 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
\r
2809 (TIMx == TIM4) ||(TIMx == TIM5))
\r
2811 /* Select the Polarity and set the CC3E Bit */
\r
2812 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
\r
2813 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
\r
2817 /* Select the Polarity and set the CC3E Bit */
\r
2818 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
\r
2819 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
\r
2822 /* Write to TIMx CCMR2 and CCER registers */
\r
2823 TIMx->CCMR2 = tmpccmr2;
\r
2824 TIMx->CCER = tmpccer;
\r
2828 * @brief Configure the TI4 as Input.
\r
2829 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2830 * @param TIM_ICPolarity : The Input Polarity.
\r
2831 * This parameter can be one of the following values:
\r
2832 * @arg TIM_ICPolarity_Rising
\r
2833 * @arg TIM_ICPolarity_Falling
\r
2834 * @param TIM_ICSelection: specifies the input to be used.
\r
2835 * This parameter can be one of the following values:
\r
2836 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
\r
2837 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
\r
2838 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
\r
2839 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2840 * This parameter must be a value between 0x00 and 0x0F.
\r
2843 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2844 uint16_t TIM_ICFilter)
\r
2846 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2848 /* Disable the Channel 4: Reset the CC4E Bit */
\r
2849 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
\r
2850 tmpccmr2 = TIMx->CCMR2;
\r
2851 tmpccer = TIMx->CCER;
\r
2852 tmp = (uint16_t)(TIM_ICPolarity << 12);
\r
2853 /* Select the Input and set the filter */
\r
2854 tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
\r
2855 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
\r
2856 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
\r
2858 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
\r
2859 (TIMx == TIM4) ||(TIMx == TIM5))
\r
2861 /* Select the Polarity and set the CC4E Bit */
\r
2862 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
\r
2863 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
\r
2867 /* Select the Polarity and set the CC4E Bit */
\r
2868 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
\r
2869 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
\r
2871 /* Write to TIMx CCMR2 and CCER registers */
\r
2872 TIMx->CCMR2 = tmpccmr2;
\r
2873 TIMx->CCER = tmpccer;
\r
2888 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r