1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
\r
2 * File Name : stm32f10x_dma.h
\r
3 * Author : MCD Application Team
\r
6 * Description : This file contains all the functions prototypes for the
\r
7 * DMA firmware library.
\r
8 ********************************************************************************
\r
9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
\r
11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
\r
12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
\r
13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
\r
14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
15 *******************************************************************************/
\r
17 /* Define to prevent recursive inclusion -------------------------------------*/
\r
18 #ifndef __STM32F10x_DMA_H
\r
19 #define __STM32F10x_DMA_H
\r
21 /* Includes ------------------------------------------------------------------*/
\r
22 #include "stm32f10x_map.h"
\r
24 /* Exported types ------------------------------------------------------------*/
\r
25 /* DMA Init structure definition */
\r
28 u32 DMA_PeripheralBaseAddr;
\r
29 u32 DMA_MemoryBaseAddr;
\r
32 u32 DMA_PeripheralInc;
\r
34 u32 DMA_PeripheralDataSize;
\r
35 u32 DMA_MemoryDataSize;
\r
41 /* Exported constants --------------------------------------------------------*/
\r
42 #define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \
\r
43 ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \
\r
44 ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \
\r
45 ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \
\r
46 ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \
\r
47 ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \
\r
48 ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \
\r
49 ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \
\r
50 ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \
\r
51 ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \
\r
52 ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \
\r
53 ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))
\r
55 /* DMA data transfer direction -----------------------------------------------*/
\r
56 #define DMA_DIR_PeripheralDST ((u32)0x00000010)
\r
57 #define DMA_DIR_PeripheralSRC ((u32)0x00000000)
\r
59 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
\r
60 ((DIR) == DMA_DIR_PeripheralSRC))
\r
62 /* DMA peripheral incremented mode -------------------------------------------*/
\r
63 #define DMA_PeripheralInc_Enable ((u32)0x00000040)
\r
64 #define DMA_PeripheralInc_Disable ((u32)0x00000000)
\r
66 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
\r
67 ((STATE) == DMA_PeripheralInc_Disable))
\r
69 /* DMA memory incremented mode -----------------------------------------------*/
\r
70 #define DMA_MemoryInc_Enable ((u32)0x00000080)
\r
71 #define DMA_MemoryInc_Disable ((u32)0x00000000)
\r
73 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
\r
74 ((STATE) == DMA_MemoryInc_Disable))
\r
76 /* DMA peripheral data size --------------------------------------------------*/
\r
77 #define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
\r
78 #define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
\r
79 #define DMA_PeripheralDataSize_Word ((u32)0x00000200)
\r
81 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
\r
82 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
\r
83 ((SIZE) == DMA_PeripheralDataSize_Word))
\r
85 /* DMA memory data size ------------------------------------------------------*/
\r
86 #define DMA_MemoryDataSize_Byte ((u32)0x00000000)
\r
87 #define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
\r
88 #define DMA_MemoryDataSize_Word ((u32)0x00000800)
\r
90 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
\r
91 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
\r
92 ((SIZE) == DMA_MemoryDataSize_Word))
\r
94 /* DMA circular/normal mode --------------------------------------------------*/
\r
95 #define DMA_Mode_Circular ((u32)0x00000020)
\r
96 #define DMA_Mode_Normal ((u32)0x00000000)
\r
98 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
\r
100 /* DMA priority level --------------------------------------------------------*/
\r
101 #define DMA_Priority_VeryHigh ((u32)0x00003000)
\r
102 #define DMA_Priority_High ((u32)0x00002000)
\r
103 #define DMA_Priority_Medium ((u32)0x00001000)
\r
104 #define DMA_Priority_Low ((u32)0x00000000)
\r
106 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
\r
107 ((PRIORITY) == DMA_Priority_High) || \
\r
108 ((PRIORITY) == DMA_Priority_Medium) || \
\r
109 ((PRIORITY) == DMA_Priority_Low))
\r
111 /* DMA memory to memory ------------------------------------------------------*/
\r
112 #define DMA_M2M_Enable ((u32)0x00004000)
\r
113 #define DMA_M2M_Disable ((u32)0x00000000)
\r
115 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
\r
117 /* DMA interrupts definition -------------------------------------------------*/
\r
118 #define DMA_IT_TC ((u32)0x00000002)
\r
119 #define DMA_IT_HT ((u32)0x00000004)
\r
120 #define DMA_IT_TE ((u32)0x00000008)
\r
122 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
\r
125 #define DMA1_IT_GL1 ((u32)0x00000001)
\r
126 #define DMA1_IT_TC1 ((u32)0x00000002)
\r
127 #define DMA1_IT_HT1 ((u32)0x00000004)
\r
128 #define DMA1_IT_TE1 ((u32)0x00000008)
\r
129 #define DMA1_IT_GL2 ((u32)0x00000010)
\r
130 #define DMA1_IT_TC2 ((u32)0x00000020)
\r
131 #define DMA1_IT_HT2 ((u32)0x00000040)
\r
132 #define DMA1_IT_TE2 ((u32)0x00000080)
\r
133 #define DMA1_IT_GL3 ((u32)0x00000100)
\r
134 #define DMA1_IT_TC3 ((u32)0x00000200)
\r
135 #define DMA1_IT_HT3 ((u32)0x00000400)
\r
136 #define DMA1_IT_TE3 ((u32)0x00000800)
\r
137 #define DMA1_IT_GL4 ((u32)0x00001000)
\r
138 #define DMA1_IT_TC4 ((u32)0x00002000)
\r
139 #define DMA1_IT_HT4 ((u32)0x00004000)
\r
140 #define DMA1_IT_TE4 ((u32)0x00008000)
\r
141 #define DMA1_IT_GL5 ((u32)0x00010000)
\r
142 #define DMA1_IT_TC5 ((u32)0x00020000)
\r
143 #define DMA1_IT_HT5 ((u32)0x00040000)
\r
144 #define DMA1_IT_TE5 ((u32)0x00080000)
\r
145 #define DMA1_IT_GL6 ((u32)0x00100000)
\r
146 #define DMA1_IT_TC6 ((u32)0x00200000)
\r
147 #define DMA1_IT_HT6 ((u32)0x00400000)
\r
148 #define DMA1_IT_TE6 ((u32)0x00800000)
\r
149 #define DMA1_IT_GL7 ((u32)0x01000000)
\r
150 #define DMA1_IT_TC7 ((u32)0x02000000)
\r
151 #define DMA1_IT_HT7 ((u32)0x04000000)
\r
152 #define DMA1_IT_TE7 ((u32)0x08000000)
\r
154 #define DMA2_IT_GL1 ((u32)0x10000001)
\r
155 #define DMA2_IT_TC1 ((u32)0x10000002)
\r
156 #define DMA2_IT_HT1 ((u32)0x10000004)
\r
157 #define DMA2_IT_TE1 ((u32)0x10000008)
\r
158 #define DMA2_IT_GL2 ((u32)0x10000010)
\r
159 #define DMA2_IT_TC2 ((u32)0x10000020)
\r
160 #define DMA2_IT_HT2 ((u32)0x10000040)
\r
161 #define DMA2_IT_TE2 ((u32)0x10000080)
\r
162 #define DMA2_IT_GL3 ((u32)0x10000100)
\r
163 #define DMA2_IT_TC3 ((u32)0x10000200)
\r
164 #define DMA2_IT_HT3 ((u32)0x10000400)
\r
165 #define DMA2_IT_TE3 ((u32)0x10000800)
\r
166 #define DMA2_IT_GL4 ((u32)0x10001000)
\r
167 #define DMA2_IT_TC4 ((u32)0x10002000)
\r
168 #define DMA2_IT_HT4 ((u32)0x10004000)
\r
169 #define DMA2_IT_TE4 ((u32)0x10008000)
\r
170 #define DMA2_IT_GL5 ((u32)0x10010000)
\r
171 #define DMA2_IT_TC5 ((u32)0x10020000)
\r
172 #define DMA2_IT_HT5 ((u32)0x10040000)
\r
173 #define DMA2_IT_TE5 ((u32)0x10080000)
\r
175 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
\r
176 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
\r
177 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
\r
178 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
\r
179 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
\r
180 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
\r
181 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
\r
182 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
\r
183 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
\r
184 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
\r
185 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
\r
186 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
\r
187 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
\r
188 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
\r
189 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
\r
190 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
\r
191 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
\r
192 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
\r
193 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
\r
194 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
\r
195 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
\r
196 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
\r
197 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
\r
198 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
\r
199 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
\r
201 /* DMA flags definition ------------------------------------------------------*/
\r
203 #define DMA1_FLAG_GL1 ((u32)0x00000001)
\r
204 #define DMA1_FLAG_TC1 ((u32)0x00000002)
\r
205 #define DMA1_FLAG_HT1 ((u32)0x00000004)
\r
206 #define DMA1_FLAG_TE1 ((u32)0x00000008)
\r
207 #define DMA1_FLAG_GL2 ((u32)0x00000010)
\r
208 #define DMA1_FLAG_TC2 ((u32)0x00000020)
\r
209 #define DMA1_FLAG_HT2 ((u32)0x00000040)
\r
210 #define DMA1_FLAG_TE2 ((u32)0x00000080)
\r
211 #define DMA1_FLAG_GL3 ((u32)0x00000100)
\r
212 #define DMA1_FLAG_TC3 ((u32)0x00000200)
\r
213 #define DMA1_FLAG_HT3 ((u32)0x00000400)
\r
214 #define DMA1_FLAG_TE3 ((u32)0x00000800)
\r
215 #define DMA1_FLAG_GL4 ((u32)0x00001000)
\r
216 #define DMA1_FLAG_TC4 ((u32)0x00002000)
\r
217 #define DMA1_FLAG_HT4 ((u32)0x00004000)
\r
218 #define DMA1_FLAG_TE4 ((u32)0x00008000)
\r
219 #define DMA1_FLAG_GL5 ((u32)0x00010000)
\r
220 #define DMA1_FLAG_TC5 ((u32)0x00020000)
\r
221 #define DMA1_FLAG_HT5 ((u32)0x00040000)
\r
222 #define DMA1_FLAG_TE5 ((u32)0x00080000)
\r
223 #define DMA1_FLAG_GL6 ((u32)0x00100000)
\r
224 #define DMA1_FLAG_TC6 ((u32)0x00200000)
\r
225 #define DMA1_FLAG_HT6 ((u32)0x00400000)
\r
226 #define DMA1_FLAG_TE6 ((u32)0x00800000)
\r
227 #define DMA1_FLAG_GL7 ((u32)0x01000000)
\r
228 #define DMA1_FLAG_TC7 ((u32)0x02000000)
\r
229 #define DMA1_FLAG_HT7 ((u32)0x04000000)
\r
230 #define DMA1_FLAG_TE7 ((u32)0x08000000)
\r
232 #define DMA2_FLAG_GL1 ((u32)0x10000001)
\r
233 #define DMA2_FLAG_TC1 ((u32)0x10000002)
\r
234 #define DMA2_FLAG_HT1 ((u32)0x10000004)
\r
235 #define DMA2_FLAG_TE1 ((u32)0x10000008)
\r
236 #define DMA2_FLAG_GL2 ((u32)0x10000010)
\r
237 #define DMA2_FLAG_TC2 ((u32)0x10000020)
\r
238 #define DMA2_FLAG_HT2 ((u32)0x10000040)
\r
239 #define DMA2_FLAG_TE2 ((u32)0x10000080)
\r
240 #define DMA2_FLAG_GL3 ((u32)0x10000100)
\r
241 #define DMA2_FLAG_TC3 ((u32)0x10000200)
\r
242 #define DMA2_FLAG_HT3 ((u32)0x10000400)
\r
243 #define DMA2_FLAG_TE3 ((u32)0x10000800)
\r
244 #define DMA2_FLAG_GL4 ((u32)0x10001000)
\r
245 #define DMA2_FLAG_TC4 ((u32)0x10002000)
\r
246 #define DMA2_FLAG_HT4 ((u32)0x10004000)
\r
247 #define DMA2_FLAG_TE4 ((u32)0x10008000)
\r
248 #define DMA2_FLAG_GL5 ((u32)0x10010000)
\r
249 #define DMA2_FLAG_TC5 ((u32)0x10020000)
\r
250 #define DMA2_FLAG_HT5 ((u32)0x10040000)
\r
251 #define DMA2_FLAG_TE5 ((u32)0x10080000)
\r
253 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
\r
254 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
\r
255 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
\r
256 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
\r
257 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
\r
258 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
\r
259 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
\r
260 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
\r
261 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
\r
262 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
\r
263 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
\r
264 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
\r
265 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
\r
266 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
\r
267 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
\r
268 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
\r
269 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
\r
270 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
\r
271 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
\r
272 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
\r
273 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
\r
274 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
\r
275 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
\r
276 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
\r
277 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
\r
279 /* DMA Buffer Size -----------------------------------------------------------*/
\r
280 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
\r
282 /* Exported macro ------------------------------------------------------------*/
\r
283 /* Exported functions ------------------------------------------------------- */
\r
284 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
\r
285 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
\r
286 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
\r
287 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
\r
288 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);
\r
289 u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
\r
290 FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
\r
291 void DMA_ClearFlag(u32 DMA_FLAG);
\r
292 ITStatus DMA_GetITStatus(u32 DMA_IT);
\r
293 void DMA_ClearITPendingBit(u32 DMA_IT);
\r
295 #endif /*__STM32F10x_DMA_H */
\r
297 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob