1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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2 * File Name : stm32f10x_map.h
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3 * Author : MCD Application Team
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6 * Description : This file contains all the peripheral register's definitions
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7 * and memory mapping.
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8 ********************************************************************************
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9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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15 *******************************************************************************/
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17 /* Define to prevent recursive inclusion -------------------------------------*/
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18 #ifndef __STM32F10x_MAP_H
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19 #define __STM32F10x_MAP_H
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25 /* Includes ------------------------------------------------------------------*/
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26 #include "stm32f10x_conf.h"
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27 #include "stm32f10x_type.h"
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28 #include "cortexm3_macro.h"
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30 /* Exported types ------------------------------------------------------------*/
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31 /******************************************************************************/
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32 /* Peripheral registers structures */
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33 /******************************************************************************/
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35 /*------------------------ Analog to Digital Converter -----------------------*/
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60 /*------------------------ Backup Registers ----------------------------------*/
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156 /*------------------------ Controller Area Network ---------------------------*/
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163 } CAN_TxMailBox_TypeDef;
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171 } CAN_FIFOMailBox_TypeDef;
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177 } CAN_FilterRegister_TypeDef;
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190 CAN_TxMailBox_TypeDef sTxMailBox[3];
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191 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
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202 CAN_FilterRegister_TypeDef sFilterRegister[14];
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205 /*------------------------ CRC calculation unit ------------------------------*/
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216 /*------------------------ Digital to Analog Converter -----------------------*/
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234 /*------------------------ Debug MCU -----------------------------------------*/
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241 /*------------------------ DMA Controller ------------------------------------*/
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248 } DMA_Channel_TypeDef;
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256 /*------------------------ External Interrupt/Event Controller ---------------*/
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267 /*------------------------ FLASH and Option Bytes Registers ------------------*/
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293 /*------------------------ Flexible Static Memory Controller -----------------*/
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297 } FSMC_Bank1_TypeDef;
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302 } FSMC_Bank1E_TypeDef;
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312 } FSMC_Bank2_TypeDef;
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322 } FSMC_Bank3_TypeDef;
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331 } FSMC_Bank4_TypeDef;
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333 /*------------------------ General Purpose and Alternate Function IO ---------*/
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352 /*------------------------ Inter-integrated Circuit Interface ----------------*/
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375 /*------------------------ Independent WATCHDOG ------------------------------*/
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384 /*------------------------ Nested Vectored Interrupt Controller --------------*/
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418 /*------------------------ Power Control -------------------------------------*/
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425 /*------------------------ Reset and Clock Control ---------------------------*/
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440 /*------------------------ Real-Time Clock -----------------------------------*/
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465 /*------------------------ SD host Interface ---------------------------------*/
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490 /*------------------------ Serial Peripheral Interface -----------------------*/
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513 /*------------------------ SystemTick ----------------------------------------*/
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522 /*------------------------ TIM -----------------------------------------------*/
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567 /*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
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586 /*------------------------ Window WATCHDOG -----------------------------------*/
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594 /******************************************************************************/
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595 /* Peripheral memory map */
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596 /******************************************************************************/
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597 /* Peripheral and SRAM base address in the alias region */
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598 #define PERIPH_BB_BASE ((u32)0x42000000)
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599 #define SRAM_BB_BASE ((u32)0x22000000)
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601 /* Peripheral and SRAM base address in the bit-band region */
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602 #define SRAM_BASE ((u32)0x20000000)
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603 #define PERIPH_BASE ((u32)0x40000000)
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605 /* FSMC registers base address */
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606 #define FSMC_R_BASE ((u32)0xA0000000)
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608 /* Peripheral memory map */
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609 #define APB1PERIPH_BASE PERIPH_BASE
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610 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
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611 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
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613 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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614 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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615 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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616 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
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617 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
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618 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
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619 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
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620 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
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621 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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622 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
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623 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
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624 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
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625 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
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626 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
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627 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
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628 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
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629 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
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630 #define CAN_BASE (APB1PERIPH_BASE + 0x6400)
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631 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
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632 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
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633 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
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635 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
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636 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
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637 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
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638 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
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639 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
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640 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
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641 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
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642 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
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643 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
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644 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
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645 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
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646 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
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647 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
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648 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
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649 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
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650 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
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652 #define SDIO_BASE (PERIPH_BASE + 0x18000)
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654 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
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655 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
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656 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
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657 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
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658 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
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659 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
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660 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
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661 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
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662 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
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663 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
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664 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
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665 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
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666 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
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667 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
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668 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
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669 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
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671 /* Flash registers base address */
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672 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
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673 /* Flash Option Bytes base address */
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674 #define OB_BASE ((u32)0x1FFFF800)
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676 /* FSMC Bankx registers base address */
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677 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
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678 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
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679 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
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680 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
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681 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
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683 /* Debug MCU registers base address */
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684 #define DBGMCU_BASE ((u32)0xE0042000)
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686 /* System Control Space memory map */
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687 #define SCS_BASE ((u32)0xE000E000)
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689 #define SysTick_BASE (SCS_BASE + 0x0010)
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690 #define NVIC_BASE (SCS_BASE + 0x0100)
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691 #define SCB_BASE (SCS_BASE + 0x0D00)
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693 /******************************************************************************/
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694 /* Peripheral declaration */
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695 /******************************************************************************/
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697 /*------------------------ Non Debug Mode ------------------------------------*/
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700 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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704 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
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708 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
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712 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
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716 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
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720 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
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724 #define RTC ((RTC_TypeDef *) RTC_BASE)
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728 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
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732 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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736 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
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740 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
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744 #define USART2 ((USART_TypeDef *) USART2_BASE)
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745 #endif /*_USART2 */
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748 #define USART3 ((USART_TypeDef *) USART3_BASE)
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749 #endif /*_USART3 */
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752 #define UART4 ((USART_TypeDef *) UART4_BASE)
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756 #define UART5 ((USART_TypeDef *) UART5_BASE)
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757 #endif /*_USART5 */
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760 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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764 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
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768 #define CAN ((CAN_TypeDef *) CAN_BASE)
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772 #define BKP ((BKP_TypeDef *) BKP_BASE)
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776 #define PWR ((PWR_TypeDef *) PWR_BASE)
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780 #define DAC ((DAC_TypeDef *) DAC_BASE)
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784 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
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788 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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792 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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796 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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800 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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804 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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808 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
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812 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
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816 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
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820 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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824 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
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828 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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832 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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836 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
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840 #define USART1 ((USART_TypeDef *) USART1_BASE)
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841 #endif /*_USART1 */
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844 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
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848 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
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852 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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853 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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856 #ifdef _DMA1_Channel1
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857 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
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858 #endif /*_DMA1_Channel1 */
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860 #ifdef _DMA1_Channel2
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861 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
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862 #endif /*_DMA1_Channel2 */
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864 #ifdef _DMA1_Channel3
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865 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
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866 #endif /*_DMA1_Channel3 */
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868 #ifdef _DMA1_Channel4
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869 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
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870 #endif /*_DMA1_Channel4 */
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872 #ifdef _DMA1_Channel5
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873 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
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874 #endif /*_DMA1_Channel5 */
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876 #ifdef _DMA1_Channel6
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877 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
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878 #endif /*_DMA1_Channel6 */
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880 #ifdef _DMA1_Channel7
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881 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
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882 #endif /*_DMA1_Channel7 */
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884 #ifdef _DMA2_Channel1
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885 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
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886 #endif /*_DMA2_Channel1 */
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888 #ifdef _DMA2_Channel2
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889 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
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890 #endif /*_DMA2_Channel2 */
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892 #ifdef _DMA2_Channel3
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893 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
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894 #endif /*_DMA2_Channel3 */
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896 #ifdef _DMA2_Channel4
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897 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
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898 #endif /*_DMA2_Channel4 */
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900 #ifdef _DMA2_Channel5
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901 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
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902 #endif /*_DMA2_Channel5 */
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905 #define RCC ((RCC_TypeDef *) RCC_BASE)
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909 #define CRC ((CRC_TypeDef *) CRC_BASE)
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913 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
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914 #define OB ((OB_TypeDef *) OB_BASE)
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918 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
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919 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
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920 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
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921 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
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922 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
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926 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
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927 #endif /*_DBGMCU */
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930 #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
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931 #endif /*_SysTick */
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934 #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
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935 #define SCB ((SCB_TypeDef *) SCB_BASE)
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938 /*------------------------ Debug Mode ----------------------------------------*/
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941 EXT TIM_TypeDef *TIM2;
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945 EXT TIM_TypeDef *TIM3;
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949 EXT TIM_TypeDef *TIM4;
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953 EXT TIM_TypeDef *TIM5;
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957 EXT TIM_TypeDef *TIM6;
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961 EXT TIM_TypeDef *TIM7;
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965 EXT RTC_TypeDef *RTC;
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969 EXT WWDG_TypeDef *WWDG;
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973 EXT IWDG_TypeDef *IWDG;
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977 EXT SPI_TypeDef *SPI2;
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981 EXT SPI_TypeDef *SPI3;
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985 EXT USART_TypeDef *USART2;
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986 #endif /*_USART2 */
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989 EXT USART_TypeDef *USART3;
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990 #endif /*_USART3 */
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993 EXT USART_TypeDef *UART4;
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997 EXT USART_TypeDef *UART5;
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1001 EXT I2C_TypeDef *I2C1;
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1005 EXT I2C_TypeDef *I2C2;
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1009 EXT CAN_TypeDef *CAN;
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1013 EXT BKP_TypeDef *BKP;
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1017 EXT PWR_TypeDef *PWR;
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1021 EXT DAC_TypeDef *DAC;
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1025 EXT AFIO_TypeDef *AFIO;
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1029 EXT EXTI_TypeDef *EXTI;
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1033 EXT GPIO_TypeDef *GPIOA;
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1034 #endif /*_GPIOA */
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1037 EXT GPIO_TypeDef *GPIOB;
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1038 #endif /*_GPIOB */
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1041 EXT GPIO_TypeDef *GPIOC;
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1042 #endif /*_GPIOC */
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1045 EXT GPIO_TypeDef *GPIOD;
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1046 #endif /*_GPIOD */
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1049 EXT GPIO_TypeDef *GPIOE;
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1050 #endif /*_GPIOE */
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1053 EXT GPIO_TypeDef *GPIOF;
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1054 #endif /*_GPIOF */
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1057 EXT GPIO_TypeDef *GPIOG;
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1058 #endif /*_GPIOG */
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1061 EXT ADC_TypeDef *ADC1;
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1065 EXT ADC_TypeDef *ADC2;
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1069 EXT TIM_TypeDef *TIM1;
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1073 EXT SPI_TypeDef *SPI1;
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1077 EXT TIM_TypeDef *TIM8;
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1081 EXT USART_TypeDef *USART1;
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1082 #endif /*_USART1 */
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1085 EXT ADC_TypeDef *ADC3;
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1089 EXT SDIO_TypeDef *SDIO;
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1093 EXT DMA_TypeDef *DMA1;
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1094 EXT DMA_TypeDef *DMA2;
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1097 #ifdef _DMA1_Channel1
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1098 EXT DMA_Channel_TypeDef *DMA1_Channel1;
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1099 #endif /*_DMA1_Channel1 */
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1101 #ifdef _DMA1_Channel2
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1102 EXT DMA_Channel_TypeDef *DMA1_Channel2;
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1103 #endif /*_DMA1_Channel2 */
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1105 #ifdef _DMA1_Channel3
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1106 EXT DMA_Channel_TypeDef *DMA1_Channel3;
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1107 #endif /*_DMA1_Channel3 */
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1109 #ifdef _DMA1_Channel4
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1110 EXT DMA_Channel_TypeDef *DMA1_Channel4;
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1111 #endif /*_DMA1_Channel4 */
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1113 #ifdef _DMA1_Channel5
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1114 EXT DMA_Channel_TypeDef *DMA1_Channel5;
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1115 #endif /*_DMA1_Channel5 */
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1117 #ifdef _DMA1_Channel6
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1118 EXT DMA_Channel_TypeDef *DMA1_Channel6;
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1119 #endif /*_DMA1_Channel6 */
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1121 #ifdef _DMA1_Channel7
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1122 EXT DMA_Channel_TypeDef *DMA1_Channel7;
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1123 #endif /*_DMA1_Channel7 */
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1125 #ifdef _DMA2_Channel1
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1126 EXT DMA_Channel_TypeDef *DMA2_Channel1;
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1127 #endif /*_DMA2_Channel1 */
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1129 #ifdef _DMA2_Channel2
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1130 EXT DMA_Channel_TypeDef *DMA2_Channel2;
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1131 #endif /*_DMA2_Channel2 */
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1133 #ifdef _DMA2_Channel3
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1134 EXT DMA_Channel_TypeDef *DMA2_Channel3;
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1135 #endif /*_DMA2_Channel3 */
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1137 #ifdef _DMA2_Channel4
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1138 EXT DMA_Channel_TypeDef *DMA2_Channel4;
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1139 #endif /*_DMA2_Channel4 */
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1141 #ifdef _DMA2_Channel5
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1142 EXT DMA_Channel_TypeDef *DMA2_Channel5;
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1143 #endif /*_DMA2_Channel5 */
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1146 EXT RCC_TypeDef *RCC;
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1150 EXT CRC_TypeDef *CRC;
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1154 EXT FLASH_TypeDef *FLASH;
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1155 EXT OB_TypeDef *OB;
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1156 #endif /*_FLASH */
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1159 EXT FSMC_Bank1_TypeDef *FSMC_Bank1;
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1160 EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E;
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1161 EXT FSMC_Bank2_TypeDef *FSMC_Bank2;
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1162 EXT FSMC_Bank3_TypeDef *FSMC_Bank3;
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1163 EXT FSMC_Bank4_TypeDef *FSMC_Bank4;
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1167 EXT DBGMCU_TypeDef *DBGMCU;
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1168 #endif /*_DBGMCU */
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1171 EXT SysTick_TypeDef *SysTick;
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1172 #endif /*_SysTick */
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1175 EXT NVIC_TypeDef *NVIC;
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1176 EXT SCB_TypeDef *SCB;
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1179 #endif /* DEBUG */
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1181 /* Exported constants --------------------------------------------------------*/
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1182 /* Exported macro ------------------------------------------------------------*/
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1183 /* Exported functions ------------------------------------------------------- */
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1185 #endif /* __STM32F10x_MAP_H */
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1187 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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