1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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2 * File Name : stm32f10x_tim.h
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3 * Author : MCD Application Team
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6 * Description : This file contains all the functions prototypes for the
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7 * TIM firmware library.
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8 ********************************************************************************
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9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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15 *******************************************************************************/
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17 /* Define to prevent recursive inclusion -------------------------------------*/
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18 #ifndef __STM32F10x_TIM_H
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19 #define __STM32F10x_TIM_H
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_map.h"
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24 /* Exported types ------------------------------------------------------------*/
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26 /* TIM Time Base Init structure definition */
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30 u16 TIM_CounterMode;
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32 u16 TIM_ClockDivision;
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33 u8 TIM_RepetitionCounter;
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34 } TIM_TimeBaseInitTypeDef;
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36 /* TIM Output Compare Init structure definition */
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40 u16 TIM_OutputState;
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41 u16 TIM_OutputNState;
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44 u16 TIM_OCNPolarity;
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45 u16 TIM_OCIdleState;
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46 u16 TIM_OCNIdleState;
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47 } TIM_OCInitTypeDef;
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49 /* TIM Input Capture Init structure definition */
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54 u16 TIM_ICSelection;
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55 u16 TIM_ICPrescaler;
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57 } TIM_ICInitTypeDef;
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59 /* BDTR structure definition */
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67 u16 TIM_BreakPolarity;
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68 u16 TIM_AutomaticOutput;
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69 } TIM_BDTRInitTypeDef;
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71 /* Exported constants --------------------------------------------------------*/
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73 #define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
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74 ((*(u32*)&(PERIPH)) == TIM2_BASE) || \
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75 ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
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76 ((*(u32*)&(PERIPH)) == TIM4_BASE) || \
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77 ((*(u32*)&(PERIPH)) == TIM5_BASE) || \
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78 ((*(u32*)&(PERIPH)) == TIM6_BASE) || \
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79 ((*(u32*)&(PERIPH)) == TIM7_BASE) || \
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80 ((*(u32*)&(PERIPH)) == TIM8_BASE))
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82 #define IS_TIM_18_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
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83 ((*(u32*)&(PERIPH)) == TIM8_BASE))
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85 #define IS_TIM_123458_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
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86 ((*(u32*)&(PERIPH)) == TIM2_BASE) || \
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87 ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
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88 ((*(u32*)&(PERIPH)) == TIM4_BASE) || \
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89 ((*(u32*)&(PERIPH)) == TIM5_BASE) || \
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90 ((*(u32*)&(PERIPH)) == TIM8_BASE))
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92 /* TIM Output Compare and PWM modes -----------------------------------------*/
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93 #define TIM_OCMode_Timing ((u16)0x0000)
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94 #define TIM_OCMode_Active ((u16)0x0010)
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95 #define TIM_OCMode_Inactive ((u16)0x0020)
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96 #define TIM_OCMode_Toggle ((u16)0x0030)
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97 #define TIM_OCMode_PWM1 ((u16)0x0060)
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98 #define TIM_OCMode_PWM2 ((u16)0x0070)
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100 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
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101 ((MODE) == TIM_OCMode_Active) || \
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102 ((MODE) == TIM_OCMode_Inactive) || \
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103 ((MODE) == TIM_OCMode_Toggle)|| \
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104 ((MODE) == TIM_OCMode_PWM1) || \
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105 ((MODE) == TIM_OCMode_PWM2))
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107 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
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108 ((MODE) == TIM_OCMode_Active) || \
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109 ((MODE) == TIM_OCMode_Inactive) || \
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110 ((MODE) == TIM_OCMode_Toggle)|| \
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111 ((MODE) == TIM_OCMode_PWM1) || \
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112 ((MODE) == TIM_OCMode_PWM2) || \
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113 ((MODE) == TIM_ForcedAction_Active) || \
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114 ((MODE) == TIM_ForcedAction_InActive))
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115 /* TIM One Pulse Mode -------------------------------------------------------*/
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116 #define TIM_OPMode_Single ((u16)0x0008)
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117 #define TIM_OPMode_Repetitive ((u16)0x0000)
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119 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
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120 ((MODE) == TIM_OPMode_Repetitive))
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122 /* TIM Channel -------------------------------------------------------------*/
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123 #define TIM_Channel_1 ((u16)0x0000)
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124 #define TIM_Channel_2 ((u16)0x0004)
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125 #define TIM_Channel_3 ((u16)0x0008)
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126 #define TIM_Channel_4 ((u16)0x000C)
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128 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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129 ((CHANNEL) == TIM_Channel_2) || \
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130 ((CHANNEL) == TIM_Channel_3) || \
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131 ((CHANNEL) == TIM_Channel_4))
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133 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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134 ((CHANNEL) == TIM_Channel_2))
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136 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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137 ((CHANNEL) == TIM_Channel_2) || \
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138 ((CHANNEL) == TIM_Channel_3))
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139 /* TIM Clock Division CKD --------------------------------------------------*/
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140 #define TIM_CKD_DIV1 ((u16)0x0000)
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141 #define TIM_CKD_DIV2 ((u16)0x0100)
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142 #define TIM_CKD_DIV4 ((u16)0x0200)
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144 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
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145 ((DIV) == TIM_CKD_DIV2) || \
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146 ((DIV) == TIM_CKD_DIV4))
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148 /* TIM Counter Mode --------------------------------------------------------*/
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149 #define TIM_CounterMode_Up ((u16)0x0000)
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150 #define TIM_CounterMode_Down ((u16)0x0010)
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151 #define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
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152 #define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
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153 #define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
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155 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
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156 ((MODE) == TIM_CounterMode_Down) || \
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157 ((MODE) == TIM_CounterMode_CenterAligned1) || \
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158 ((MODE) == TIM_CounterMode_CenterAligned2) || \
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159 ((MODE) == TIM_CounterMode_CenterAligned3))
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161 /* TIM Output Compare Polarity ---------------------------------------------*/
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162 #define TIM_OCPolarity_High ((u16)0x0000)
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163 #define TIM_OCPolarity_Low ((u16)0x0002)
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165 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
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166 ((POLARITY) == TIM_OCPolarity_Low))
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168 /* TIM Output Compare N Polarity -------------------------------------------*/
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169 #define TIM_OCNPolarity_High ((u16)0x0000)
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170 #define TIM_OCNPolarity_Low ((u16)0x0008)
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172 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
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173 ((POLARITY) == TIM_OCNPolarity_Low))
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175 /* TIM Output Compare states -----------------------------------------------*/
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176 #define TIM_OutputState_Disable ((u16)0x0000)
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177 #define TIM_OutputState_Enable ((u16)0x0001)
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179 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
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180 ((STATE) == TIM_OutputState_Enable))
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182 /* TIM Output Compare N States ---------------------------------------------*/
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183 #define TIM_OutputNState_Disable ((u16)0x0000)
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184 #define TIM_OutputNState_Enable ((u16)0x0004)
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186 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
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187 ((STATE) == TIM_OutputNState_Enable))
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189 /* TIM Capture Compare States -----------------------------------------------*/
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190 #define TIM_CCx_Enable ((u16)0x0001)
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191 #define TIM_CCx_Disable ((u16)0x0000)
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193 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
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194 ((CCX) == TIM_CCx_Disable))
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196 /* TIM Capture Compare N States --------------------------------------------*/
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197 #define TIM_CCxN_Enable ((u16)0x0004)
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198 #define TIM_CCxN_Disable ((u16)0x0000)
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200 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
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201 ((CCXN) == TIM_CCxN_Disable))
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203 /* Break Input enable/disable -----------------------------------------------*/
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204 #define TIM_Break_Enable ((u16)0x1000)
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205 #define TIM_Break_Disable ((u16)0x0000)
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207 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
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208 ((STATE) == TIM_Break_Disable))
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210 /* Break Polarity -----------------------------------------------------------*/
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211 #define TIM_BreakPolarity_Low ((u16)0x0000)
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212 #define TIM_BreakPolarity_High ((u16)0x2000)
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214 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
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215 ((POLARITY) == TIM_BreakPolarity_High))
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217 /* TIM AOE Bit Set/Reset ---------------------------------------------------*/
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218 #define TIM_AutomaticOutput_Enable ((u16)0x4000)
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219 #define TIM_AutomaticOutput_Disable ((u16)0x0000)
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221 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
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222 ((STATE) == TIM_AutomaticOutput_Disable))
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223 /* Lock levels --------------------------------------------------------------*/
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224 #define TIM_LOCKLevel_OFF ((u16)0x0000)
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225 #define TIM_LOCKLevel_1 ((u16)0x0100)
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226 #define TIM_LOCKLevel_2 ((u16)0x0200)
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227 #define TIM_LOCKLevel_3 ((u16)0x0300)
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229 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
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230 ((LEVEL) == TIM_LOCKLevel_1) || \
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231 ((LEVEL) == TIM_LOCKLevel_2) || \
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232 ((LEVEL) == TIM_LOCKLevel_3))
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234 /* OSSI: Off-State Selection for Idle mode states ---------------------------*/
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235 #define TIM_OSSIState_Enable ((u16)0x0400)
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236 #define TIM_OSSIState_Disable ((u16)0x0000)
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238 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
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239 ((STATE) == TIM_OSSIState_Disable))
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241 /* OSSR: Off-State Selection for Run mode states ----------------------------*/
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242 #define TIM_OSSRState_Enable ((u16)0x0800)
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243 #define TIM_OSSRState_Disable ((u16)0x0000)
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245 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
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246 ((STATE) == TIM_OSSRState_Disable))
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248 /* TIM Output Compare Idle State -------------------------------------------*/
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249 #define TIM_OCIdleState_Set ((u16)0x0100)
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250 #define TIM_OCIdleState_Reset ((u16)0x0000)
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252 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
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253 ((STATE) == TIM_OCIdleState_Reset))
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255 /* TIM Output Compare N Idle State -----------------------------------------*/
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256 #define TIM_OCNIdleState_Set ((u16)0x0200)
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257 #define TIM_OCNIdleState_Reset ((u16)0x0000)
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259 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
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260 ((STATE) == TIM_OCNIdleState_Reset))
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262 /* TIM Input Capture Polarity ----------------------------------------------*/
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263 #define TIM_ICPolarity_Rising ((u16)0x0000)
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264 #define TIM_ICPolarity_Falling ((u16)0x0002)
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266 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
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267 ((POLARITY) == TIM_ICPolarity_Falling))
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269 /* TIM Input Capture Selection ---------------------------------------------*/
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270 #define TIM_ICSelection_DirectTI ((u16)0x0001)
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271 #define TIM_ICSelection_IndirectTI ((u16)0x0002)
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272 #define TIM_ICSelection_TRC ((u16)0x0003)
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274 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
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275 ((SELECTION) == TIM_ICSelection_IndirectTI) || \
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276 ((SELECTION) == TIM_ICSelection_TRC))
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278 /* TIM Input Capture Prescaler ---------------------------------------------*/
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279 #define TIM_ICPSC_DIV1 ((u16)0x0000)
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280 #define TIM_ICPSC_DIV2 ((u16)0x0004)
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281 #define TIM_ICPSC_DIV4 ((u16)0x0008)
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282 #define TIM_ICPSC_DIV8 ((u16)0x000C)
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284 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
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285 ((PRESCALER) == TIM_ICPSC_DIV2) || \
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286 ((PRESCALER) == TIM_ICPSC_DIV4) || \
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287 ((PRESCALER) == TIM_ICPSC_DIV8))
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289 /* TIM interrupt sources ---------------------------------------------------*/
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290 #define TIM_IT_Update ((u16)0x0001)
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291 #define TIM_IT_CC1 ((u16)0x0002)
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292 #define TIM_IT_CC2 ((u16)0x0004)
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293 #define TIM_IT_CC3 ((u16)0x0008)
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294 #define TIM_IT_CC4 ((u16)0x0010)
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295 #define TIM_IT_COM ((u16)0x0020)
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296 #define TIM_IT_Trigger ((u16)0x0040)
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297 #define TIM_IT_Break ((u16)0x0080)
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299 #define IS_TIM_IT(IT) ((((IT) & (u16)0xFF00) == 0x0000) && ((IT) != 0x0000))
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301 #define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
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302 (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
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303 (((TIM_IT) & (u16)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
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304 (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
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305 (((TIM_IT) & (u16)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
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306 (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
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307 (((TIM_IT) & (u16)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
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309 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
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310 ((IT) == TIM_IT_CC1) || \
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311 ((IT) == TIM_IT_CC2) || \
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312 ((IT) == TIM_IT_CC3) || \
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313 ((IT) == TIM_IT_CC4) || \
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314 ((IT) == TIM_IT_COM) || \
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315 ((IT) == TIM_IT_Trigger) || \
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316 ((IT) == TIM_IT_Break))
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318 /* TIM DMA Base address ----------------------------------------------------*/
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319 #define TIM_DMABase_CR1 ((u16)0x0000)
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320 #define TIM_DMABase_CR2 ((u16)0x0001)
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321 #define TIM_DMABase_SMCR ((u16)0x0002)
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322 #define TIM_DMABase_DIER ((u16)0x0003)
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323 #define TIM_DMABase_SR ((u16)0x0004)
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324 #define TIM_DMABase_EGR ((u16)0x0005)
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325 #define TIM_DMABase_CCMR1 ((u16)0x0006)
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326 #define TIM_DMABase_CCMR2 ((u16)0x0007)
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327 #define TIM_DMABase_CCER ((u16)0x0008)
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328 #define TIM_DMABase_CNT ((u16)0x0009)
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329 #define TIM_DMABase_PSC ((u16)0x000A)
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330 #define TIM_DMABase_ARR ((u16)0x000B)
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331 #define TIM_DMABase_RCR ((u16)0x000C)
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332 #define TIM_DMABase_CCR1 ((u16)0x000D)
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333 #define TIM_DMABase_CCR2 ((u16)0x000E)
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334 #define TIM_DMABase_CCR3 ((u16)0x000F)
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335 #define TIM_DMABase_CCR4 ((u16)0x0010)
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336 #define TIM_DMABase_BDTR ((u16)0x0011)
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337 #define TIM_DMABase_DCR ((u16)0x0012)
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339 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
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340 ((BASE) == TIM_DMABase_CR2) || \
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341 ((BASE) == TIM_DMABase_SMCR) || \
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342 ((BASE) == TIM_DMABase_DIER) || \
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343 ((BASE) == TIM_DMABase_SR) || \
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344 ((BASE) == TIM_DMABase_EGR) || \
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345 ((BASE) == TIM_DMABase_CCMR1) || \
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346 ((BASE) == TIM_DMABase_CCMR2) || \
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347 ((BASE) == TIM_DMABase_CCER) || \
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348 ((BASE) == TIM_DMABase_CNT) || \
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349 ((BASE) == TIM_DMABase_PSC) || \
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350 ((BASE) == TIM_DMABase_ARR) || \
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351 ((BASE) == TIM_DMABase_RCR) || \
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352 ((BASE) == TIM_DMABase_CCR1) || \
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353 ((BASE) == TIM_DMABase_CCR2) || \
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354 ((BASE) == TIM_DMABase_CCR3) || \
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355 ((BASE) == TIM_DMABase_CCR4) || \
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356 ((BASE) == TIM_DMABase_BDTR) || \
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357 ((BASE) == TIM_DMABase_DCR))
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359 /* TIM DMA Burst Length ----------------------------------------------------*/
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360 #define TIM_DMABurstLength_1Byte ((u16)0x0000)
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361 #define TIM_DMABurstLength_2Bytes ((u16)0x0100)
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362 #define TIM_DMABurstLength_3Bytes ((u16)0x0200)
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363 #define TIM_DMABurstLength_4Bytes ((u16)0x0300)
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364 #define TIM_DMABurstLength_5Bytes ((u16)0x0400)
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365 #define TIM_DMABurstLength_6Bytes ((u16)0x0500)
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366 #define TIM_DMABurstLength_7Bytes ((u16)0x0600)
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367 #define TIM_DMABurstLength_8Bytes ((u16)0x0700)
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368 #define TIM_DMABurstLength_9Bytes ((u16)0x0800)
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369 #define TIM_DMABurstLength_10Bytes ((u16)0x0900)
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370 #define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
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371 #define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
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372 #define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
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373 #define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
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374 #define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
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375 #define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
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376 #define TIM_DMABurstLength_17Bytes ((u16)0x1000)
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377 #define TIM_DMABurstLength_18Bytes ((u16)0x1100)
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379 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
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380 ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
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381 ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
\r
382 ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
\r
383 ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
\r
384 ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
\r
385 ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
\r
386 ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
\r
387 ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
\r
388 ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
\r
389 ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
\r
390 ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
\r
391 ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
\r
392 ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
\r
393 ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
\r
394 ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
\r
395 ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
\r
396 ((LENGTH) == TIM_DMABurstLength_18Bytes))
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398 /* TIM DMA sources ---------------------------------------------------------*/
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399 #define TIM_DMA_Update ((u16)0x0100)
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400 #define TIM_DMA_CC1 ((u16)0x0200)
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401 #define TIM_DMA_CC2 ((u16)0x0400)
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402 #define TIM_DMA_CC3 ((u16)0x0800)
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403 #define TIM_DMA_CC4 ((u16)0x1000)
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404 #define TIM_DMA_COM ((u16)0x2000)
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405 #define TIM_DMA_Trigger ((u16)0x4000)
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407 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
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409 #define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
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410 (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
\r
411 (((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
\r
412 (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
\r
413 (((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
\r
414 (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
\r
415 (((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
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417 /* TIM External Trigger Prescaler ------------------------------------------*/
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418 #define TIM_ExtTRGPSC_OFF ((u16)0x0000)
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419 #define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
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420 #define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
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421 #define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
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423 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
\r
424 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
\r
425 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
\r
426 ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
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428 /* TIM Internal Trigger Selection ------------------------------------------*/
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429 #define TIM_TS_ITR0 ((u16)0x0000)
\r
430 #define TIM_TS_ITR1 ((u16)0x0010)
\r
431 #define TIM_TS_ITR2 ((u16)0x0020)
\r
432 #define TIM_TS_ITR3 ((u16)0x0030)
\r
433 #define TIM_TS_TI1F_ED ((u16)0x0040)
\r
434 #define TIM_TS_TI1FP1 ((u16)0x0050)
\r
435 #define TIM_TS_TI2FP2 ((u16)0x0060)
\r
436 #define TIM_TS_ETRF ((u16)0x0070)
\r
438 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
\r
439 ((SELECTION) == TIM_TS_ITR1) || \
\r
440 ((SELECTION) == TIM_TS_ITR2) || \
\r
441 ((SELECTION) == TIM_TS_ITR3) || \
\r
442 ((SELECTION) == TIM_TS_TI1F_ED) || \
\r
443 ((SELECTION) == TIM_TS_TI1FP1) || \
\r
444 ((SELECTION) == TIM_TS_TI2FP2) || \
\r
445 ((SELECTION) == TIM_TS_ETRF))
\r
447 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
\r
448 ((SELECTION) == TIM_TS_ITR1) || \
\r
449 ((SELECTION) == TIM_TS_ITR2) || \
\r
450 ((SELECTION) == TIM_TS_ITR3))
\r
452 /* TIM TIx External Clock Source -------------------------------------------*/
\r
453 #define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
\r
454 #define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
\r
455 #define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
\r
457 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
\r
458 ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
\r
459 ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
\r
461 /* TIM External Trigger Polarity -------------------------------------------*/
\r
462 #define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
\r
463 #define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
\r
465 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
\r
466 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
\r
468 /* TIM Prescaler Reload Mode -----------------------------------------------*/
\r
469 #define TIM_PSCReloadMode_Update ((u16)0x0000)
\r
470 #define TIM_PSCReloadMode_Immediate ((u16)0x0001)
\r
472 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
\r
473 ((RELOAD) == TIM_PSCReloadMode_Immediate))
\r
475 /* TIM Forced Action -------------------------------------------------------*/
\r
476 #define TIM_ForcedAction_Active ((u16)0x0050)
\r
477 #define TIM_ForcedAction_InActive ((u16)0x0040)
\r
479 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
\r
480 ((ACTION) == TIM_ForcedAction_InActive))
\r
482 /* TIM Encoder Mode --------------------------------------------------------*/
\r
483 #define TIM_EncoderMode_TI1 ((u16)0x0001)
\r
484 #define TIM_EncoderMode_TI2 ((u16)0x0002)
\r
485 #define TIM_EncoderMode_TI12 ((u16)0x0003)
\r
487 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
\r
488 ((MODE) == TIM_EncoderMode_TI2) || \
\r
489 ((MODE) == TIM_EncoderMode_TI12))
\r
491 /* TIM Event Source --------------------------------------------------------*/
\r
492 #define TIM_EventSource_Update ((u16)0x0001)
\r
493 #define TIM_EventSource_CC1 ((u16)0x0002)
\r
494 #define TIM_EventSource_CC2 ((u16)0x0004)
\r
495 #define TIM_EventSource_CC3 ((u16)0x0008)
\r
496 #define TIM_EventSource_CC4 ((u16)0x0010)
\r
497 #define TIM_EventSource_COM ((u16)0x0020)
\r
498 #define TIM_EventSource_Trigger ((u16)0x0040)
\r
499 #define TIM_EventSource_Break ((u16)0x0080)
\r
501 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
\r
503 #define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
\r
504 (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
\r
505 (((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
\r
506 (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
\r
507 (((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
\r
508 (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
\r
509 (((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
\r
511 /* TIM Update Source --------------------------------------------------------*/
\r
512 #define TIM_UpdateSource_Global ((u16)0x0000)
\r
513 #define TIM_UpdateSource_Regular ((u16)0x0001)
\r
515 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
\r
516 ((SOURCE) == TIM_UpdateSource_Regular))
\r
518 /* TIM Ouput Compare Preload State ------------------------------------------*/
\r
519 #define TIM_OCPreload_Enable ((u16)0x0008)
\r
520 #define TIM_OCPreload_Disable ((u16)0x0000)
\r
522 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
\r
523 ((STATE) == TIM_OCPreload_Disable))
\r
525 /* TIM Ouput Compare Fast State ---------------------------------------------*/
\r
526 #define TIM_OCFast_Enable ((u16)0x0004)
\r
527 #define TIM_OCFast_Disable ((u16)0x0000)
\r
529 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
\r
530 ((STATE) == TIM_OCFast_Disable))
\r
532 /* TIM Ouput Compare Clear State --------------------------------------------*/
\r
533 #define TIM_OCClear_Enable ((u16)0x0080)
\r
534 #define TIM_OCClear_Disable ((u16)0x0000)
\r
536 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
\r
537 ((STATE) == TIM_OCClear_Disable))
\r
539 /* TIM Trigger Output Source ------------------------------------------------*/
\r
540 #define TIM_TRGOSource_Reset ((u16)0x0000)
\r
541 #define TIM_TRGOSource_Enable ((u16)0x0010)
\r
542 #define TIM_TRGOSource_Update ((u16)0x0020)
\r
543 #define TIM_TRGOSource_OC1 ((u16)0x0030)
\r
544 #define TIM_TRGOSource_OC1Ref ((u16)0x0040)
\r
545 #define TIM_TRGOSource_OC2Ref ((u16)0x0050)
\r
546 #define TIM_TRGOSource_OC3Ref ((u16)0x0060)
\r
547 #define TIM_TRGOSource_OC4Ref ((u16)0x0070)
\r
549 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
\r
550 ((SOURCE) == TIM_TRGOSource_Enable) || \
\r
551 ((SOURCE) == TIM_TRGOSource_Update) || \
\r
552 ((SOURCE) == TIM_TRGOSource_OC1) || \
\r
553 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
\r
554 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
\r
555 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
\r
556 ((SOURCE) == TIM_TRGOSource_OC4Ref))
\r
558 #define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
559 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
560 (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
\r
561 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
562 ((TRGO) == TIM_TRGOSource_Reset)) ||\
\r
563 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
564 (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
\r
565 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
566 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
567 ((TRGO) == TIM_TRGOSource_Enable)) ||\
\r
568 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
569 (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
\r
570 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
571 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
572 ((TRGO) == TIM_TRGOSource_Update)) ||\
\r
573 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
574 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
575 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
576 ((TRGO) == TIM_TRGOSource_OC1)) ||\
\r
577 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
578 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
579 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
580 ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
\r
581 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
582 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
583 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
584 ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
\r
585 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
586 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
587 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
588 ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\
\r
589 ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
\r
590 (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
\r
591 (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
\r
592 ((TRGO) == TIM_TRGOSource_OC4Ref)))
\r
594 /* TIM Slave Mode ----------------------------------------------------------*/
\r
595 #define TIM_SlaveMode_Reset ((u16)0x0004)
\r
596 #define TIM_SlaveMode_Gated ((u16)0x0005)
\r
597 #define TIM_SlaveMode_Trigger ((u16)0x0006)
\r
598 #define TIM_SlaveMode_External1 ((u16)0x0007)
\r
600 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
\r
601 ((MODE) == TIM_SlaveMode_Gated) || \
\r
602 ((MODE) == TIM_SlaveMode_Trigger) || \
\r
603 ((MODE) == TIM_SlaveMode_External1))
\r
605 /* TIM Master Slave Mode ---------------------------------------------------*/
\r
606 #define TIM_MasterSlaveMode_Enable ((u16)0x0080)
\r
607 #define TIM_MasterSlaveMode_Disable ((u16)0x0000)
\r
609 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
\r
610 ((STATE) == TIM_MasterSlaveMode_Disable))
\r
612 /* TIM Flags ---------------------------------------------------------------*/
\r
613 #define TIM_FLAG_Update ((u16)0x0001)
\r
614 #define TIM_FLAG_CC1 ((u16)0x0002)
\r
615 #define TIM_FLAG_CC2 ((u16)0x0004)
\r
616 #define TIM_FLAG_CC3 ((u16)0x0008)
\r
617 #define TIM_FLAG_CC4 ((u16)0x0010)
\r
618 #define TIM_FLAG_COM ((u16)0x0020)
\r
619 #define TIM_FLAG_Trigger ((u16)0x0040)
\r
620 #define TIM_FLAG_Break ((u16)0x0080)
\r
621 #define TIM_FLAG_CC1OF ((u16)0x0200)
\r
622 #define TIM_FLAG_CC2OF ((u16)0x0400)
\r
623 #define TIM_FLAG_CC3OF ((u16)0x0800)
\r
624 #define TIM_FLAG_CC4OF ((u16)0x1000)
\r
626 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
\r
627 ((FLAG) == TIM_FLAG_CC1) || \
\r
628 ((FLAG) == TIM_FLAG_CC2) || \
\r
629 ((FLAG) == TIM_FLAG_CC3) || \
\r
630 ((FLAG) == TIM_FLAG_CC4) || \
\r
631 ((FLAG) == TIM_FLAG_COM) || \
\r
632 ((FLAG) == TIM_FLAG_Trigger) || \
\r
633 ((FLAG) == TIM_FLAG_Break) || \
\r
634 ((FLAG) == TIM_FLAG_CC1OF) || \
\r
635 ((FLAG) == TIM_FLAG_CC2OF) || \
\r
636 ((FLAG) == TIM_FLAG_CC3OF) || \
\r
637 ((FLAG) == TIM_FLAG_CC4OF))
\r
639 #define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
\r
640 (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
\r
641 (((TIM_FLAG) & (u16)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
\r
642 (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
\r
643 (((TIM_FLAG) & (u16)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
\r
644 (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
\r
645 (((TIM_FLAG) & (u16)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
\r
647 #define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) ||\
\r
648 ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
\r
649 ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
\r
650 (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\
\r
651 ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \
\r
652 ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\
\r
653 ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
\r
654 ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) ||\
\r
655 ((*(u32*)&(PERIPH))==TIM1_BASE)|| ((*(u32*)&(PERIPH))==TIM8_BASE) || \
\r
656 ((*(u32*)&(PERIPH))==TIM7_BASE) || ((*(u32*)&(PERIPH))==TIM6_BASE)) && \
\r
657 (((TIM_FLAG) == TIM_FLAG_Update))) ||\
\r
658 ((((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) &&\
\r
659 (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\
\r
660 ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
\r
661 ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
\r
662 ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
\r
663 (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\
\r
664 ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
\r
666 /* TIM Input Capture Filer Value ---------------------------------------------*/
\r
667 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
\r
669 /* TIM External Trigger Filter -----------------------------------------------*/
\r
670 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
\r
672 /* Exported macro ------------------------------------------------------------*/
\r
673 /* Exported functions --------------------------------------------------------*/
\r
675 void TIM_DeInit(TIM_TypeDef* TIMx);
\r
676 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
\r
677 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
678 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
679 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
680 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
681 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
682 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
683 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
\r
684 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
\r
685 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
686 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
687 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
\r
688 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
689 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
690 void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
\r
691 void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
\r
692 void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
\r
693 void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState);
\r
694 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
\r
695 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
\r
696 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
\r
697 u16 TIM_ICPolarity, u16 ICFilter);
\r
698 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
\r
700 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
\r
701 u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter);
\r
702 void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
\r
704 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
\r
705 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
\r
706 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
\r
707 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
\r
708 u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
\r
709 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
710 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
711 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
712 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
713 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
714 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
715 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
716 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
717 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
718 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
719 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
720 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
721 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
722 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
723 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
724 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
725 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
\r
726 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
\r
727 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
\r
728 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
\r
729 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
730 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
\r
731 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
732 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
\r
733 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
734 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
\r
735 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
736 void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx);
\r
737 void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN);
\r
738 void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode);
\r
739 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
740 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
\r
741 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
742 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
\r
743 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
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744 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
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745 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
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746 void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter);
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747 void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
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748 void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
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749 void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
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750 void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
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751 void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
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752 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
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753 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
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754 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
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755 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
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756 void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
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757 u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
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758 u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
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759 u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
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760 u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
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761 u16 TIM_GetCounter(TIM_TypeDef* TIMx);
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762 u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
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763 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
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764 void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
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765 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
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766 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
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768 #endif /*__STM32F10x_TIM_H */
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770 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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projects / freertos / blob