1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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2 * File Name : stm32f10x_rcc.c
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3 * Author : MCD Application Team
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6 * Description : This file provides all the RCC firmware functions.
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7 ********************************************************************************
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8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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14 *******************************************************************************/
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16 /* Includes ------------------------------------------------------------------*/
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17 #include "stm32f10x_rcc.h"
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19 /* Private typedef -----------------------------------------------------------*/
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20 /* Private define ------------------------------------------------------------*/
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21 /* ------------ RCC registers bit address in the alias region ----------- */
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22 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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24 /* --- CR Register ---*/
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25 /* Alias word address of HSION bit */
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26 #define CR_OFFSET (RCC_OFFSET + 0x00)
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27 #define HSION_BitNumber 0x00
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28 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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30 /* Alias word address of PLLON bit */
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31 #define PLLON_BitNumber 0x18
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32 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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34 /* Alias word address of CSSON bit */
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35 #define CSSON_BitNumber 0x13
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36 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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38 /* --- CFGR Register ---*/
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39 /* Alias word address of USBPRE bit */
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40 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
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41 #define USBPRE_BitNumber 0x16
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42 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
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44 /* --- BDCR Register ---*/
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45 /* Alias word address of RTCEN bit */
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46 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
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47 #define RTCEN_BitNumber 0x0F
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48 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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50 /* Alias word address of BDRST bit */
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51 #define BDRST_BitNumber 0x10
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52 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
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54 /* --- CSR Register ---*/
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55 /* Alias word address of LSION bit */
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56 #define CSR_OFFSET (RCC_OFFSET + 0x24)
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57 #define LSION_BitNumber 0x00
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58 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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60 /* ---------------------- RCC registers bit mask ------------------------ */
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61 /* CR register bit mask */
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62 #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
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63 #define CR_HSEBYP_Set ((u32)0x00040000)
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64 #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
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65 #define CR_HSEON_Set ((u32)0x00010000)
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66 #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
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68 /* CFGR register bit mask */
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69 #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
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70 #define CFGR_PLLMull_Mask ((u32)0x003C0000)
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71 #define CFGR_PLLSRC_Mask ((u32)0x00010000)
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72 #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
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73 #define CFGR_SWS_Mask ((u32)0x0000000C)
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74 #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
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75 #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
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76 #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
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77 #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
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78 #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
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79 #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
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80 #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
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81 #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
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82 #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
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84 /* CSR register bit mask */
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85 #define CSR_RMVF_Set ((u32)0x01000000)
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88 #define FLAG_Mask ((u8)0x1F)
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90 /* Typical Value of the HSI in Hz */
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91 #define HSI_Value ((u32)8000000)
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93 /* CIR register byte 2 (Bits[15:8]) base address */
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94 #define CIR_BYTE2_ADDRESS ((u32)0x40021009)
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95 /* CIR register byte 3 (Bits[23:16]) base address */
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96 #define CIR_BYTE3_ADDRESS ((u32)0x4002100A)
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98 /* CFGR register byte 4 (Bits[31:24]) base address */
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99 #define CFGR_BYTE4_ADDRESS ((u32)0x40021007)
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101 /* BDCR register base address */
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102 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
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104 /* Time out for HSE start up */
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105 #define HSEStartUp_TimeOut ((u16)0x01FF)
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107 /* Private macro -------------------------------------------------------------*/
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108 /* Private variables ---------------------------------------------------------*/
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109 static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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110 static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
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112 static volatile FlagStatus HSEStatus;
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113 static vu32 StartUpCounter = 0;
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115 /* Private function prototypes -----------------------------------------------*/
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116 /* Private functions ---------------------------------------------------------*/
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118 /*******************************************************************************
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119 * Function Name : RCC_DeInit
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120 * Description : Resets the RCC clock configuration to the default reset state.
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124 *******************************************************************************/
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125 void RCC_DeInit(void)
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127 /* Set HSION bit */
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128 RCC->CR |= (u32)0x00000001;
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130 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
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131 RCC->CFGR &= (u32)0xF8FF0000;
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133 /* Reset HSEON, CSSON and PLLON bits */
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134 RCC->CR &= (u32)0xFEF6FFFF;
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136 /* Reset HSEBYP bit */
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137 RCC->CR &= (u32)0xFFFBFFFF;
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139 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
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140 RCC->CFGR &= (u32)0xFF80FFFF;
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142 /* Disable all interrupts */
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143 RCC->CIR = 0x00000000;
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146 /*******************************************************************************
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147 * Function Name : RCC_HSEConfig
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148 * Description : Configures the External High Speed oscillator (HSE).
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149 * HSE can not be stopped if it is used directly or through the
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150 * PLL as system clock.
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151 * Input : - RCC_HSE: specifies the new state of the HSE.
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152 * This parameter can be one of the following values:
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153 * - RCC_HSE_OFF: HSE oscillator OFF
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154 * - RCC_HSE_ON: HSE oscillator ON
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155 * - RCC_HSE_Bypass: HSE oscillator bypassed with external
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159 *******************************************************************************/
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160 void RCC_HSEConfig(u32 RCC_HSE)
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162 /* Check the parameters */
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163 assert_param(IS_RCC_HSE(RCC_HSE));
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165 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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166 /* Reset HSEON bit */
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167 RCC->CR &= CR_HSEON_Reset;
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169 /* Reset HSEBYP bit */
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170 RCC->CR &= CR_HSEBYP_Reset;
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172 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
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176 /* Set HSEON bit */
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177 RCC->CR |= CR_HSEON_Set;
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180 case RCC_HSE_Bypass:
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181 /* Set HSEBYP and HSEON bits */
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182 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
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190 /*******************************************************************************
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191 * Function Name : RCC_WaitForHSEStartUp
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192 * Description : Waits for HSE start-up.
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195 * Return : An ErrorStatus enumuration value:
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196 * - SUCCESS: HSE oscillator is stable and ready to use
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197 * - ERROR: HSE oscillator not yet ready
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198 *******************************************************************************/
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199 ErrorStatus RCC_WaitForHSEStartUp(void)
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201 ErrorStatus status = ERROR;
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203 /* Wait till HSE is ready and if Time out is reached exit */
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206 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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208 } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
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211 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
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223 /*******************************************************************************
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224 * Function Name : RCC_AdjustHSICalibrationValue
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225 * Description : Adjusts the Internal High Speed oscillator (HSI) calibration
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227 * Input : - HSICalibrationValue: specifies the calibration trimming value.
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228 * This parameter must be a number between 0 and 0x1F.
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231 *******************************************************************************/
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232 void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
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236 /* Check the parameters */
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237 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
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241 /* Clear HSITRIM[4:0] bits */
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242 tmpreg &= CR_HSITRIM_Mask;
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244 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
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245 tmpreg |= (u32)HSICalibrationValue << 3;
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247 /* Store the new value */
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251 /*******************************************************************************
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252 * Function Name : RCC_HSICmd
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253 * Description : Enables or disables the Internal High Speed oscillator (HSI).
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254 * HSI can not be stopped if it is used directly or through the
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255 * PLL as system clock.
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256 * Input : - NewState: new state of the HSI.
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257 * This parameter can be: ENABLE or DISABLE.
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260 *******************************************************************************/
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261 void RCC_HSICmd(FunctionalState NewState)
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263 /* Check the parameters */
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264 assert_param(IS_FUNCTIONAL_STATE(NewState));
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266 *(vu32 *) CR_HSION_BB = (u32)NewState;
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269 /*******************************************************************************
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270 * Function Name : RCC_PLLConfig
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271 * Description : Configures the PLL clock source and multiplication factor.
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272 * This function must be used only when the PLL is disabled.
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273 * Input : - RCC_PLLSource: specifies the PLL entry clock source.
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274 * This parameter can be one of the following values:
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275 * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
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276 * by 2 selected as PLL clock entry
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277 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
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278 * as PLL clock entry
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279 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
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280 * by 2 selected as PLL clock entry
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281 * - RCC_PLLMul: specifies the PLL multiplication factor.
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282 * This parameter can be RCC_PLLMul_x where x:[2,16]
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285 *******************************************************************************/
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286 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
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290 /* Check the parameters */
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291 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
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292 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
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294 tmpreg = RCC->CFGR;
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296 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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297 tmpreg &= CFGR_PLL_Mask;
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299 /* Set the PLL configuration bits */
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300 tmpreg |= RCC_PLLSource | RCC_PLLMul;
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302 /* Store the new value */
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303 RCC->CFGR = tmpreg;
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306 /*******************************************************************************
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307 * Function Name : RCC_PLLCmd
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308 * Description : Enables or disables the PLL.
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309 * The PLL can not be disabled if it is used as system clock.
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310 * Input : - NewState: new state of the PLL.
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311 * This parameter can be: ENABLE or DISABLE.
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314 *******************************************************************************/
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315 void RCC_PLLCmd(FunctionalState NewState)
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317 /* Check the parameters */
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318 assert_param(IS_FUNCTIONAL_STATE(NewState));
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320 *(vu32 *) CR_PLLON_BB = (u32)NewState;
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323 /*******************************************************************************
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324 * Function Name : RCC_SYSCLKConfig
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325 * Description : Configures the system clock (SYSCLK).
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326 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
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327 * clock. This parameter can be one of the following values:
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328 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
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329 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
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330 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
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333 *******************************************************************************/
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334 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
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338 /* Check the parameters */
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339 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
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341 tmpreg = RCC->CFGR;
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343 /* Clear SW[1:0] bits */
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344 tmpreg &= CFGR_SW_Mask;
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346 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
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347 tmpreg |= RCC_SYSCLKSource;
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349 /* Store the new value */
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350 RCC->CFGR = tmpreg;
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353 /*******************************************************************************
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354 * Function Name : RCC_GetSYSCLKSource
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355 * Description : Returns the clock source used as system clock.
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358 * Return : The clock source used as system clock. The returned value can
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359 * be one of the following:
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360 * - 0x00: HSI used as system clock
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361 * - 0x04: HSE used as system clock
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362 * - 0x08: PLL used as system clock
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363 *******************************************************************************/
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364 u8 RCC_GetSYSCLKSource(void)
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366 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
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369 /*******************************************************************************
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370 * Function Name : RCC_HCLKConfig
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371 * Description : Configures the AHB clock (HCLK).
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372 * Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is
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373 * derived from the system clock (SYSCLK).
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374 * This parameter can be one of the following values:
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375 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
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376 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
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377 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
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378 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
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379 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
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380 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
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381 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
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382 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
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383 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
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386 *******************************************************************************/
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387 void RCC_HCLKConfig(u32 RCC_SYSCLK)
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391 /* Check the parameters */
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392 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
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394 tmpreg = RCC->CFGR;
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396 /* Clear HPRE[3:0] bits */
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397 tmpreg &= CFGR_HPRE_Reset_Mask;
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399 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
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400 tmpreg |= RCC_SYSCLK;
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402 /* Store the new value */
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403 RCC->CFGR = tmpreg;
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406 /*******************************************************************************
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407 * Function Name : RCC_PCLK1Config
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408 * Description : Configures the Low Speed APB clock (PCLK1).
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409 * Input : - RCC_HCLK: defines the APB1 clock divider. This clock is
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410 * derived from the AHB clock (HCLK).
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411 * This parameter can be one of the following values:
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412 * - RCC_HCLK_Div1: APB1 clock = HCLK
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413 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
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414 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
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415 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
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416 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
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419 *******************************************************************************/
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420 void RCC_PCLK1Config(u32 RCC_HCLK)
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424 /* Check the parameters */
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425 assert_param(IS_RCC_PCLK(RCC_HCLK));
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427 tmpreg = RCC->CFGR;
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429 /* Clear PPRE1[2:0] bits */
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430 tmpreg &= CFGR_PPRE1_Reset_Mask;
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432 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
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433 tmpreg |= RCC_HCLK;
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435 /* Store the new value */
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436 RCC->CFGR = tmpreg;
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439 /*******************************************************************************
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440 * Function Name : RCC_PCLK2Config
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441 * Description : Configures the High Speed APB clock (PCLK2).
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442 * Input : - RCC_HCLK: defines the APB2 clock divider. This clock is
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443 * derived from the AHB clock (HCLK).
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444 * This parameter can be one of the following values:
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445 * - RCC_HCLK_Div1: APB2 clock = HCLK
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446 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
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447 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
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448 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
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449 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
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452 *******************************************************************************/
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453 void RCC_PCLK2Config(u32 RCC_HCLK)
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457 /* Check the parameters */
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458 assert_param(IS_RCC_PCLK(RCC_HCLK));
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460 tmpreg = RCC->CFGR;
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462 /* Clear PPRE2[2:0] bits */
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463 tmpreg &= CFGR_PPRE2_Reset_Mask;
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465 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
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466 tmpreg |= RCC_HCLK << 3;
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468 /* Store the new value */
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469 RCC->CFGR = tmpreg;
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472 /*******************************************************************************
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473 * Function Name : RCC_ITConfig
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474 * Description : Enables or disables the specified RCC interrupts.
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475 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
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477 * This parameter can be any combination of the following values:
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478 * - RCC_IT_LSIRDY: LSI ready interrupt
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479 * - RCC_IT_LSERDY: LSE ready interrupt
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480 * - RCC_IT_HSIRDY: HSI ready interrupt
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481 * - RCC_IT_HSERDY: HSE ready interrupt
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482 * - RCC_IT_PLLRDY: PLL ready interrupt
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483 * - NewState: new state of the specified RCC interrupts.
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484 * This parameter can be: ENABLE or DISABLE.
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487 *******************************************************************************/
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488 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
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490 /* Check the parameters */
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491 assert_param(IS_RCC_IT(RCC_IT));
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492 assert_param(IS_FUNCTIONAL_STATE(NewState));
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494 if (NewState != DISABLE)
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496 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
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497 *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
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501 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
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502 *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
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506 /*******************************************************************************
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507 * Function Name : RCC_USBCLKConfig
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508 * Description : Configures the USB clock (USBCLK).
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509 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
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510 * is derived from the PLL output.
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511 * This parameter can be one of the following values:
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512 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
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513 * selected as USB clock source
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514 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
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518 *******************************************************************************/
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519 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
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521 /* Check the parameters */
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522 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
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524 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
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527 /*******************************************************************************
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528 * Function Name : RCC_ADCCLKConfig
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529 * Description : Configures the ADC clock (ADCCLK).
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530 * Input : - RCC_PCLK2: defines the ADC clock divider. This clock is
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531 * derived from the APB2 clock (PCLK2).
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532 * This parameter can be one of the following values:
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533 * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
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534 * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
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535 * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
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536 * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
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539 *******************************************************************************/
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540 void RCC_ADCCLKConfig(u32 RCC_PCLK2)
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544 /* Check the parameters */
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545 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
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547 tmpreg = RCC->CFGR;
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549 /* Clear ADCPRE[1:0] bits */
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550 tmpreg &= CFGR_ADCPRE_Reset_Mask;
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552 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
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553 tmpreg |= RCC_PCLK2;
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555 /* Store the new value */
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556 RCC->CFGR = tmpreg;
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559 /*******************************************************************************
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560 * Function Name : RCC_LSEConfig
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561 * Description : Configures the External Low Speed oscillator (LSE).
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562 * Input : - RCC_LSE: specifies the new state of the LSE.
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563 * This parameter can be one of the following values:
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564 * - RCC_LSE_OFF: LSE oscillator OFF
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565 * - RCC_LSE_ON: LSE oscillator ON
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566 * - RCC_LSE_Bypass: LSE oscillator bypassed with external
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570 *******************************************************************************/
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571 void RCC_LSEConfig(u8 RCC_LSE)
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573 /* Check the parameters */
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574 assert_param(IS_RCC_LSE(RCC_LSE));
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576 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
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577 /* Reset LSEON bit */
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578 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
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580 /* Reset LSEBYP bit */
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581 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
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583 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
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587 /* Set LSEON bit */
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588 *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
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591 case RCC_LSE_Bypass:
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592 /* Set LSEBYP and LSEON bits */
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593 *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
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601 /*******************************************************************************
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602 * Function Name : RCC_LSICmd
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603 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
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604 * LSI can not be disabled if the IWDG is running.
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605 * Input : - NewState: new state of the LSI.
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606 * This parameter can be: ENABLE or DISABLE.
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609 *******************************************************************************/
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610 void RCC_LSICmd(FunctionalState NewState)
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612 /* Check the parameters */
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613 assert_param(IS_FUNCTIONAL_STATE(NewState));
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615 *(vu32 *) CSR_LSION_BB = (u32)NewState;
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618 /*******************************************************************************
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619 * Function Name : RCC_RTCCLKConfig
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620 * Description : Configures the RTC clock (RTCCLK).
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621 * Once the RTC clock is selected it can
\92t be changed unless the
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622 * Backup domain is reset.
\r
623 * Input : - RCC_RTCCLKSource: specifies the RTC clock source.
\r
624 * This parameter can be one of the following values:
\r
625 * - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
\r
626 * - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
\r
627 * - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
\r
628 * selected as RTC clock
\r
631 *******************************************************************************/
\r
632 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
\r
634 /* Check the parameters */
\r
635 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
\r
637 /* Select the RTC clock source */
\r
638 RCC->BDCR |= RCC_RTCCLKSource;
\r
641 /*******************************************************************************
\r
642 * Function Name : RCC_RTCCLKCmd
\r
643 * Description : Enables or disables the RTC clock.
\r
644 * This function must be used only after the RTC clock was
\r
645 * selected using the RCC_RTCCLKConfig function.
\r
646 * Input : - NewState: new state of the RTC clock.
\r
647 * This parameter can be: ENABLE or DISABLE.
\r
650 *******************************************************************************/
\r
651 void RCC_RTCCLKCmd(FunctionalState NewState)
\r
653 /* Check the parameters */
\r
654 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
656 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
\r
659 /*******************************************************************************
\r
660 * Function Name : RCC_GetClocksFreq
\r
661 * Description : Returns the frequencies of different on chip clocks.
\r
662 * Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
\r
663 * will hold the clocks frequencies.
\r
666 *******************************************************************************/
\r
667 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
\r
669 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
\r
671 /* Get SYSCLK source -------------------------------------------------------*/
\r
672 tmp = RCC->CFGR & CFGR_SWS_Mask;
\r
676 case 0x00: /* HSI used as system clock */
\r
677 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\r
680 case 0x04: /* HSE used as system clock */
\r
681 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
\r
684 case 0x08: /* PLL used as system clock */
\r
685 /* Get PLL clock source and multiplication factor ----------------------*/
\r
686 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
\r
687 pllmull = ( pllmull >> 18) + 2;
\r
689 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
\r
691 if (pllsource == 0x00)
\r
692 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
\r
693 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
\r
696 {/* HSE selected as PLL clock entry */
\r
698 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
\r
699 {/* HSE oscillator clock divided by 2 */
\r
701 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
\r
705 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
\r
711 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\r
715 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
\r
716 /* Get HCLK prescaler */
\r
717 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
\r
719 presc = APBAHBPrescTable[tmp];
\r
721 /* HCLK clock frequency */
\r
722 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
\r
724 /* Get PCLK1 prescaler */
\r
725 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
\r
727 presc = APBAHBPrescTable[tmp];
\r
729 /* PCLK1 clock frequency */
\r
730 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
732 /* Get PCLK2 prescaler */
\r
733 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
\r
735 presc = APBAHBPrescTable[tmp];
\r
737 /* PCLK2 clock frequency */
\r
738 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
740 /* Get ADCCLK prescaler */
\r
741 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
\r
743 presc = ADCPrescTable[tmp];
\r
745 /* ADCCLK clock frequency */
\r
746 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
\r
749 /*******************************************************************************
\r
750 * Function Name : RCC_AHBPeriphClockCmd
\r
751 * Description : Enables or disables the AHB peripheral clock.
\r
752 * Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
\r
753 * This parameter can be any combination of the following values:
\r
754 * - RCC_AHBPeriph_DMA1
\r
755 * - RCC_AHBPeriph_DMA2
\r
756 * - RCC_AHBPeriph_SRAM
\r
757 * - RCC_AHBPeriph_FLITF
\r
758 * - RCC_AHBPeriph_CRC
\r
759 * - RCC_AHBPeriph_FSMC
\r
760 * - RCC_AHBPeriph_SDIO
\r
761 * SRAM and FLITF clock can be disabled only during sleep mode.
\r
762 * - NewState: new state of the specified peripheral clock.
\r
763 * This parameter can be: ENABLE or DISABLE.
\r
766 *******************************************************************************/
\r
767 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
\r
769 /* Check the parameters */
\r
770 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
\r
771 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
773 if (NewState != DISABLE)
\r
775 RCC->AHBENR |= RCC_AHBPeriph;
\r
779 RCC->AHBENR &= ~RCC_AHBPeriph;
\r
783 /*******************************************************************************
\r
784 * Function Name : RCC_APB2PeriphClockCmd
\r
785 * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
\r
786 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
\r
788 * This parameter can be any combination of the following values:
\r
789 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
\r
790 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
\r
791 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
\r
792 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
\r
793 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
\r
794 * RCC_APB2Periph_ALL
\r
795 * - NewState: new state of the specified peripheral clock.
\r
796 * This parameter can be: ENABLE or DISABLE.
\r
799 *******************************************************************************/
\r
800 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
\r
802 /* Check the parameters */
\r
803 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
804 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
806 if (NewState != DISABLE)
\r
808 RCC->APB2ENR |= RCC_APB2Periph;
\r
812 RCC->APB2ENR &= ~RCC_APB2Periph;
\r
816 /*******************************************************************************
\r
817 * Function Name : RCC_APB1PeriphClockCmd
\r
818 * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
\r
819 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
\r
821 * This parameter can be any combination of the following values:
\r
822 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
\r
823 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
\r
824 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
\r
825 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
\r
826 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
\r
827 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
\r
828 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
\r
829 * - NewState: new state of the specified peripheral clock.
\r
830 * This parameter can be: ENABLE or DISABLE.
\r
833 *******************************************************************************/
\r
834 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
\r
836 /* Check the parameters */
\r
837 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
838 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
840 if (NewState != DISABLE)
\r
842 RCC->APB1ENR |= RCC_APB1Periph;
\r
846 RCC->APB1ENR &= ~RCC_APB1Periph;
\r
850 /*******************************************************************************
\r
851 * Function Name : RCC_APB2PeriphResetCmd
\r
852 * Description : Forces or releases High Speed APB (APB2) peripheral reset.
\r
853 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
\r
854 * This parameter can be any combination of the following values:
\r
855 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
\r
856 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
\r
857 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
\r
858 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
\r
859 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
\r
860 * RCC_APB2Periph_ALL
\r
861 * - NewState: new state of the specified peripheral reset.
\r
862 * This parameter can be: ENABLE or DISABLE.
\r
865 *******************************************************************************/
\r
866 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
\r
868 /* Check the parameters */
\r
869 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
870 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
872 if (NewState != DISABLE)
\r
874 RCC->APB2RSTR |= RCC_APB2Periph;
\r
878 RCC->APB2RSTR &= ~RCC_APB2Periph;
\r
882 /*******************************************************************************
\r
883 * Function Name : RCC_APB1PeriphResetCmd
\r
884 * Description : Forces or releases Low Speed APB (APB1) peripheral reset.
\r
885 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
\r
886 * This parameter can be any combination of the following values:
\r
887 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
\r
888 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
\r
889 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
\r
890 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
\r
891 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
\r
892 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
\r
893 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
\r
894 * - NewState: new state of the specified peripheral clock.
\r
895 * This parameter can be: ENABLE or DISABLE.
\r
898 *******************************************************************************/
\r
899 void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
\r
901 /* Check the parameters */
\r
902 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
903 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
905 if (NewState != DISABLE)
\r
907 RCC->APB1RSTR |= RCC_APB1Periph;
\r
911 RCC->APB1RSTR &= ~RCC_APB1Periph;
\r
915 /*******************************************************************************
\r
916 * Function Name : RCC_BackupResetCmd
\r
917 * Description : Forces or releases the Backup domain reset.
\r
918 * Input : - NewState: new state of the Backup domain reset.
\r
919 * This parameter can be: ENABLE or DISABLE.
\r
922 *******************************************************************************/
\r
923 void RCC_BackupResetCmd(FunctionalState NewState)
\r
925 /* Check the parameters */
\r
926 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
928 *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
\r
931 /*******************************************************************************
\r
932 * Function Name : RCC_ClockSecuritySystemCmd
\r
933 * Description : Enables or disables the Clock Security System.
\r
934 * Input : - NewState: new state of the Clock Security System..
\r
935 * This parameter can be: ENABLE or DISABLE.
\r
938 *******************************************************************************/
\r
939 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
\r
941 /* Check the parameters */
\r
942 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
944 *(vu32 *) CR_CSSON_BB = (u32)NewState;
\r
947 /*******************************************************************************
\r
948 * Function Name : RCC_MCOConfig
\r
949 * Description : Selects the clock source to output on MCO pin.
\r
950 * Input : - RCC_MCO: specifies the clock source to output.
\r
951 * This parameter can be one of the following values:
\r
952 * - RCC_MCO_NoClock: No clock selected
\r
953 * - RCC_MCO_SYSCLK: System clock selected
\r
954 * - RCC_MCO_HSI: HSI oscillator clock selected
\r
955 * - RCC_MCO_HSE: HSE oscillator clock selected
\r
956 * - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
\r
959 *******************************************************************************/
\r
960 void RCC_MCOConfig(u8 RCC_MCO)
\r
962 /* Check the parameters */
\r
963 assert_param(IS_RCC_MCO(RCC_MCO));
\r
965 /* Perform Byte access to MCO[2:0] bits to select the MCO source */
\r
966 *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO;
\r
969 /*******************************************************************************
\r
970 * Function Name : RCC_GetFlagStatus
\r
971 * Description : Checks whether the specified RCC flag is set or not.
\r
972 * Input : - RCC_FLAG: specifies the flag to check.
\r
973 * This parameter can be one of the following values:
\r
974 * - RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
975 * - RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
976 * - RCC_FLAG_PLLRDY: PLL clock ready
\r
977 * - RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
978 * - RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
979 * - RCC_FLAG_PINRST: Pin reset
\r
980 * - RCC_FLAG_PORRST: POR/PDR reset
\r
981 * - RCC_FLAG_SFTRST: Software reset
\r
982 * - RCC_FLAG_IWDGRST: Independent Watchdog reset
\r
983 * - RCC_FLAG_WWDGRST: Window Watchdog reset
\r
984 * - RCC_FLAG_LPWRRST: Low Power reset
\r
986 * Return : The new state of RCC_FLAG (SET or RESET).
\r
987 *******************************************************************************/
\r
988 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
\r
992 FlagStatus bitstatus = RESET;
\r
994 /* Check the parameters */
\r
995 assert_param(IS_RCC_FLAG(RCC_FLAG));
\r
997 /* Get the RCC register index */
\r
998 tmp = RCC_FLAG >> 5;
\r
1000 if (tmp == 1) /* The flag to check is in CR register */
\r
1002 statusreg = RCC->CR;
\r
1004 else if (tmp == 2) /* The flag to check is in BDCR register */
\r
1006 statusreg = RCC->BDCR;
\r
1008 else /* The flag to check is in CSR register */
\r
1010 statusreg = RCC->CSR;
\r
1013 /* Get the flag position */
\r
1014 tmp = RCC_FLAG & FLAG_Mask;
\r
1016 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
\r
1022 bitstatus = RESET;
\r
1025 /* Return the flag status */
\r
1029 /*******************************************************************************
\r
1030 * Function Name : RCC_ClearFlag
\r
1031 * Description : Clears the RCC reset flags.
\r
1032 * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
\r
1033 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
\r
1034 * RCC_FLAG_LPWRRST
\r
1038 *******************************************************************************/
\r
1039 void RCC_ClearFlag(void)
\r
1041 /* Set RMVF bit to clear the reset flags */
\r
1042 RCC->CSR |= CSR_RMVF_Set;
\r
1045 /*******************************************************************************
\r
1046 * Function Name : RCC_GetITStatus
\r
1047 * Description : Checks whether the specified RCC interrupt has occurred or not.
\r
1048 * Input : - RCC_IT: specifies the RCC interrupt source to check.
\r
1049 * This parameter can be one of the following values:
\r
1050 * - RCC_IT_LSIRDY: LSI ready interrupt
\r
1051 * - RCC_IT_LSERDY: LSE ready interrupt
\r
1052 * - RCC_IT_HSIRDY: HSI ready interrupt
\r
1053 * - RCC_IT_HSERDY: HSE ready interrupt
\r
1054 * - RCC_IT_PLLRDY: PLL ready interrupt
\r
1055 * - RCC_IT_CSS: Clock Security System interrupt
\r
1057 * Return : The new state of RCC_IT (SET or RESET).
\r
1058 *******************************************************************************/
\r
1059 ITStatus RCC_GetITStatus(u8 RCC_IT)
\r
1061 ITStatus bitstatus = RESET;
\r
1063 /* Check the parameters */
\r
1064 assert_param(IS_RCC_GET_IT(RCC_IT));
\r
1066 /* Check the status of the specified RCC interrupt */
\r
1067 if ((RCC->CIR & RCC_IT) != (u32)RESET)
\r
1073 bitstatus = RESET;
\r
1076 /* Return the RCC_IT status */
\r
1080 /*******************************************************************************
\r
1081 * Function Name : RCC_ClearITPendingBit
\r
1082 * Description : Clears the RCC
\92s interrupt pending bits.
\r
1083 * Input : - RCC_IT: specifies the interrupt pending bit to clear.
\r
1084 * This parameter can be any combination of the following values:
\r
1085 * - RCC_IT_LSIRDY: LSI ready interrupt
\r
1086 * - RCC_IT_LSERDY: LSE ready interrupt
\r
1087 * - RCC_IT_HSIRDY: HSI ready interrupt
\r
1088 * - RCC_IT_HSERDY: HSE ready interrupt
\r
1089 * - RCC_IT_PLLRDY: PLL ready interrupt
\r
1090 * - RCC_IT_CSS: Clock Security System interrupt
\r
1093 *******************************************************************************/
\r
1094 void RCC_ClearITPendingBit(u8 RCC_IT)
\r
1096 /* Check the parameters */
\r
1097 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
\r
1099 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
\r
1101 *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT;
\r
1104 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
\r