1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_adc.h
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file contains all the functions prototypes for the
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6 * ADC firmware library.
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7 ********************************************************************************
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12 ********************************************************************************
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13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 *******************************************************************************/
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21 /* Define to prevent recursive inclusion -------------------------------------*/
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22 #ifndef __STM32F10x_ADC_H
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23 #define __STM32F10x_ADC_H
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25 /* Includes ------------------------------------------------------------------*/
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26 #include "stm32f10x_map.h"
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28 /* Exported types ------------------------------------------------------------*/
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29 /* ADC Init structure definition */
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33 FunctionalState ADC_ScanConvMode;
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34 FunctionalState ADC_ContinuousConvMode;
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35 u32 ADC_ExternalTrigConv;
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37 u8 ADC_NbrOfChannel;
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40 /* Exported constants --------------------------------------------------------*/
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41 /* ADC dual mode -------------------------------------------------------------*/
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42 #define ADC_Mode_Independent ((u32)0x00000000)
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43 #define ADC_Mode_RegInjecSimult ((u32)0x00010000)
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44 #define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
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45 #define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
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46 #define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
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47 #define ADC_Mode_InjecSimult ((u32)0x00050000)
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48 #define ADC_Mode_RegSimult ((u32)0x00060000)
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49 #define ADC_Mode_FastInterl ((u32)0x00070000)
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50 #define ADC_Mode_SlowInterl ((u32)0x00080000)
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51 #define ADC_Mode_AlterTrig ((u32)0x00090000)
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53 #define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
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54 (MODE == ADC_Mode_RegInjecSimult) || \
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55 (MODE == ADC_Mode_RegSimult_AlterTrig) || \
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56 (MODE == ADC_Mode_InjecSimult_FastInterl) || \
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57 (MODE == ADC_Mode_InjecSimult_SlowInterl) || \
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58 (MODE == ADC_Mode_InjecSimult) || \
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59 (MODE == ADC_Mode_RegSimult) || \
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60 (MODE == ADC_Mode_FastInterl) || \
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61 (MODE == ADC_Mode_SlowInterl) || \
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62 (MODE == ADC_Mode_AlterTrig))
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64 /* ADC extrenal trigger sources for regular channels conversion --------------*/
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65 #define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
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66 #define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
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67 #define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
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68 #define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
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69 #define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
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70 #define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
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71 #define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)
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72 #define ADC_ExternalTrigConv_None ((u32)0x000E0000)
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74 #define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
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75 (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
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76 (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
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77 (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
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78 (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
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79 (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
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80 (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
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81 (TRIG1 == ADC_ExternalTrigConv_None))
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83 /* ADC data align ------------------------------------------------------------*/
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84 #define ADC_DataAlign_Right ((u32)0x00000000)
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85 #define ADC_DataAlign_Left ((u32)0x00000800)
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87 #define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
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88 (ALIGN == ADC_DataAlign_Left))
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90 /* ADC channels --------------------------------------------------------------*/
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91 #define ADC_Channel_0 ((u8)0x00)
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92 #define ADC_Channel_1 ((u8)0x01)
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93 #define ADC_Channel_2 ((u8)0x02)
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94 #define ADC_Channel_3 ((u8)0x03)
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95 #define ADC_Channel_4 ((u8)0x04)
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96 #define ADC_Channel_5 ((u8)0x05)
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97 #define ADC_Channel_6 ((u8)0x06)
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98 #define ADC_Channel_7 ((u8)0x07)
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99 #define ADC_Channel_8 ((u8)0x08)
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100 #define ADC_Channel_9 ((u8)0x09)
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101 #define ADC_Channel_10 ((u8)0x0A)
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102 #define ADC_Channel_11 ((u8)0x0B)
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103 #define ADC_Channel_12 ((u8)0x0C)
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104 #define ADC_Channel_13 ((u8)0x0D)
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105 #define ADC_Channel_14 ((u8)0x0E)
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106 #define ADC_Channel_15 ((u8)0x0F)
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107 #define ADC_Channel_16 ((u8)0x10)
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108 #define ADC_Channel_17 ((u8)0x11)
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110 #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
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111 (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
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112 (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
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113 (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
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114 (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
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115 (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
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116 (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
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117 (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
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118 (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
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120 /* ADC sampling times --------------------------------------------------------*/
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121 #define ADC_SampleTime_1Cycles5 ((u8)0x00)
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122 #define ADC_SampleTime_7Cycles5 ((u8)0x01)
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123 #define ADC_SampleTime_13Cycles5 ((u8)0x02)
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124 #define ADC_SampleTime_28Cycles5 ((u8)0x03)
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125 #define ADC_SampleTime_41Cycles5 ((u8)0x04)
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126 #define ADC_SampleTime_55Cycles5 ((u8)0x05)
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127 #define ADC_SampleTime_71Cycles5 ((u8)0x06)
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128 #define ADC_SampleTime_239Cycles5 ((u8)0x07)
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130 #define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
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131 (TIME == ADC_SampleTime_7Cycles5) || \
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132 (TIME == ADC_SampleTime_13Cycles5) || \
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133 (TIME == ADC_SampleTime_28Cycles5) || \
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134 (TIME == ADC_SampleTime_41Cycles5) || \
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135 (TIME == ADC_SampleTime_55Cycles5) || \
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136 (TIME == ADC_SampleTime_71Cycles5) || \
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137 (TIME == ADC_SampleTime_239Cycles5))
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139 /* ADC extrenal trigger sources for injected channels conversion -------------*/
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140 #define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
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141 #define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
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142 #define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
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143 #define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
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144 #define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
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145 #define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
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146 #define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)
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147 #define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
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149 #define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
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150 (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
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151 (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
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152 (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
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153 (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
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154 (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
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155 (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
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156 (TRIG == ADC_ExternalTrigInjecConv_None))
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158 /* ADC injected channel selection --------------------------------------------*/
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159 #define ADC_InjectedChannel_1 ((u8)0x14)
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160 #define ADC_InjectedChannel_2 ((u8)0x18)
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161 #define ADC_InjectedChannel_3 ((u8)0x1C)
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162 #define ADC_InjectedChannel_4 ((u8)0x20)
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164 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
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165 (CHANNEL == ADC_InjectedChannel_2) || \
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166 (CHANNEL == ADC_InjectedChannel_3) || \
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167 (CHANNEL == ADC_InjectedChannel_4))
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169 /* ADC analog watchdog selection ---------------------------------------------*/
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170 #define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
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171 #define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
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172 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
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173 #define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
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174 #define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
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175 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
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176 #define ADC_AnalogWatchdog_None ((u32)0x00000000)
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178 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
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179 (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
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180 (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
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181 (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
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182 (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
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183 (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
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184 (WATCHDOG == ADC_AnalogWatchdog_None))
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186 /* ADC interrupts definition -------------------------------------------------*/
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187 #define ADC_IT_EOC ((u16)0x0220)
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188 #define ADC_IT_AWD ((u16)0x0140)
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189 #define ADC_IT_JEOC ((u16)0x0480)
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191 #define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
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192 #define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
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193 (IT == ADC_IT_JEOC))
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195 /* ADC flags definition ------------------------------------------------------*/
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196 #define ADC_FLAG_AWD ((u8)0x01)
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197 #define ADC_FLAG_EOC ((u8)0x02)
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198 #define ADC_FLAG_JEOC ((u8)0x04)
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199 #define ADC_FLAG_JSTRT ((u8)0x08)
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200 #define ADC_FLAG_STRT ((u8)0x10)
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202 #define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
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203 #define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
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204 (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
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205 (FLAG == ADC_FLAG_STRT))
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207 /* ADC thresholds ------------------------------------------------------------*/
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208 #define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
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210 /* ADC injected offset -------------------------------------------------------*/
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211 #define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
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213 /* ADC injected length -------------------------------------------------------*/
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214 #define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
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216 /* ADC injected rank ---------------------------------------------------------*/
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217 #define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
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219 /* ADC regular length --------------------------------------------------------*/
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220 #define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
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222 /* ADC regular rank ----------------------------------------------------------*/
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223 #define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
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225 /* ADC regular discontinuous mode number -------------------------------------*/
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226 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
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228 /* Exported macro ------------------------------------------------------------*/
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229 /* Exported functions ------------------------------------------------------- */
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230 void ADC_DeInit(ADC_TypeDef* ADCx);
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231 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
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232 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
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233 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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234 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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235 void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
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236 void ADC_ResetCalibration(ADC_TypeDef* ADCx);
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237 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
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238 void ADC_StartCalibration(ADC_TypeDef* ADCx);
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239 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
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240 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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241 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
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242 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
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243 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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244 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
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245 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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246 u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
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247 u32 ADC_GetDualModeConversionValue(void);
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248 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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249 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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250 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
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251 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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252 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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253 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
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254 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
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255 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
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256 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
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257 u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
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258 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
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259 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
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260 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
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261 void ADC_TempSensorCmd(FunctionalState NewState);
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262 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
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263 void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
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264 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
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265 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
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267 #endif /*__STM32F10x_ADC_H */
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269 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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