1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_dma.h
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file contains all the functions prototypes for the
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6 * DMA firmware library.
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7 ********************************************************************************
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12 ********************************************************************************
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13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 *******************************************************************************/
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21 /* Define to prevent recursive inclusion -------------------------------------*/
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22 #ifndef __STM32F10x_DMA_H
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23 #define __STM32F10x_DMA_H
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25 /* Includes ------------------------------------------------------------------*/
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26 #include "stm32f10x_map.h"
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28 /* Exported types ------------------------------------------------------------*/
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29 /* DMA Init structure definition */
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32 u32 DMA_PeripheralBaseAddr;
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33 u32 DMA_MemoryBaseAddr;
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35 u32 DMA_BufferSize;
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36 u32 DMA_PeripheralInc;
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38 u32 DMA_PeripheralDataSize;
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39 u32 DMA_MemoryDataSize;
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45 /* Exported constants --------------------------------------------------------*/
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46 /* DMA data transfer direction -----------------------------------------------*/
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47 #define DMA_DIR_PeripheralDST ((u32)0x00000010)
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48 #define DMA_DIR_PeripheralSRC ((u32)0x00000000)
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50 #define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \
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51 (DIR == DMA_DIR_PeripheralSRC))
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53 /* DMA peripheral incremented mode -------------------------------------------*/
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54 #define DMA_PeripheralInc_Enable ((u32)0x00000040)
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55 #define DMA_PeripheralInc_Disable ((u32)0x00000000)
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57 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \
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58 (STATE == DMA_PeripheralInc_Disable))
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60 /* DMA memory incremented mode -----------------------------------------------*/
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61 #define DMA_MemoryInc_Enable ((u32)0x00000080)
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62 #define DMA_MemoryInc_Disable ((u32)0x00000000)
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64 #define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \
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65 (STATE == DMA_MemoryInc_Disable))
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67 /* DMA peripheral data size --------------------------------------------------*/
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68 #define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
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69 #define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
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70 #define DMA_PeripheralDataSize_Word ((u32)0x00000200)
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72 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \
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73 (SIZE == DMA_PeripheralDataSize_HalfWord) || \
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74 (SIZE == DMA_PeripheralDataSize_Word))
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76 /* DMA memory data size ------------------------------------------------------*/
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77 #define DMA_MemoryDataSize_Byte ((u32)0x00000000)
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78 #define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
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79 #define DMA_MemoryDataSize_Word ((u32)0x00000800)
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81 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \
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82 (SIZE == DMA_MemoryDataSize_HalfWord) || \
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83 (SIZE == DMA_MemoryDataSize_Word))
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85 /* DMA circular/normal mode --------------------------------------------------*/
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86 #define DMA_Mode_Circular ((u32)0x00000020)
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87 #define DMA_Mode_Normal ((u32)0x00000000)
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89 #define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal))
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91 /* DMA priority level --------------------------------------------------------*/
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92 #define DMA_Priority_VeryHigh ((u32)0x00003000)
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93 #define DMA_Priority_High ((u32)0x00002000)
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94 #define DMA_Priority_Medium ((u32)0x00001000)
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95 #define DMA_Priority_Low ((u32)0x00000000)
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97 #define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \
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98 (PRIORITY == DMA_Priority_High) || \
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99 (PRIORITY == DMA_Priority_Medium) || \
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100 (PRIORITY == DMA_Priority_Low))
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102 /* DMA memory to memory ------------------------------------------------------*/
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103 #define DMA_M2M_Enable ((u32)0x00004000)
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104 #define DMA_M2M_Disable ((u32)0x00000000)
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106 #define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable))
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108 /* DMA interrupts definition -------------------------------------------------*/
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109 #define DMA_IT_TC ((u32)0x00000002)
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110 #define DMA_IT_HT ((u32)0x00000004)
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111 #define DMA_IT_TE ((u32)0x00000008)
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113 #define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00))
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115 #define DMA_IT_GL1 ((u32)0x00000001)
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116 #define DMA_IT_TC1 ((u32)0x00000002)
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117 #define DMA_IT_HT1 ((u32)0x00000004)
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118 #define DMA_IT_TE1 ((u32)0x00000008)
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119 #define DMA_IT_GL2 ((u32)0x00000010)
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120 #define DMA_IT_TC2 ((u32)0x00000020)
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121 #define DMA_IT_HT2 ((u32)0x00000040)
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122 #define DMA_IT_TE2 ((u32)0x00000080)
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123 #define DMA_IT_GL3 ((u32)0x00000100)
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124 #define DMA_IT_TC3 ((u32)0x00000200)
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125 #define DMA_IT_HT3 ((u32)0x00000400)
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126 #define DMA_IT_TE3 ((u32)0x00000800)
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127 #define DMA_IT_GL4 ((u32)0x00001000)
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128 #define DMA_IT_TC4 ((u32)0x00002000)
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129 #define DMA_IT_HT4 ((u32)0x00004000)
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130 #define DMA_IT_TE4 ((u32)0x00008000)
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131 #define DMA_IT_GL5 ((u32)0x00010000)
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132 #define DMA_IT_TC5 ((u32)0x00020000)
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133 #define DMA_IT_HT5 ((u32)0x00040000)
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134 #define DMA_IT_TE5 ((u32)0x00080000)
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135 #define DMA_IT_GL6 ((u32)0x00100000)
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136 #define DMA_IT_TC6 ((u32)0x00200000)
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137 #define DMA_IT_HT6 ((u32)0x00400000)
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138 #define DMA_IT_TE6 ((u32)0x00800000)
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139 #define DMA_IT_GL7 ((u32)0x01000000)
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140 #define DMA_IT_TC7 ((u32)0x02000000)
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141 #define DMA_IT_HT7 ((u32)0x04000000)
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142 #define DMA_IT_TE7 ((u32)0x08000000)
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144 #define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00))
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145 #define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \
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146 (IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \
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147 (IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \
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148 (IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \
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149 (IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \
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150 (IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \
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151 (IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \
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152 (IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \
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153 (IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \
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154 (IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \
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155 (IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \
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156 (IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \
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157 (IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \
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158 (IT == DMA_IT_HT7) || (IT == DMA_IT_TE7))
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160 /* DMA flags definition ------------------------------------------------------*/
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161 #define DMA_FLAG_GL1 ((u32)0x00000001)
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162 #define DMA_FLAG_TC1 ((u32)0x00000002)
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163 #define DMA_FLAG_HT1 ((u32)0x00000004)
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164 #define DMA_FLAG_TE1 ((u32)0x00000008)
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165 #define DMA_FLAG_GL2 ((u32)0x00000010)
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166 #define DMA_FLAG_TC2 ((u32)0x00000020)
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167 #define DMA_FLAG_HT2 ((u32)0x00000040)
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168 #define DMA_FLAG_TE2 ((u32)0x00000080)
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169 #define DMA_FLAG_GL3 ((u32)0x00000100)
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170 #define DMA_FLAG_TC3 ((u32)0x00000200)
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171 #define DMA_FLAG_HT3 ((u32)0x00000400)
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172 #define DMA_FLAG_TE3 ((u32)0x00000800)
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173 #define DMA_FLAG_GL4 ((u32)0x00001000)
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174 #define DMA_FLAG_TC4 ((u32)0x00002000)
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175 #define DMA_FLAG_HT4 ((u32)0x00004000)
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176 #define DMA_FLAG_TE4 ((u32)0x00008000)
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177 #define DMA_FLAG_GL5 ((u32)0x00010000)
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178 #define DMA_FLAG_TC5 ((u32)0x00020000)
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179 #define DMA_FLAG_HT5 ((u32)0x00040000)
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180 #define DMA_FLAG_TE5 ((u32)0x00080000)
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181 #define DMA_FLAG_GL6 ((u32)0x00100000)
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182 #define DMA_FLAG_TC6 ((u32)0x00200000)
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183 #define DMA_FLAG_HT6 ((u32)0x00400000)
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184 #define DMA_FLAG_TE6 ((u32)0x00800000)
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185 #define DMA_FLAG_GL7 ((u32)0x01000000)
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186 #define DMA_FLAG_TC7 ((u32)0x02000000)
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187 #define DMA_FLAG_HT7 ((u32)0x04000000)
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188 #define DMA_FLAG_TE7 ((u32)0x08000000)
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190 #define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00))
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191 #define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \
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192 (FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \
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193 (FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \
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194 (FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \
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195 (FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \
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196 (FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \
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197 (FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \
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198 (FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \
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199 (FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \
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200 (FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \
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201 (FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \
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202 (FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \
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203 (FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \
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204 (FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7))
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206 /* DMA Buffer Size -----------------------------------------------------------*/
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207 #define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000))
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209 /* Exported macro ------------------------------------------------------------*/
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210 /* Exported functions ------------------------------------------------------- */
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211 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
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212 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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213 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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214 void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
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215 void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState);
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216 u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
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217 FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
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218 void DMA_ClearFlag(u32 DMA_FLAG);
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219 ITStatus DMA_GetITStatus(u32 DMA_IT);
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220 void DMA_ClearITPendingBit(u32 DMA_IT);
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222 #endif /*__STM32F10x_DMA_H */
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224 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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