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Remove unnecessary use of portLONG, portCHAR and portSHORT.
[freertos] / Demo / ColdFire_MCF51CN128_CodeWarrior / Sources / main.c
1 /*\r
2     FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.\r
3 \r
4     This file is part of the FreeRTOS distribution.\r
5 \r
6     FreeRTOS is free software; you can redistribute it and/or modify it    under\r
7     the terms of the GNU General Public License (version 2) as published by the\r
8     Free Software Foundation and modified by the FreeRTOS exception.\r
9     **NOTE** The exception to the GPL is included to allow you to distribute a\r
10     combined work that includes FreeRTOS without being obliged to provide the\r
11     source code for proprietary components outside of the FreeRTOS kernel.\r
12     Alternative commercial license and support terms are also available upon\r
13     request.  See the licensing section of http://www.FreeRTOS.org for full\r
14     license details.\r
15 \r
16     FreeRTOS is distributed in the hope that it will be useful,    but WITHOUT\r
17     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
18     FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
19     more details.\r
20 \r
21     You should have received a copy of the GNU General Public License along\r
22     with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
23     Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
24 \r
25 \r
26     ***************************************************************************\r
27     *                                                                         *\r
28     * The FreeRTOS eBook and reference manual are available to purchase for a *\r
29     * small fee. Help yourself get started quickly while also helping the     *\r
30     * FreeRTOS project! See http://www.FreeRTOS.org/Documentation for details *\r
31     *                                                                         *\r
32     ***************************************************************************\r
33 \r
34     1 tab == 4 spaces!\r
35 \r
36     Please ensure to read the configuration and relevant port sections of the\r
37     online documentation.\r
38 \r
39     http://www.FreeRTOS.org - Documentation, latest information, license and\r
40     contact details.\r
41 \r
42     http://www.SafeRTOS.com - A version that is certified for use in safety\r
43     critical systems.\r
44 \r
45     http://www.OpenRTOS.com - Commercial support, development, porting,\r
46     licensing and training services.\r
47 */\r
48 \r
49 \r
50 /*\r
51  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
52  * documentation provides more details of the standard demo application tasks.\r
53  * In addition to the standard demo tasks, the following tasks and tests are\r
54  * defined and/or created within this file:\r
55  *\r
56  * "Web server" - Very basic demonstration of the uIP stack.  The WEB server\r
57  * simply generates a page that shows the current state of all the tasks within\r
58  * the system, including the high water mark of each task stack. The high water\r
59  * mark is displayed as the amount of stack that has never been used, so the\r
60  * closer the value is to zero the closer the task has come to overflowing its\r
61  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub\r
62  * pages display some TCP/IP status information and permit LED3 to be turned on\r
63  * and off using a check box.\r
64  *\r
65  * Tick hook function that implements a "Check" function -  This is executed \r
66  * every 5 seconds from the tick hook function.  It checks to ensure that all \r
67  * the standard demo tasks are still operational and running without error.  \r
68  * The system status (pass/fail) is then displayed underneith the task table on \r
69  * the served WEB pages.  \r
70  *\r
71  * "Reg test" tasks - These fill the registers with known values, then check\r
72  * that each register still contains its expected value.  Each task uses\r
73  * different values.  The tasks run with very low priority so get preempted very\r
74  * frequently.  A register containing an unexpected value is indicative of an\r
75  * error in the context switching mechanism.\r
76  *\r
77  */\r
78 \r
79 /* Standard includes. */\r
80 #include <stdio.h>\r
81 \r
82 /* Scheduler includes. */\r
83 #include "FreeRTOS.h"\r
84 #include "task.h"\r
85 #include "queue.h"\r
86 #include "semphr.h"\r
87 \r
88 /* Demo app includes. */\r
89 #include "BlockQ.h"\r
90 #include "death.h"\r
91 #include "flash.h"\r
92 #include "partest.h"\r
93 #include "GenQTest.h"\r
94 #include "QPeek.h"\r
95 #include "recmutex.h"\r
96 \r
97 /*-----------------------------------------------------------*/\r
98 \r
99 /* ComTest constants - there is no free LED for the comtest tasks. */\r
100 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )\r
101 #define mainCOM_TEST_LED                                        ( 5 )\r
102 \r
103 /* Task priorities. */\r
104 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
105 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
106 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
107 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
108 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
109 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
110 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
111 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
112 \r
113 /* WEB server requires enough stack for the string handling functions. */\r
114 #define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )\r
115 \r
116 /*\r
117  * Configure the hardware for the demo.\r
118  */\r
119 static void prvSetupHardware( void );\r
120 \r
121 /*\r
122  * Implements the 'check' function as described at the top of this file.\r
123  */\r
124 static void prvCheckFunction( void );\r
125 \r
126 /*\r
127  * Implement the 'Reg test' functionality as described at the top of this file.\r
128  */\r
129 static void vRegTest1Task( void *pvParameters );\r
130 static void vRegTest2Task( void *pvParameters );\r
131 \r
132 /*\r
133  * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
134  * this task.\r
135  */\r
136 extern void vuIP_Task( void *pvParameters );\r
137 \r
138 /*-----------------------------------------------------------*/\r
139 \r
140 /* Counters used to detect errors within the reg test tasks. */\r
141 static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
142 \r
143 /* Flag that latches any errors detected in the system. */\r
144 unsigned long ulCheckErrors = 0;\r
145 \r
146 /*-----------------------------------------------------------*/\r
147 \r
148 int main( void )\r
149 {\r
150 extern void vBasicWEBServer( void *pv );\r
151 \r
152         /* Setup the hardware ready for this demo. */\r
153         prvSetupHardware();\r
154         \r
155         xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
156 \r
157         /* Start the standard demo tasks. */\r
158         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
159         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
160         vStartQueuePeekTasks();\r
161         vStartRecursiveMutexTasks();\r
162         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
163 \r
164         /* Start the reg test tasks - defined in this file. */\r
165         xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
166         xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
167 \r
168         /* Start the scheduler. */\r
169         vTaskStartScheduler();\r
170 \r
171     /* Will only get here if there was insufficient memory to create the idle\r
172     task. */\r
173         for( ;; )\r
174         {\r
175         }\r
176 }\r
177 /*-----------------------------------------------------------*/\r
178 \r
179 void vApplicationTickHook( void )\r
180 {\r
181 static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
182 const unsigned long ulExecutionRate = 5000 / portTICK_RATE_MS;\r
183         \r
184     /* Increment the count of how many times the tick hook has been called. */\r
185     ulExecutionCount++;\r
186     \r
187     /* Is it time to perform the check again? */\r
188         if( ulExecutionCount >= ulExecutionRate )\r
189         {\r
190                 /* Reset the execution count so this function is called again in 5\r
191                 seconds time. */\r
192                 ulExecutionCount = 0;\r
193         \r
194                 /* Has an error been found in any task? */\r
195                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
196                 {\r
197                         ulCheckErrors |= 0x01UL;\r
198                 }\r
199 \r
200                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
201                 {\r
202                         ulCheckErrors |= 0x02UL;\r
203                 }\r
204 \r
205                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
206                 {\r
207                         ulCheckErrors |= 0x04UL;\r
208                 }\r
209 \r
210                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
211             {\r
212                 ulCheckErrors |= 0x200UL;\r
213             }\r
214 \r
215                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
216                 {\r
217                         ulCheckErrors |= 0x1000UL;\r
218                 }\r
219 \r
220                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
221                 {\r
222                         ulCheckErrors |= 0x1000UL;\r
223                 }\r
224 \r
225                 ulLastRegTest1Count = ulRegTest1Counter;\r
226                 ulLastRegTest2Count = ulRegTest2Counter;\r
227         }\r
228 }\r
229 /*-----------------------------------------------------------*/\r
230 \r
231 static void prvSetupHardware( void ) \r
232 {\r
233         /* Disable the watchdog, STOP and WAIT modes. */\r
234         SOPT1 = 0;\r
235 \r
236         /* --- Setup clock to use external 25MHz source. --- */\r
237         \r
238         /* Extal and xtal pin ON. */\r
239         PTDPF1_D4 = 0x03;\r
240         PTDPF1_D5 = 0x03;\r
241 \r
242         /* Switch from FEI to FBE (FLL bypassed external)\r
243         enable external clock source */\r
244         MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */\r
245               | MCGC2_EREFS_MASK    /* Because crystal is being used */\r
246               | MCGC2_RANGE_MASK;   /* High range */\r
247                 \r
248         /* Select clock mode and clear IREFs. */\r
249         MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */\r
250               | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */\r
251               | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */\r
252           \r
253         /* Wait for Reference and Clock status bits to update. */\r
254         while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )\r
255         {\r
256                 /* Nothing to do here. */\r
257         }\r
258 \r
259         /* Switch from FBE to PBE (PLL bypassed internal) mode. */\r
260         MCGC3 =  0x08               /* Set PLL multi 50MHz. */\r
261               |  MCGC3_PLLS_MASK;   /* Select PLL. */\r
262 \r
263         /* Wait for PLL status and lock bits to update. */\r
264         while( !MCGSC_PLLST | !MCGSC_LOCK )\r
265         {\r
266                 /* Nothing to do here. */\r
267         }\r
268 \r
269 \r
270         /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external \r
271         mode). */\r
272         MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */\r
273 \r
274         /* Wait for the clock status bits to update. */\r
275         while( MCGSC_CLKST != 0x03 )\r
276         {\r
277                 /* Nothing to do here. */\r
278         }\r
279 \r
280         /* Setup the IO for the LED outputs. */\r
281         vParTestInitialise();\r
282 }\r
283 /*-----------------------------------------------------------*/\r
284 \r
285 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
286 {\r
287         /* This will get called if a stack overflow is detected during the context\r
288         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
289         problems within nested interrupts, but only do this for debug purposes as\r
290         it will increase the context switch time. */\r
291 \r
292         ( void ) pxTask;\r
293         ( void ) pcTaskName;\r
294 \r
295         for( ;; )\r
296         {\r
297         }\r
298 }\r
299 /*-----------------------------------------------------------*/\r
300 \r
301 static void vRegTest1Task( void *pvParameters )\r
302 {\r
303   /* Just to remove compiler warnings. */\r
304   ( void ) pvParameters;\r
305   \r
306         /* Set all the registers to known values, then check that each retains its\r
307         expected value - as described at the top of this file.  If an error is\r
308         found then the loop counter will no longer be incremented allowing the check\r
309         task to recognise the error. */\r
310         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
311                                                 "       moveq           #1, d0                                  \n\t"\r
312                                                 "       moveq           #2, d1                                  \n\t"\r
313                                                 "       moveq           #3, d2                                  \n\t"\r
314                                                 "       moveq           #4, d3                                  \n\t"\r
315                                                 "       moveq           #5, d4                                  \n\t"\r
316                                                 "       moveq           #6, d5                                  \n\t"                                           \r
317                                                 "       moveq           #7, d6                                  \n\t"\r
318                                                 "       moveq           #8, d7                                  \n\t"\r
319                                                 "       move            #9, a0                                  \n\t"\r
320                                                 "       move            #10, a1                                 \n\t"\r
321                                                 "       move            #11, a2                                 \n\t"\r
322                                                 "       move            #12, a3                                 \n\t"\r
323                                                 "       move            #13, a4                                 \n\t"\r
324                                                 "       move            #15, a6                                 \n\t"\r
325                                                 "                                                                               \n\t"\r
326                                                 "       cmpi.l          #1, d0                                  \n\t"\r
327                                                 "       bne                     reg_test_1_error                \n\t"\r
328                                                 "       cmpi.l          #2, d1                                  \n\t"\r
329                                                 "       bne                     reg_test_1_error                \n\t"\r
330                                                 "       cmpi.l          #3, d2                                  \n\t"\r
331                                                 "       bne                     reg_test_1_error                \n\t"\r
332                                                 "       cmpi.l          #4, d3                                  \n\t"\r
333                                                 "       bne                     reg_test_1_error                \n\t"\r
334                                                 "       cmpi.l          #5, d4                                  \n\t"\r
335                                                 "       bne                     reg_test_1_error                \n\t"\r
336                                                 "       cmpi.l          #6, d5                                  \n\t"\r
337                                                 "       bne                     reg_test_1_error                \n\t"\r
338                                                 "       cmpi.l          #7, d6                                  \n\t"\r
339                                                 "       bne                     reg_test_1_error                \n\t"\r
340                                                 "       cmpi.l          #8, d7                                  \n\t"\r
341                                                 "       bne                     reg_test_1_error                \n\t"\r
342                                                 "       move            a0, d0                                  \n\t"\r
343                                                 "       cmpi.l          #9, d0                                  \n\t"\r
344                                                 "       bne                     reg_test_1_error                \n\t"\r
345                                                 "       move            a1, d0                                  \n\t"\r
346                                                 "       cmpi.l          #10, d0                                 \n\t"\r
347                                                 "       bne                     reg_test_1_error                \n\t"\r
348                                                 "       move            a2, d0                                  \n\t"\r
349                                                 "       cmpi.l          #11, d0                                 \n\t"\r
350                                                 "       bne                     reg_test_1_error                \n\t"\r
351                                                 "       move            a3, d0                                  \n\t"\r
352                                                 "       cmpi.l          #12, d0                                 \n\t"\r
353                                                 "       bne                     reg_test_1_error                \n\t"\r
354                                                 "       move            a4, d0                                  \n\t"\r
355                                                 "       cmpi.l          #13, d0                                 \n\t"\r
356                                                 "       bne                     reg_test_1_error                \n\t"\r
357                                                 "       move            a6, d0                                  \n\t"\r
358                                                 "       cmpi.l          #15, d0                                 \n\t"\r
359                                                 "       bne                     reg_test_1_error                \n\t"\r
360                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
361                                                 "       addq            #1, d0                                  \n\t"\r
362                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
363                                                 "       bra                     reg_test_1_start                \n\t"\r
364                                                 "reg_test_1_error:                                              \n\t"\r
365                                                 "       bra                     reg_test_1_error                \n\t"\r
366                                         );\r
367 }\r
368 /*-----------------------------------------------------------*/\r
369 \r
370 static void vRegTest2Task( void *pvParameters )\r
371 {\r
372   /* Just to remove compiler warnings. */\r
373   ( void ) pvParameters;\r
374 \r
375         /* Set all the registers to known values, then check that each retains its\r
376         expected value - as described at the top of this file.  If an error is\r
377         found then the loop counter will no longer be incremented allowing the check\r
378         task to recognise the error. */\r
379         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
380                                                 "       moveq           #10, d0                                 \n\t"\r
381                                                 "       moveq           #20, d1                                 \n\t"\r
382                                                 "       moveq           #30, d2                                 \n\t"\r
383                                                 "       moveq           #40, d3                                 \n\t"\r
384                                                 "       moveq           #50, d4                                 \n\t"\r
385                                                 "       moveq           #60, d5                                 \n\t"\r
386                                                 "       moveq           #70, d6                                 \n\t"\r
387                                                 "       moveq           #80, d7                                 \n\t"\r
388                                                 "       move            #90, a0                                 \n\t"\r
389                                                 "       move            #100, a1                                \n\t"\r
390                                                 "       move            #110, a2                                \n\t"\r
391                                                 "       move            #120, a3                                \n\t"\r
392                                                 "       move            #130, a4                                \n\t"\r
393                                                 "       move            #150, a6                                \n\t"\r
394                                                 "                                                                               \n\t"\r
395                                                 "       cmpi.l          #10, d0                                 \n\t"\r
396                                                 "       bne                     reg_test_2_error                \n\t"\r
397                                                 "       cmpi.l          #20, d1                                 \n\t"\r
398                                                 "       bne                     reg_test_2_error                \n\t"\r
399                                                 "       cmpi.l          #30, d2                                 \n\t"\r
400                                                 "       bne                     reg_test_2_error                \n\t"\r
401                                                 "       cmpi.l          #40, d3                                 \n\t"\r
402                                                 "       bne                     reg_test_2_error                \n\t"\r
403                                                 "       cmpi.l          #50, d4                                 \n\t"\r
404                                                 "       bne                     reg_test_2_error                \n\t"\r
405                                                 "       cmpi.l          #60, d5                                 \n\t"\r
406                                                 "       bne                     reg_test_2_error                \n\t"\r
407                                                 "       cmpi.l          #70, d6                                 \n\t"\r
408                                                 "       bne                     reg_test_2_error                \n\t"\r
409                                                 "       cmpi.l          #80, d7                                 \n\t"\r
410                                                 "       bne                     reg_test_2_error                \n\t"\r
411                                                 "       move            a0, d0                                  \n\t"\r
412                                                 "       cmpi.l          #90, d0                                 \n\t"\r
413                                                 "       bne                     reg_test_2_error                \n\t"\r
414                                                 "       move            a1, d0                                  \n\t"\r
415                                                 "       cmpi.l          #100, d0                                \n\t"\r
416                                                 "       bne                     reg_test_2_error                \n\t"\r
417                                                 "       move            a2, d0                                  \n\t"\r
418                                                 "       cmpi.l          #110, d0                                \n\t"\r
419                                                 "       bne                     reg_test_2_error                \n\t"\r
420                                                 "       move            a3, d0                                  \n\t"\r
421                                                 "       cmpi.l          #120, d0                                \n\t"\r
422                                                 "       bne                     reg_test_2_error                \n\t"\r
423                                                 "       move            a4, d0                                  \n\t"\r
424                                                 "       cmpi.l          #130, d0                                \n\t"\r
425                                                 "       bne                     reg_test_2_error                \n\t"\r
426                                                 "       move            a6, d0                                  \n\t"\r
427                                                 "       cmpi.l          #150, d0                                \n\t"\r
428                                                 "       bne                     reg_test_2_error                \n\t"\r
429                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
430                                                 "       addq            #1, d0                                  \n\t"\r
431                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
432                                                 "       bra                     reg_test_2_start                \n\t"\r
433                                                 "reg_test_2_error:                                              \n\t"\r
434                                                 "       bra                     reg_test_2_error                \n\t"\r
435                                         );\r
436 }\r
437 /*-----------------------------------------------------------*/\r
438 \r