1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2008/05/23 Revision: 0.95
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7 * (c) Copyright UNIS, a.s. 1997-2008
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12 * http : www.processorexpert.com
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13 * mail : info@processorexpert.com
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16 #ifndef __MCF52221_PAD_H__
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17 #define __MCF52221_PAD_H__
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20 /*********************************************************************
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24 *********************************************************************/
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26 /* Register read/write macros */
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27 #define MCF_PAD_PSRR (*(vuint32*)(0x40100078))
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28 #define MCF_PAD_PDSR (*(vuint32*)(0x4010007C))
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31 /* Bit definitions and macros for MCF_PAD_PSRR */
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32 #define MCF_PAD_PSRR_PSRR0 (0x1)
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33 #define MCF_PAD_PSRR_PSRR1 (0x2)
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34 #define MCF_PAD_PSRR_PSRR2 (0x4)
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35 #define MCF_PAD_PSRR_PSRR3 (0x8)
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36 #define MCF_PAD_PSRR_PSRR4 (0x10)
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37 #define MCF_PAD_PSRR_PSRR5 (0x20)
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38 #define MCF_PAD_PSRR_PSRR6 (0x40)
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39 #define MCF_PAD_PSRR_PSRR7 (0x80)
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40 #define MCF_PAD_PSRR_PSRR8 (0x100)
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41 #define MCF_PAD_PSRR_PSRR9 (0x200)
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42 #define MCF_PAD_PSRR_PSRR10 (0x400)
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43 #define MCF_PAD_PSRR_PSRR11 (0x800)
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44 #define MCF_PAD_PSRR_PSRR12 (0x1000)
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45 #define MCF_PAD_PSRR_PSRR13 (0x2000)
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46 #define MCF_PAD_PSRR_PSRR14 (0x4000)
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47 #define MCF_PAD_PSRR_PSRR15 (0x8000)
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48 #define MCF_PAD_PSRR_PSRR16 (0x10000)
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49 #define MCF_PAD_PSRR_PSRR17 (0x20000)
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50 #define MCF_PAD_PSRR_PSRR18 (0x40000)
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51 #define MCF_PAD_PSRR_PSRR19 (0x80000)
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52 #define MCF_PAD_PSRR_PSRR20 (0x100000)
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53 #define MCF_PAD_PSRR_PSRR21 (0x200000)
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54 #define MCF_PAD_PSRR_PSRR22 (0x400000)
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55 #define MCF_PAD_PSRR_PSRR23 (0x800000)
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56 #define MCF_PAD_PSRR_PSRR24 (0x1000000)
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57 #define MCF_PAD_PSRR_PSRR25 (0x2000000)
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58 #define MCF_PAD_PSRR_PSRR26 (0x4000000)
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59 #define MCF_PAD_PSRR_PSRR27 (0x8000000)
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61 /* Bit definitions and macros for MCF_PAD_PDSR */
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62 #define MCF_PAD_PDSR_PDSR0 (0x1)
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63 #define MCF_PAD_PDSR_PDSR1 (0x2)
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64 #define MCF_PAD_PDSR_PDSR2 (0x4)
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65 #define MCF_PAD_PDSR_PDSR3 (0x8)
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66 #define MCF_PAD_PDSR_PDSR4 (0x10)
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67 #define MCF_PAD_PDSR_PDSR5 (0x20)
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68 #define MCF_PAD_PDSR_PDSR6 (0x40)
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69 #define MCF_PAD_PDSR_PDSR7 (0x80)
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70 #define MCF_PAD_PDSR_PDSR8 (0x100)
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71 #define MCF_PAD_PDSR_PDSR9 (0x200)
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72 #define MCF_PAD_PDSR_PDSR10 (0x400)
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73 #define MCF_PAD_PDSR_PDSR11 (0x800)
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74 #define MCF_PAD_PDSR_PDSR12 (0x1000)
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75 #define MCF_PAD_PDSR_PDSR13 (0x2000)
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76 #define MCF_PAD_PDSR_PDSR14 (0x4000)
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77 #define MCF_PAD_PDSR_PDSR15 (0x8000)
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78 #define MCF_PAD_PDSR_PDSR16 (0x10000)
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79 #define MCF_PAD_PDSR_PDSR17 (0x20000)
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80 #define MCF_PAD_PDSR_PDSR18 (0x40000)
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81 #define MCF_PAD_PDSR_PDSR19 (0x80000)
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82 #define MCF_PAD_PDSR_PDSR20 (0x100000)
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83 #define MCF_PAD_PDSR_PDSR21 (0x200000)
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84 #define MCF_PAD_PDSR_PDSR22 (0x400000)
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85 #define MCF_PAD_PDSR_PDSR23 (0x800000)
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86 #define MCF_PAD_PDSR_PDSR24 (0x1000000)
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87 #define MCF_PAD_PDSR_PDSR25 (0x2000000)
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88 #define MCF_PAD_PDSR_PDSR26 (0x4000000)
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89 #define MCF_PAD_PDSR_PDSR27 (0x8000000)
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92 #endif /* __MCF52221_PAD_H__ */
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