2 * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
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3 * All rights reserved.
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5 * Redistribution and use in source and binary forms, with or without modification,
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6 * are permitted provided that the following conditions are met:
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8 * 1. Redistributions of source code must retain the above copyright notice,
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9 * this list of conditions and the following disclaimer.
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10 * 2. Redistributions in binary form must reproduce the above copyright notice,
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11 * this list of conditions and the following disclaimer in the documentation
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12 * and/or other materials provided with the distribution.
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13 * 3. The name of the author may not be used to endorse or promote products
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14 * derived from this software without specific prior written permission.
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16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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19 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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21 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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27 * This file is part of the lwIP TCP/IP stack.
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29 * Author: Adam Dunkels <adam@sics.se>
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33 /* Standard library includes. */
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37 /* FreeRTOS includes. */
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38 #include "FreeRTOS.h"
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41 xTaskHandle xEthIntTask;
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43 /* lwIP includes. */
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44 #include "lwip/def.h"
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45 #include "lwip/mem.h"
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46 #include "lwip/pbuf.h"
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47 #include "lwip/sys.h"
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48 #include "lwip/stats.h"
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49 #include "lwip/snmp.h"
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50 #include "netif/etharp.h"
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52 /* Hardware includes. */
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55 /* Delay to wait for a DMA buffer to become available if one is not already
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57 #define netifBUFFER_WAIT_ATTEMPTS 10
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58 #define netifBUFFER_WAIT_DELAY (10 / portTICK_RATE_MS)
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60 /* Delay between polling the PHY to see if a link has been established. */
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61 #define netifLINK_DELAY ( 500 / portTICK_RATE_MS )
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63 /* Delay between looking for incoming packets. In ideal world this would be
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65 #define netifBLOCK_TIME_WAITING_FOR_INPUT netifLINK_DELAY
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67 /* Name for the netif. */
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71 /* Hardware specific. */
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72 #define netifFIRST_FEC_VECTOR 23
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74 /*-----------------------------------------------------------*/
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76 /* The DMA descriptors. This is a char array to allow us to align it correctly. */
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77 static unsigned portCHAR xFECTxDescriptors_unaligned[ ( configNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ];
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78 static unsigned portCHAR xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_BUFFERS * sizeof( FECBD ) ) + 16 ];
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79 static FECBD *xFECTxDescriptors;
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80 static FECBD *xFECRxDescriptors;
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82 /* The DMA buffers. These are char arrays to allow them to be alligned correctly. */
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83 static unsigned portCHAR ucFECTxBuffers[ ( configNUM_FEC_TX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
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84 static unsigned portCHAR ucFECRxBuffers[ ( configNUM_FEC_RX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
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85 static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxNextTxBuffer = 0;
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87 /* Semaphore used by the FEC interrupt handler to wake the handler task. */
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88 static xSemaphoreHandle xFecSemaphore;
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90 #pragma options align= packed
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93 struct eth_addr *ethaddr;
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94 /* Add whatever per-interface state that is needed here. */
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97 /*-----------------------------------------------------------*/
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99 /* Standard lwIP netif handlers. */
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100 static void prvInitialiseFECBuffers( void );
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101 static void low_level_init( struct netif *netif );
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102 static err_t low_level_output(struct netif *netif, struct pbuf *p);
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103 static struct pbuf *low_level_input(struct netif *netif);
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104 static void ethernetif_input( void *pParams );
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106 /* Functions adapted from Freescale provided code. */
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107 static int fec_mii_write( int phy_addr, int reg_addr, int data );
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108 static int fec_mii_read( int phy_addr, int reg_addr, uint16* data );
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109 static uint8 fec_hash_address( const uint8* addr );
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110 static void fec_set_address( const uint8 *pa );
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111 static void fec_irq_enable( void );
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113 /*-----------------------------------------------------------*/
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115 /********************************************************************/
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117 * Write a value to a PHY's MII register.
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121 * phy_addr Address of the PHY.
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122 * reg_addr Address of the register in the PHY.
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123 * data Data to be written to the PHY register.
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129 * Please refer to your PHY manual for registers and their meanings.
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130 * mii_write() polls for the FEC's MII interrupt event and clears it.
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131 * If after a suitable amount of time the event isn't triggered, a
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132 * value of 0 is returned.
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134 static int fec_mii_write( int phy_addr, int reg_addr, int data )
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139 /* Clear the MII interrupt bit */
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140 MCF_FEC_EIR = MCF_FEC_EIR_MII;
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142 /* Mask the MII interrupt */
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143 eimr = MCF_FEC_EIMR;
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144 MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;
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146 /* Write to the MII Management Frame Register to kick-off the MII write */
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147 MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_WRITE | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | MCF_FEC_MMFR_DATA( data );
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149 /* Poll for the MII interrupt (interrupt should be masked) */
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150 for (timeout = 0; timeout < MII_TIMEOUT; timeout++)
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152 if (MCF_FEC_EIR & MCF_FEC_EIR_MII)
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158 if( timeout == MII_TIMEOUT )
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163 /* Clear the MII interrupt bit */
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164 MCF_FEC_EIR = MCF_FEC_EIR_MII;
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166 /* Restore the EIMR */
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167 MCF_FEC_EIMR = eimr;
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172 /********************************************************************/
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174 * Read a value from a PHY's MII register.
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178 * phy_addr Address of the PHY.
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179 * reg_addr Address of the register in the PHY.
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180 * data Pointer to storage for the Data to be read
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181 * from the PHY register (passed by reference)
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187 * Please refer to your PHY manual for registers and their meanings.
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188 * mii_read() polls for the FEC's MII interrupt event and clears it.
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189 * If after a suitable amount of time the event isn't triggered, a
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190 * value of 0 is returned.
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192 static int fec_mii_read( int phy_addr, int reg_addr, uint16* data )
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197 /* Clear the MII interrupt bit */
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198 MCF_FEC_EIR = MCF_FEC_EIR_MII;
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200 /* Mask the MII interrupt */
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201 eimr = MCF_FEC_EIMR;
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202 MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;
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204 /* Write to the MII Management Frame Register to kick-off the MII read */
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205 MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_READ | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10;
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207 /* Poll for the MII interrupt (interrupt should be masked) */
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208 for (timeout = 0; timeout < MII_TIMEOUT; timeout++)
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210 if (MCF_FEC_EIR & MCF_FEC_EIR_MII)
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216 if(timeout == MII_TIMEOUT)
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221 /* Clear the MII interrupt bit */
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222 MCF_FEC_EIR = MCF_FEC_EIR_MII;
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224 /* Restore the EIMR */
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225 MCF_FEC_EIMR = eimr;
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227 *data = (uint16)(MCF_FEC_MMFR & 0x0000FFFF);
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233 /********************************************************************/
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235 * Generate the hash table settings for the given address
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238 * addr 48-bit (6 byte) Address to generate the hash for
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241 * The 6 most significant bits of the 32-bit CRC result
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243 static uint8 fec_hash_address( const uint8* addr )
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255 if((byte & 0x01)^(crc & 0x01))
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258 crc = crc ^ 0xEDB88320;
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269 return (uint8)(crc >> 26);
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272 /********************************************************************/
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274 * Set the Physical (Hardware) Address and the Individual Address
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275 * Hash in the selected FEC
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279 * pa Physical (Hardware) Address for the selected FEC
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281 static void fec_set_address( const uint8 *pa )
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286 * Set the Physical Address
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288 MCF_FEC_PALR = (uint32)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]);
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289 MCF_FEC_PAUR = (uint32)((pa[4]<<24) | (pa[5]<<16));
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292 * Calculate and set the hash for given Physical Address
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293 * in the Individual Address Hash registers
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295 crc = fec_hash_address(pa);
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298 MCF_FEC_IAUR |= (uint32)(1 << (crc - 32));
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302 MCF_FEC_IALR |= (uint32)(1 << crc);
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307 /********************************************************************/
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309 * Enable interrupts on the selected FEC
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312 static void fec_irq_enable( void )
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316 #if INTC_LVL_FEC > configMAX_SYSCALL_INTERRUPT_PRIORITY
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317 #error INTC_LVL_FEC must be less than or equal to configMAX_SYSCALL_INTERRUPT_PRIORITY
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320 fec_vbase = 64 + netifFIRST_FEC_VECTOR;
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322 /* Enable FEC interrupts to the ColdFire core
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323 * Setup each ICR with a unique interrupt level combination */
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327 MCF_INTC0_ICR(fec_vbase+4) = MCF_INTC_ICR_IL(INTC_LVL_FEC);
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329 /* FEC Rx Buffer */
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330 MCF_INTC0_ICR(fec_vbase+5) = MCF_INTC_ICR_IL(INTC_LVL_FEC);
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332 /* FEC FIFO Underrun */
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333 MCF_INTC0_ICR(fec_vbase+2) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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335 /* FEC Collision Retry Limit */
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336 MCF_INTC0_ICR(fec_vbase+3) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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338 /* FEC Late Collision */
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339 MCF_INTC0_ICR(fec_vbase+7) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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341 /* FEC Heartbeat Error */
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342 MCF_INTC0_ICR(fec_vbase+8) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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344 /* FEC Bus Error */
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345 MCF_INTC0_ICR(fec_vbase+10) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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347 /* FEC Babbling Transmit */
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348 MCF_INTC0_ICR(fec_vbase+11) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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350 /* FEC Babbling Receive */
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351 MCF_INTC0_ICR(fec_vbase+12) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);
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353 /* Enable the FEC interrupts in the mask register */
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354 MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK33 | MCF_INTC_IMRH_INT_MASK34 | MCF_INTC_IMRH_INT_MASK35 );
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355 MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK26 | MCF_INTC_IMRL_INT_MASK27 | MCF_INTC_IMRL_INT_MASK28 | MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK30 | MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_MASKALL );
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357 /* Clear any pending FEC interrupt events */
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358 MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;
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360 /* Unmask all FEC interrupts */
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361 MCF_FEC_EIMR = MCF_FEC_EIMR_UNMASK_ALL;
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365 * In this function, the hardware should be initialized.
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366 * Called from ethernetif_init().
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368 * @param netif the already initialized lwip network interface structure
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369 * for this ethernetif
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371 static void low_level_init( struct netif *netif )
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373 unsigned portSHORT usData;
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374 const unsigned portCHAR ucMACAddress[6] =
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376 configMAC_0, configMAC_1,configMAC_2,configMAC_3,configMAC_4,configMAC_5
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379 prvInitialiseFECBuffers();
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380 vSemaphoreCreateBinary( xFecSemaphore );
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382 for( usData = 0; usData < 6; usData++ )
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384 netif->hwaddr[ usData ] = ucMACAddress[ usData ];
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387 /* Set the Reset bit and clear the Enable bit */
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388 MCF_FEC_ECR = MCF_FEC_ECR_RESET;
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390 /* Wait at least 8 clock cycles */
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391 for( usData = 0; usData < 10; usData++ )
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396 /* Set MII speed to 2.5MHz. */
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397 MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 );
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400 * Make sure the external interface signals are enabled
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402 MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_IRQ3_FEC_MDIO | MCF_GPIO_PNQPAR_IRQ5_FEC_MDC;
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405 MCF_GPIO_PTIPAR = MCF_GPIO_PTIPAR_FEC_COL_FEC_COL
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406 | MCF_GPIO_PTIPAR_FEC_CRS_FEC_CRS
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407 | MCF_GPIO_PTIPAR_FEC_RXCLK_FEC_RXCLK
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408 | MCF_GPIO_PTIPAR_FEC_RXD0_FEC_RXD0
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409 | MCF_GPIO_PTIPAR_FEC_RXD1_FEC_RXD1
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410 | MCF_GPIO_PTIPAR_FEC_RXD2_FEC_RXD2
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411 | MCF_GPIO_PTIPAR_FEC_RXD3_FEC_RXD3
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412 | MCF_GPIO_PTIPAR_FEC_RXDV_FEC_RXDV;
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414 MCF_GPIO_PTJPAR = MCF_GPIO_PTJPAR_FEC_RXER_FEC_RXER
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415 | MCF_GPIO_PTJPAR_FEC_TXCLK_FEC_TXCLK
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416 | MCF_GPIO_PTJPAR_FEC_TXD0_FEC_TXD0
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417 | MCF_GPIO_PTJPAR_FEC_TXD1_FEC_TXD1
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418 | MCF_GPIO_PTJPAR_FEC_TXD2_FEC_TXD2
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419 | MCF_GPIO_PTJPAR_FEC_TXD3_FEC_TXD3
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420 | MCF_GPIO_PTJPAR_FEC_TXEN_FEC_TXEN
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421 | MCF_GPIO_PTJPAR_FEC_TXER_FEC_TXER;
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424 /* Can we talk to the PHY? */
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427 vTaskDelay( netifLINK_DELAY );
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429 fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData );
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431 } while( ( usData == 0xffff ) || ( usData == 0 ) );
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433 /* Start auto negotiate. */
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434 fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
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436 /* Wait for auto negotiate to complete. */
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439 vTaskDelay( netifLINK_DELAY );
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440 fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );
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442 } while( !( usData & PHY_BMSR_AN_COMPLETE ) );
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444 /* When we get here we have a link - find out what has been negotiated. */
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445 fec_mii_read( configPHY_ADDRESS, PHY_ANLPAR, &usData );
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447 if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_100BTX ) )
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449 /* Speed is 100. */
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456 if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_10BTX_FDX ) )
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459 MCF_FEC_RCR &= (uint32)~MCF_FEC_RCR_DRT;
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460 MCF_FEC_TCR |= MCF_FEC_TCR_FDEN;
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464 MCF_FEC_RCR |= MCF_FEC_RCR_DRT;
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465 MCF_FEC_TCR &= (uint32)~MCF_FEC_TCR_FDEN;
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468 /* Clear the Individual and Group Address Hash registers */
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474 /* Set the Physical Address for the selected FEC */
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475 fec_set_address( ucMACAddress );
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477 /* Set Rx Buffer Size */
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478 MCF_FEC_EMRBR = (uint16)configFEC_BUFFER_SIZE;
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480 /* Point to the start of the circular Rx buffer descriptor queue */
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481 MCF_FEC_ERDSR = ( volatile unsigned portLONG ) &( xFECRxDescriptors[ 0 ] );
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483 /* Point to the start of the circular Tx buffer descriptor queue */
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484 MCF_FEC_ETSDR = ( volatile unsigned portLONG ) &( xFECTxDescriptors[ 0 ] );
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486 /* Mask all FEC interrupts */
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487 MCF_FEC_EIMR = MCF_FEC_EIMR_MASK_ALL;
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489 /* Clear all FEC interrupt events */
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490 MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;
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492 /* Initialize the Receive Control Register */
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493 MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) | MCF_FEC_RCR_FCE;
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495 MCF_FEC_RCR |= MCF_FEC_RCR_MII_MODE;
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497 #if( configUSE_PROMISCUOUS_MODE == 1 )
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499 MCF_FEC_RCR |= MCF_FEC_RCR_PROM;
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503 /* Create the task that handles the EMAC. */
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504 xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", configETHERNET_INPUT_TASK_STACK_SIZE, (void *)netif, configETHERNET_INPUT_TASK_PRIORITY, &xEthIntTask );
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507 MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
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508 MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
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512 * This function should do the actual transmission of the packet. The packet is
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513 * contained in the pbuf that is passed to the function. This pbuf
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514 * might be chained.
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516 * @param netif the lwip network interface structure for this ethernetif
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517 * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
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518 * @return ERR_OK if the packet could be sent
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519 * an err_t value if the packet couldn't be sent
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521 * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
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522 * strange results. You might consider waiting for space in the DMA queue
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523 * to become availale since the stack doesn't retry to send a packet
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524 * dropped because of memory failure (except for the TCP timers).
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526 static err_t low_level_output(struct netif *netif, struct pbuf *p)
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530 unsigned portCHAR *pcTxData = NULL;
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536 pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
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539 /* Get a DMA buffer into which we can write the data to send. */
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540 for( i = 0; i < netifBUFFER_WAIT_ATTEMPTS; i++ )
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542 if( xFECTxDescriptors[ uxNextTxBuffer ].status & TX_BD_R )
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544 /* Wait for the buffer to become available. */
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545 vTaskDelay( netifBUFFER_WAIT_DELAY );
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549 pcTxData = xFECTxDescriptors[ uxNextTxBuffer ].data;
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554 if( pcTxData == NULL )
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556 /* For break point only. */
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563 for( q = p; q != NULL; q = q->next )
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565 /* Send the data from the pbuf to the interface, one pbuf at a
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566 time. The size of the data in each pbuf is kept in the ->len
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568 memcpy( &pcTxData[l], (u8_t*)q->payload, q->len );
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573 /* Setup the buffer descriptor for transmission */
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574 xFECTxDescriptors[ uxNextTxBuffer ].length = l;//nbuf->length + ETH_HDR_LEN;
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575 xFECTxDescriptors[ uxNextTxBuffer ].status |= (TX_BD_R | TX_BD_L);
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577 /* Continue the Tx DMA task (in case it was waiting for a new TxBD) */
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578 MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
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581 if( uxNextTxBuffer >= configNUM_FEC_TX_BUFFERS )
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583 uxNextTxBuffer = 0;
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587 pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
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590 LINK_STATS_INC(link.xmit);
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596 * Should allocate a pbuf and transfer the bytes of the incoming
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597 * packet from the interface into the pbuf.
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599 * @param netif the lwip network interface structure for this ethernetif
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600 * @return a pbuf filled with the received packet (including MAC header)
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601 * NULL on memory error
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603 static struct pbuf *low_level_input(struct netif *netif)
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605 struct pbuf *p, *q;
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613 /* Obtain the size of the packet and put it into the "len" variable. */
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614 len = xFECRxDescriptors[ uxNextRxBuffer ].length;
\r
616 if( ( len != 0 ) && ( ( xFECRxDescriptors[ uxNextRxBuffer ].status & RX_BD_E ) == 0 ) )
\r
619 len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
\r
622 /* We allocate a pbuf chain of pbufs from the pool. */
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623 p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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629 pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
\r
632 /* We iterate over the pbuf chain until we have read the entire
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633 * packet into the pbuf. */
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634 for(q = p; q != NULL; q = q->next)
\r
636 /* Read enough bytes to fill this pbuf in the chain. The
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637 * available data in the pbuf is given by the q->len
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639 memcpy((u8_t*)q->payload, &(xFECRxDescriptors[ uxNextRxBuffer ].data[l]), q->len);
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645 pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
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648 LINK_STATS_INC(link.recv);
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654 LINK_STATS_INC(link.memerr);
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655 LINK_STATS_INC(link.drop);
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660 /* Free the descriptor. */
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661 xFECRxDescriptors[ uxNextRxBuffer ].status |= RX_BD_E;
\r
662 MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
\r
665 if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS )
\r
667 uxNextRxBuffer = 0;
\r
676 * This function should be called when a packet is ready to be read
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677 * from the interface. It uses the function low_level_input() that
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678 * should handle the actual reception of bytes from the network
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679 * interface.Then the type of the received packet is determined and
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680 * the appropriate input function is called.
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682 * @param netif the lwip network interface structure for this ethernetif
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685 static void ethernetif_input( void *pParams )
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687 struct netif *netif;
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688 struct ethernetif *ethernetif;
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689 struct eth_hdr *ethhdr;
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692 netif = (struct netif*) pParams;
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693 ethernetif = netif->state;
\r
700 /* move received packet into a new pbuf */
\r
701 p = low_level_input( netif );
\r
705 /* No packet could be read. Wait a for an interrupt to tell us
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706 there is more data available. */
\r
707 xSemaphoreTake( xFecSemaphore, netifBLOCK_TIME_WAITING_FOR_INPUT );
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710 } while( p == NULL );
\r
712 /* points to packet payload, which starts with an Ethernet header */
\r
713 ethhdr = p->payload;
\r
715 switch (htons(ethhdr->type)) {
\r
716 /* IP or ARP packet? */
\r
720 pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
\r
722 /* full packet send to tcpip_thread to process */
\r
723 if (netif->input(p, netif) != ERR_OK)
\r
725 LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
\r
733 #if ETHARP_TRUST_IP_MAC
\r
734 etharp_ip_input(netif, p);
\r
737 etharp_arp_input(netif, ethernetif->ethaddr, p);
\r
749 * Should be called at the beginning of the program to set up the
\r
750 * network interface. It calls the function low_level_init() to do the
\r
751 * actual setup of the hardware.
\r
753 * This function should be passed as a parameter to netif_add().
\r
755 * @param netif the lwip network interface structure for this ethernetif
\r
756 * @return ERR_OK if the loopif is initialized
\r
757 * ERR_MEM if private data couldn't be allocated
\r
758 * any other err_t on error
\r
760 err_t ethernetif_init(struct netif *netif)
\r
762 struct ethernetif *ethernetif;
\r
764 LWIP_ASSERT("netif != NULL", (netif != NULL));
\r
766 ethernetif = mem_malloc(sizeof(struct ethernetif));
\r
768 if (ethernetif == NULL)
\r
770 LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
\r
774 #if LWIP_NETIF_HOSTNAME
\r
775 /* Initialize interface hostname */
\r
776 netif->hostname = "lwip";
\r
777 #endif /* LWIP_NETIF_HOSTNAME */
\r
780 * Initialize the snmp variables and counters inside the struct netif.
\r
781 * The last argument should be replaced with your link speed, in units
\r
782 * of bits per second.
\r
784 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100);
\r
786 netif->state = ethernetif;
\r
787 netif->name[0] = IFNAME0;
\r
788 netif->name[1] = IFNAME1;
\r
790 /* We directly use etharp_output() here to save a function call.
\r
791 * You can instead declare your own function an call etharp_output()
\r
792 * from it if you have to do some checks before sending (e.g. if link
\r
795 netif->output = etharp_output;
\r
796 netif->linkoutput = low_level_output;
\r
798 ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
\r
800 low_level_init(netif);
\r
804 /*-----------------------------------------------------------*/
\r
806 static void prvInitialiseFECBuffers( void )
\r
808 unsigned portBASE_TYPE ux;
\r
809 unsigned portCHAR *pcBufPointer;
\r
811 pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] );
\r
812 while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )
\r
817 xFECTxDescriptors = ( FECBD * ) pcBufPointer;
\r
819 pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] );
\r
820 while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )
\r
825 xFECRxDescriptors = ( FECBD * ) pcBufPointer;
\r
828 /* Setup the buffers and descriptors. */
\r
829 pcBufPointer = &( ucFECTxBuffers[ 0 ] );
\r
830 while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )
\r
835 for( ux = 0; ux < configNUM_FEC_TX_BUFFERS; ux++ )
\r
837 xFECTxDescriptors[ ux ].status = TX_BD_TC;
\r
838 xFECTxDescriptors[ ux ].data = pcBufPointer;
\r
839 pcBufPointer += configFEC_BUFFER_SIZE;
\r
840 xFECTxDescriptors[ ux ].length = 0;
\r
843 pcBufPointer = &( ucFECRxBuffers[ 0 ] );
\r
844 while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )
\r
849 for( ux = 0; ux < configNUM_FEC_RX_BUFFERS; ux++ )
\r
851 xFECRxDescriptors[ ux ].status = RX_BD_E;
\r
852 xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE;
\r
853 xFECRxDescriptors[ ux ].data = pcBufPointer;
\r
854 pcBufPointer += configFEC_BUFFER_SIZE;
\r
857 /* Set the wrap bit in the last descriptors to form a ring. */
\r
858 xFECTxDescriptors[ configNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W;
\r
859 xFECRxDescriptors[ configNUM_FEC_RX_BUFFERS - 1 ].status |= RX_BD_W;
\r
861 uxNextRxBuffer = 0;
\r
862 uxNextTxBuffer = 0;
\r
864 /*-----------------------------------------------------------*/
\r
866 __declspec(interrupt:0) void vFECISRHandler( void )
\r
868 unsigned portLONG ulEvent;
\r
869 portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;
\r
871 ulEvent = MCF_FEC_EIR & MCF_FEC_EIMR;
\r
872 MCF_FEC_EIR = ulEvent;
\r
874 if( ( ulEvent & MCF_FEC_EIR_RXB ) || ( ulEvent & MCF_FEC_EIR_RXF ) )
\r
876 /* A packet has been received. Wake the handler task. */
\r
877 xSemaphoreGiveFromISR( xFecSemaphore, &xHighPriorityTaskWoken );
\r
880 if (ulEvent & ( MCF_FEC_EIR_UN | MCF_FEC_EIR_RL | MCF_FEC_EIR_LC | MCF_FEC_EIR_EBERR | MCF_FEC_EIR_BABT | MCF_FEC_EIR_BABR | MCF_FEC_EIR_HBERR ) )
\r
882 /* Sledge hammer error handling. */
\r
883 prvInitialiseFECBuffers();
\r
884 MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
\r
887 portEND_SWITCHING_ISR( xHighPriorityTaskWoken );
\r