1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.91
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8 #ifndef __MCF52235_ADC_H__
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9 #define __MCF52235_ADC_H__
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12 /*********************************************************************
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14 * Analog-to-Digital Converter (ADC)
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000]))
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20 #define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002]))
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21 #define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004]))
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22 #define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006]))
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23 #define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008]))
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24 #define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A]))
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25 #define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C]))
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26 #define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E]))
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27 #define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010]))
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28 #define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012]))
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29 #define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014]))
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30 #define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016]))
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31 #define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018]))
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32 #define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A]))
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33 #define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C]))
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34 #define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E]))
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35 #define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020]))
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36 #define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022]))
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37 #define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024]))
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38 #define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026]))
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39 #define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028]))
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40 #define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A]))
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41 #define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C]))
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42 #define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E]))
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43 #define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030]))
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44 #define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032]))
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45 #define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034]))
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46 #define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036]))
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47 #define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038]))
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48 #define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A]))
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49 #define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C]))
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50 #define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E]))
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51 #define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040]))
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52 #define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042]))
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53 #define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044]))
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54 #define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046]))
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55 #define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048]))
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56 #define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A]))
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57 #define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C]))
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58 #define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E]))
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59 #define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050]))
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60 #define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052]))
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61 #define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054]))
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62 #define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012 + ((x)*0x2)]))
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63 #define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022 + ((x)*0x2)]))
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64 #define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032 + ((x)*0x2)]))
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65 #define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042 + ((x)*0x2)]))
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68 /* Bit definitions and macros for MCF_ADC_CTRL1 */
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69 #define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)
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70 #define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)
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71 #define MCF_ADC_CTRL1_HLMTIE (0x100)
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72 #define MCF_ADC_CTRL1_LLMTIE (0x200)
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73 #define MCF_ADC_CTRL1_ZCIE (0x400)
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74 #define MCF_ADC_CTRL1_EOSIE0 (0x800)
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75 #define MCF_ADC_CTRL1_SYNC0 (0x1000)
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76 #define MCF_ADC_CTRL1_START0 (0x2000)
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77 #define MCF_ADC_CTRL1_STOP0 (0x4000)
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79 /* Bit definitions and macros for MCF_ADC_CTRL2 */
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80 #define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)
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81 #define MCF_ADC_CTRL2_SIMULT (0x20)
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82 #define MCF_ADC_CTRL2_EOSIE1 (0x800)
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83 #define MCF_ADC_CTRL2_SYNC1 (0x1000)
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84 #define MCF_ADC_CTRL2_START1 (0x2000)
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85 #define MCF_ADC_CTRL2_STOP1 (0x4000)
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87 /* Bit definitions and macros for MCF_ADC_ADZCC */
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88 #define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)
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89 #define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)
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90 #define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)
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91 #define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)
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92 #define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)
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93 #define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)
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94 #define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)
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95 #define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)
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97 /* Bit definitions and macros for MCF_ADC_ADLST1 */
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98 #define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)
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99 #define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)
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100 #define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)
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101 #define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)
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103 /* Bit definitions and macros for MCF_ADC_ADLST2 */
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104 #define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)
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105 #define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)
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106 #define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)
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107 #define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)
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109 /* Bit definitions and macros for MCF_ADC_ADSDIS */
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110 #define MCF_ADC_ADSDIS_DS0 (0x1)
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111 #define MCF_ADC_ADSDIS_DS1 (0x2)
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112 #define MCF_ADC_ADSDIS_DS2 (0x4)
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113 #define MCF_ADC_ADSDIS_DS3 (0x8)
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114 #define MCF_ADC_ADSDIS_DS4 (0x10)
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115 #define MCF_ADC_ADSDIS_DS5 (0x20)
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116 #define MCF_ADC_ADSDIS_DS6 (0x40)
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117 #define MCF_ADC_ADSDIS_DS7 (0x80)
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119 /* Bit definitions and macros for MCF_ADC_ADSTAT */
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120 #define MCF_ADC_ADSTAT_RDY0 (0x1)
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121 #define MCF_ADC_ADSTAT_RDY1 (0x2)
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122 #define MCF_ADC_ADSTAT_RDY2 (0x4)
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123 #define MCF_ADC_ADSTAT_RDY3 (0x8)
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124 #define MCF_ADC_ADSTAT_RDY4 (0x10)
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125 #define MCF_ADC_ADSTAT_RDY5 (0x20)
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126 #define MCF_ADC_ADSTAT_RDY6 (0x40)
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127 #define MCF_ADC_ADSTAT_RDY7 (0x80)
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128 #define MCF_ADC_ADSTAT_HLMTI (0x100)
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129 #define MCF_ADC_ADSTAT_LLMTI (0x200)
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130 #define MCF_ADC_ADSTAT_ZCI (0x400)
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131 #define MCF_ADC_ADSTAT_EOSI0 (0x800)
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132 #define MCF_ADC_ADSTAT_EOSI1 (0x1000)
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133 #define MCF_ADC_ADSTAT_CIP1 (0x4000)
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134 #define MCF_ADC_ADSTAT_CIP0 (0x8000)
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136 /* Bit definitions and macros for MCF_ADC_ADLSTAT */
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137 #define MCF_ADC_ADLSTAT_LLS0 (0x1)
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138 #define MCF_ADC_ADLSTAT_LLS1 (0x2)
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139 #define MCF_ADC_ADLSTAT_LLS2 (0x4)
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140 #define MCF_ADC_ADLSTAT_LLS3 (0x8)
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141 #define MCF_ADC_ADLSTAT_LLS4 (0x10)
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142 #define MCF_ADC_ADLSTAT_LLS5 (0x20)
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143 #define MCF_ADC_ADLSTAT_LLS6 (0x40)
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144 #define MCF_ADC_ADLSTAT_LLS7 (0x80)
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145 #define MCF_ADC_ADLSTAT_HLS0 (0x100)
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146 #define MCF_ADC_ADLSTAT_HLS1 (0x200)
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147 #define MCF_ADC_ADLSTAT_HLS2 (0x400)
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148 #define MCF_ADC_ADLSTAT_HLS3 (0x800)
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149 #define MCF_ADC_ADLSTAT_HLS4 (0x1000)
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150 #define MCF_ADC_ADLSTAT_HLS5 (0x2000)
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151 #define MCF_ADC_ADLSTAT_HLS6 (0x4000)
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152 #define MCF_ADC_ADLSTAT_HLS7 (0x8000)
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154 /* Bit definitions and macros for MCF_ADC_ADZCSTAT */
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155 #define MCF_ADC_ADZCSTAT_ZCS0 (0x1)
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156 #define MCF_ADC_ADZCSTAT_ZCS1 (0x2)
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157 #define MCF_ADC_ADZCSTAT_ZCS2 (0x4)
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158 #define MCF_ADC_ADZCSTAT_ZCS3 (0x8)
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159 #define MCF_ADC_ADZCSTAT_ZCS4 (0x10)
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160 #define MCF_ADC_ADZCSTAT_ZCS5 (0x20)
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161 #define MCF_ADC_ADZCSTAT_ZCS6 (0x40)
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162 #define MCF_ADC_ADZCSTAT_ZCS7 (0x80)
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164 /* Bit definitions and macros for MCF_ADC_ADRSLT */
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165 #define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)
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166 #define MCF_ADC_ADRSLT_SEXT (0x8000)
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168 /* Bit definitions and macros for MCF_ADC_ADLLMT */
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169 #define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)
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171 /* Bit definitions and macros for MCF_ADC_ADHLMT */
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172 #define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)
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174 /* Bit definitions and macros for MCF_ADC_ADOFS */
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175 #define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)
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177 /* Bit definitions and macros for MCF_ADC_POWER */
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178 #define MCF_ADC_POWER_PD0 (0x1)
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179 #define MCF_ADC_POWER_PD1 (0x2)
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180 #define MCF_ADC_POWER_PD2 (0x4)
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181 #define MCF_ADC_POWER_APD (0x8)
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182 #define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)
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183 #define MCF_ADC_POWER_PSTS0 (0x400)
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184 #define MCF_ADC_POWER_PSTS1 (0x800)
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185 #define MCF_ADC_POWER_PSTS2 (0x1000)
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186 #define MCF_ADC_POWER_ASB (0x8000)
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188 /* Bit definitions and macros for MCF_ADC_CAL */
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189 #define MCF_ADC_CAL_SEL_VREFL (0x4000)
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190 #define MCF_ADC_CAL_SEL_VREFH (0x8000)
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193 #endif /* __MCF52235_ADC_H__ */
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