1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.91
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8 #ifndef __MCF52235_DTIM_H__
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9 #define __MCF52235_DTIM_H__
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12 /*********************************************************************
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x400]))
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20 #define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x402]))
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21 #define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x403]))
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22 #define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x404]))
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23 #define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x408]))
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24 #define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x40C]))
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26 #define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x440]))
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27 #define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x442]))
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28 #define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x443]))
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29 #define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x444]))
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30 #define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x448]))
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31 #define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x44C]))
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33 #define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x480]))
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34 #define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x482]))
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35 #define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x483]))
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36 #define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x484]))
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37 #define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x488]))
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38 #define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x48C]))
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40 #define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x4C0]))
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41 #define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x4C2]))
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42 #define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x4C3]))
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43 #define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x4C4]))
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44 #define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x4C8]))
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45 #define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x4CC]))
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47 #define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x400 + ((x)*0x40)]))
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48 #define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x402 + ((x)*0x40)]))
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49 #define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x403 + ((x)*0x40)]))
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50 #define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x404 + ((x)*0x40)]))
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51 #define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x408 + ((x)*0x40)]))
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52 #define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x40C + ((x)*0x40)]))
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55 /* Bit definitions and macros for MCF_DTIM_DTMR */
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56 #define MCF_DTIM_DTMR_RST (0x1)
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57 #define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
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58 #define MCF_DTIM_DTMR_CLK_STOP (0)
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59 #define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
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60 #define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
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61 #define MCF_DTIM_DTMR_CLK_DTIN (0x6)
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62 #define MCF_DTIM_DTMR_FRR (0x8)
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63 #define MCF_DTIM_DTMR_ORRI (0x10)
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64 #define MCF_DTIM_DTMR_OM (0x20)
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65 #define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
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66 #define MCF_DTIM_DTMR_CE_NONE (0)
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67 #define MCF_DTIM_DTMR_CE_RISE (0x40)
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68 #define MCF_DTIM_DTMR_CE_FALL (0x80)
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69 #define MCF_DTIM_DTMR_CE_ANY (0xC0)
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70 #define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
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72 /* Bit definitions and macros for MCF_DTIM_DTXMR */
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73 #define MCF_DTIM_DTXMR_MODE16 (0x1)
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74 #define MCF_DTIM_DTXMR_HALTED (0x40)
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75 #define MCF_DTIM_DTXMR_DMAEN (0x80)
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77 /* Bit definitions and macros for MCF_DTIM_DTER */
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78 #define MCF_DTIM_DTER_CAP (0x1)
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79 #define MCF_DTIM_DTER_REF (0x2)
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81 /* Bit definitions and macros for MCF_DTIM_DTRR */
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82 #define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
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84 /* Bit definitions and macros for MCF_DTIM_DTCR */
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85 #define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
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87 /* Bit definitions and macros for MCF_DTIM_DTCN */
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88 #define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
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91 #endif /* __MCF52235_DTIM_H__ */
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