1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.91
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8 #ifndef __MCF52235_PAD_H__
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9 #define __MCF52235_PAD_H__
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12 /*********************************************************************
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14 * Common GPIO Registers
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_PAD_PWOR (*(vuint16*)(&__IPSBAR[0x100078]))
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20 #define MCF_PAD_PDSR1 (*(vuint16*)(&__IPSBAR[0x10007A]))
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21 #define MCF_PAD_PDSR0 (*(vuint32*)(&__IPSBAR[0x10007C]))
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24 /* Bit definitions and macros for MCF_PAD_PWOR */
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25 #define MCF_PAD_PWOR_PWOR0 (0x1)
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26 #define MCF_PAD_PWOR_PWOR1 (0x2)
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27 #define MCF_PAD_PWOR_PWOR2 (0x4)
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28 #define MCF_PAD_PWOR_PWOR3 (0x8)
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29 #define MCF_PAD_PWOR_PWOR4 (0x10)
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30 #define MCF_PAD_PWOR_PWOR5 (0x20)
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31 #define MCF_PAD_PWOR_PWOR6 (0x40)
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32 #define MCF_PAD_PWOR_PWOR7 (0x80)
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33 #define MCF_PAD_PWOR_PWOR8 (0x100)
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34 #define MCF_PAD_PWOR_PWOR9 (0x200)
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35 #define MCF_PAD_PWOR_PWOR10 (0x400)
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36 #define MCF_PAD_PWOR_PWOR11 (0x800)
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37 #define MCF_PAD_PWOR_PWOR12 (0x1000)
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38 #define MCF_PAD_PWOR_PWOR13 (0x2000)
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39 #define MCF_PAD_PWOR_PWOR14 (0x4000)
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40 #define MCF_PAD_PWOR_PWOR15 (0x8000)
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42 /* Bit definitions and macros for MCF_PAD_PDSR1 */
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43 #define MCF_PAD_PDSR1_PDSR32 (0x1)
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44 #define MCF_PAD_PDSR1_PDSR33 (0x2)
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45 #define MCF_PAD_PDSR1_PDSR34 (0x4)
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46 #define MCF_PAD_PDSR1_PDSR35 (0x8)
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47 #define MCF_PAD_PDSR1_PDSR36 (0x10)
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48 #define MCF_PAD_PDSR1_PDSR37 (0x20)
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49 #define MCF_PAD_PDSR1_PDSR38 (0x40)
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50 #define MCF_PAD_PDSR1_PDSR39 (0x80)
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51 #define MCF_PAD_PDSR1_PDSR40 (0x100)
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52 #define MCF_PAD_PDSR1_PDSR41 (0x200)
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53 #define MCF_PAD_PDSR1_PDSR42 (0x400)
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54 #define MCF_PAD_PDSR1_PDSR43 (0x800)
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55 #define MCF_PAD_PDSR1_PDSR44 (0x1000)
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56 #define MCF_PAD_PDSR1_PDSR45 (0x2000)
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57 #define MCF_PAD_PDSR1_PDSR46 (0x4000)
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58 #define MCF_PAD_PDSR1_PDSR47 (0x8000)
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60 /* Bit definitions and macros for MCF_PAD_PDSR0 */
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61 #define MCF_PAD_PDSR0_PDSR0 (0x1)
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62 #define MCF_PAD_PDSR0_PDSR1 (0x2)
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63 #define MCF_PAD_PDSR0_PDSR2 (0x4)
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64 #define MCF_PAD_PDSR0_PDSR3 (0x8)
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65 #define MCF_PAD_PDSR0_PDSR4 (0x10)
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66 #define MCF_PAD_PDSR0_PDSR5 (0x20)
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67 #define MCF_PAD_PDSR0_PDSR6 (0x40)
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68 #define MCF_PAD_PDSR0_PDSR7 (0x80)
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69 #define MCF_PAD_PDSR0_PDSR8 (0x100)
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70 #define MCF_PAD_PDSR0_PDSR9 (0x200)
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71 #define MCF_PAD_PDSR0_PDSR10 (0x400)
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72 #define MCF_PAD_PDSR0_PDSR11 (0x800)
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73 #define MCF_PAD_PDSR0_PDSR12 (0x1000)
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74 #define MCF_PAD_PDSR0_PDSR13 (0x2000)
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75 #define MCF_PAD_PDSR0_PDSR14 (0x4000)
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76 #define MCF_PAD_PDSR0_PDSR15 (0x8000)
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77 #define MCF_PAD_PDSR0_PDSR16 (0x10000)
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78 #define MCF_PAD_PDSR0_PDSR17 (0x20000)
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79 #define MCF_PAD_PDSR0_PDSR18 (0x40000)
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80 #define MCF_PAD_PDSR0_PDSR19 (0x80000)
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81 #define MCF_PAD_PDSR0_PDSR20 (0x100000)
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82 #define MCF_PAD_PDSR0_PDSR21 (0x200000)
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83 #define MCF_PAD_PDSR0_PDSR22 (0x400000)
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84 #define MCF_PAD_PDSR0_PDSR23 (0x800000)
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85 #define MCF_PAD_PDSR0_PDSR24 (0x1000000)
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86 #define MCF_PAD_PDSR0_PDSR25 (0x2000000)
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87 #define MCF_PAD_PDSR0_PDSR26 (0x4000000)
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88 #define MCF_PAD_PDSR0_PDSR27 (0x8000000)
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89 #define MCF_PAD_PDSR0_PDSR28 (0x10000000)
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90 #define MCF_PAD_PDSR0_PDSR29 (0x20000000)
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91 #define MCF_PAD_PDSR0_PDSR30 (0x40000000)
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92 #define MCF_PAD_PDSR0_PDSR31 (0x80000000)
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95 #endif /* __MCF52235_PAD_H__ */
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