1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2007/03/19 Revision: 0.91
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8 #ifndef __MCF52235_SCM_H__
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9 #define __MCF52235_SCM_H__
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12 /*********************************************************************
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14 * System Control Module (SCM)
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16 *********************************************************************/
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18 /* Register read/write macros */
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19 #define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))
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20 #define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0xC]))
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21 #define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))
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22 #define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))
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23 #define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))
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24 #define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))
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25 #define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x18]))
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26 #define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))
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27 #define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))
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28 #define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x21]))
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29 #define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x22]))
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30 #define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x23]))
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31 #define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))
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32 #define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))
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33 #define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))
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34 #define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))
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35 #define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))
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36 #define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x29]))
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37 #define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2A]))
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38 #define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2B]))
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39 #define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2C]))
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40 #define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))
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41 #define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))
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42 #define MCF_SCM_PACR(x) (*(vuint8 *)(&__IPSBAR[0x24 + ((x)*0x1)]))
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43 #define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))
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46 #define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))
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47 #define MCF_SCM_IPSBAR_V (0x1)
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48 #define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
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51 /* Bit definitions and macros for MCF_SCM_RAMBAR */
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52 #define MCF_SCM_RAMBAR_BDE (0x200)
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53 #define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
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55 /* Bit definitions and macros for MCF_SCM_PPMRH */
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56 #define MCF_SCM_PPMRH_CDPORTS (0x1)
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57 #define MCF_SCM_PPMRH_CDEPORT (0x2)
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58 #define MCF_SCM_PPMRH_CDPIT0 (0x8)
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59 #define MCF_SCM_PPMRH_CDPIT1 (0x10)
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60 #define MCF_SCM_PPMRH_CDADC (0x80)
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61 #define MCF_SCM_PPMRH_CDGPT (0x100)
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62 #define MCF_SCM_PPMRH_CDPWM (0x200)
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63 #define MCF_SCM_PPMRH_CDFCAN (0x400)
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64 #define MCF_SCM_PPMRH_CDCFM (0x800)
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65 #define MCF_SCM_PPMRH_CDEPHY (0x1000)
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66 #define MCF_SCM_PPMRH_CDRNGA (0x2000)
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68 /* Bit definitions and macros for MCF_SCM_CRSR */
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69 #define MCF_SCM_CRSR_CWDR (0x20)
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70 #define MCF_SCM_CRSR_EXT (0x80)
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72 /* Bit definitions and macros for MCF_SCM_CWCR */
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73 #define MCF_SCM_CWCR_CWTIF (0x1)
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74 #define MCF_SCM_CWCR_CWTAVAL (0x2)
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75 #define MCF_SCM_CWCR_CWTA (0x4)
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76 #define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
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77 #define MCF_SCM_CWCR_CWT_2_9 (0)
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78 #define MCF_SCM_CWCR_CWT_2_11 (0x8)
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79 #define MCF_SCM_CWCR_CWT_2_13 (0x10)
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80 #define MCF_SCM_CWCR_CWT_2_15 (0x18)
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81 #define MCF_SCM_CWCR_CWT_2_19 (0x20)
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82 #define MCF_SCM_CWCR_CWT_2_23 (0x28)
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83 #define MCF_SCM_CWCR_CWT_2_27 (0x30)
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84 #define MCF_SCM_CWCR_CWT_2_31 (0x38)
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85 #define MCF_SCM_CWCR_CWRI (0x40)
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86 #define MCF_SCM_CWCR_CWE (0x80)
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88 /* Bit definitions and macros for MCF_SCM_CWSR */
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89 #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
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91 /* Bit definitions and macros for MCF_SCM_DMAREQC */
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92 #define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
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93 #define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
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94 #define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
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95 #define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
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97 /* Bit definitions and macros for MCF_SCM_PPMRL */
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98 #define MCF_SCM_PPMRL_CDG (0x2)
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99 #define MCF_SCM_PPMRL_CDDMA (0x10)
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100 #define MCF_SCM_PPMRL_CDUART0 (0x20)
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101 #define MCF_SCM_PPMRL_CDUART1 (0x40)
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102 #define MCF_SCM_PPMRL_CDUART2 (0x80)
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103 #define MCF_SCM_PPMRL_CDI2C (0x200)
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104 #define MCF_SCM_PPMRL_CDQSPI (0x400)
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105 #define MCF_SCM_PPMRL_CDRTC (0x1000)
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106 #define MCF_SCM_PPMRL_CDTMR0 (0x2000)
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107 #define MCF_SCM_PPMRL_CDTMR1 (0x4000)
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108 #define MCF_SCM_PPMRL_CDTMR2 (0x8000)
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109 #define MCF_SCM_PPMRL_CDTMR3 (0x10000)
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110 #define MCF_SCM_PPMRL_CDINTC0 (0x20000)
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111 #define MCF_SCM_PPMRL_CDINTC1 (0x40000)
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112 #define MCF_SCM_PPMRL_CDFEC0 (0x200000)
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114 /* Bit definitions and macros for MCF_SCM_MPARK */
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115 #define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
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116 #define MCF_SCM_MPARK_PRKLAST (0x1000)
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117 #define MCF_SCM_MPARK_TIMEOUT (0x2000)
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118 #define MCF_SCM_MPARK_FIXED (0x4000)
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119 #define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)
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120 #define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
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121 #define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
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122 #define MCF_SCM_MPARK_BCR24BIT (0x1000000)
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123 #define MCF_SCM_MPARK_M2_P_EN (0x2000000)
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125 /* Bit definitions and macros for MCF_SCM_MPR */
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126 #define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
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128 /* Bit definitions and macros for MCF_SCM_PPMRS */
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129 #define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)
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130 #define MCF_SCM_PPMRS_DISABLE_ALL (0x40)
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131 #define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)
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132 #define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)
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133 #define MCF_SCM_PPMRS_DISABLE_PWM (0x29)
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134 #define MCF_SCM_PPMRS_DISABLE_GPT (0x28)
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135 #define MCF_SCM_PPMRS_DISABLE_ADC (0x27)
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136 #define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)
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137 #define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)
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138 #define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)
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139 #define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)
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140 #define MCF_SCM_PPMRS_DISABLE_INTC (0x11)
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141 #define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)
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142 #define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)
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143 #define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)
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144 #define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)
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145 #define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)
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146 #define MCF_SCM_PPMRS_DISABLE_I2C (0x9)
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147 #define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)
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148 #define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)
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149 #define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)
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150 #define MCF_SCM_PPMRS_DISABLE_DMA (0x4)
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151 #define MCF_SCM_PPMRS_SET_CDG (0x1)
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153 /* Bit definitions and macros for MCF_SCM_PPMRC */
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154 #define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)
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155 #define MCF_SCM_PPMRC_ENABLE_ALL (0x40)
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156 #define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)
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157 #define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)
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158 #define MCF_SCM_PPMRC_ENABLE_PWM (0x29)
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159 #define MCF_SCM_PPMRC_ENABLE_GPT (0x28)
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160 #define MCF_SCM_PPMRC_ENABLE_ADC (0x27)
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161 #define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)
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162 #define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)
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163 #define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)
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164 #define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)
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165 #define MCF_SCM_PPMRC_ENABLE_INTC (0x11)
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166 #define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)
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167 #define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)
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168 #define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)
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169 #define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)
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170 #define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)
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171 #define MCF_SCM_PPMRC_ENABLE_I2C (0x9)
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172 #define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)
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173 #define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)
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174 #define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)
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175 #define MCF_SCM_PPMRC_ENABLE_DMA (0x4)
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176 #define MCF_SCM_PPMRC_CLEAR_CDG (0x1)
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178 /* Bit definitions and macros for MCF_SCM_IPSBMT */
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179 #define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)
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180 #define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)
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181 #define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)
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182 #define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)
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183 #define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)
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184 #define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)
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185 #define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)
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186 #define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)
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187 #define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)
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188 #define MCF_SCM_IPSBMT_BME (0x8)
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190 /* Bit definitions and macros for MCF_SCM_PACR */
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191 #define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)
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192 #define MCF_SCM_PACR_LOCK0 (0x8)
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193 #define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
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194 #define MCF_SCM_PACR_LOCK1 (0x80)
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196 /* Bit definitions and macros for MCF_SCM_GPACR */
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197 #define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
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198 #define MCF_SCM_GPACR_LOCK (0x80)
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201 #endif /* __MCF52235_SCM_H__ */
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