1 /* Coldfire C Header File
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2 * Copyright Freescale Semiconductor Inc
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3 * All rights reserved.
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5 * 2008/04/17 Revision: 0.2
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7 * (c) Copyright UNIS, spol. s r.o. 1997-2008
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12 * http : www.processorexpert.com
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13 * mail : info@processorexpert.com
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16 #ifndef __MCF52259_PAD_H__
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17 #define __MCF52259_PAD_H__
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20 /*********************************************************************
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24 *********************************************************************/
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26 /* Register read/write macros */
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27 #define MCF_PAD_PSRR0 (*(vuint32*)(0x40100078))
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28 #define MCF_PAD_PDSR0 (*(vuint32*)(0x4010007C))
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29 #define MCF_PAD_PSRR1 (*(vuint32*)(0x40100080))
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30 #define MCF_PAD_PSRR2 (*(vuint16*)(0x40100086))
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31 #define MCF_PAD_PDSR1 (*(vuint32*)(0x40100088))
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32 #define MCF_PAD_PDSR2 (*(vuint16*)(0x4010008E))
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35 /* Bit definitions and macros for MCF_PAD_PSRR0 */
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36 #define MCF_PAD_PSRR0_PSRR0 (0x1)
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37 #define MCF_PAD_PSRR0_PSRR1 (0x2)
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38 #define MCF_PAD_PSRR0_PSRR2 (0x4)
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39 #define MCF_PAD_PSRR0_PSRR3 (0x8)
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40 #define MCF_PAD_PSRR0_PSRR4 (0x10)
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41 #define MCF_PAD_PSRR0_PSRR5 (0x20)
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42 #define MCF_PAD_PSRR0_PSRR6 (0x40)
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43 #define MCF_PAD_PSRR0_PSRR7 (0x80)
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44 #define MCF_PAD_PSRR0_PSRR8 (0x100)
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45 #define MCF_PAD_PSRR0_PSRR9 (0x200)
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46 #define MCF_PAD_PSRR0_PSRR10 (0x400)
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47 #define MCF_PAD_PSRR0_PSRR11 (0x800)
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48 #define MCF_PAD_PSRR0_PSRR12 (0x1000)
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49 #define MCF_PAD_PSRR0_PSRR13 (0x2000)
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50 #define MCF_PAD_PSRR0_PSRR14 (0x4000)
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51 #define MCF_PAD_PSRR0_PSRR15 (0x8000)
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52 #define MCF_PAD_PSRR0_PSRR16 (0x10000)
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53 #define MCF_PAD_PSRR0_PSRR17 (0x20000)
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54 #define MCF_PAD_PSRR0_PSRR18 (0x40000)
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55 #define MCF_PAD_PSRR0_PSRR19 (0x80000)
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56 #define MCF_PAD_PSRR0_PSRR20 (0x100000)
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57 #define MCF_PAD_PSRR0_PSRR21 (0x200000)
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58 #define MCF_PAD_PSRR0_PSRR22 (0x400000)
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59 #define MCF_PAD_PSRR0_PSRR23 (0x800000)
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60 #define MCF_PAD_PSRR0_PSRR24 (0x1000000)
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61 #define MCF_PAD_PSRR0_PSRR25 (0x2000000)
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62 #define MCF_PAD_PSRR0_PSRR26 (0x4000000)
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63 #define MCF_PAD_PSRR0_PSRR27 (0x8000000)
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64 #define MCF_PAD_PSRR0_PSRR28 (0x10000000)
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65 #define MCF_PAD_PSRR0_PSRR29 (0x20000000)
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66 #define MCF_PAD_PSRR0_PSRR30 (0x40000000)
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67 #define MCF_PAD_PSRR0_PSRR31 (0x80000000)
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69 /* Bit definitions and macros for MCF_PAD_PDSR0 */
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70 #define MCF_PAD_PDSR0_PDSR0 (0x1)
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71 #define MCF_PAD_PDSR0_PDSR1 (0x2)
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72 #define MCF_PAD_PDSR0_PDSR2 (0x4)
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73 #define MCF_PAD_PDSR0_PDSR3 (0x8)
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74 #define MCF_PAD_PDSR0_PDSR4 (0x10)
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75 #define MCF_PAD_PDSR0_PDSR5 (0x20)
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76 #define MCF_PAD_PDSR0_PDSR6 (0x40)
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77 #define MCF_PAD_PDSR0_PDSR7 (0x80)
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78 #define MCF_PAD_PDSR0_PDSR8 (0x100)
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79 #define MCF_PAD_PDSR0_PDSR9 (0x200)
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80 #define MCF_PAD_PDSR0_PDSR10 (0x400)
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81 #define MCF_PAD_PDSR0_PDSR11 (0x800)
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82 #define MCF_PAD_PDSR0_PDSR12 (0x1000)
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83 #define MCF_PAD_PDSR0_PDSR13 (0x2000)
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84 #define MCF_PAD_PDSR0_PDSR14 (0x4000)
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85 #define MCF_PAD_PDSR0_PDSR15 (0x8000)
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86 #define MCF_PAD_PDSR0_PDSR16 (0x10000)
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87 #define MCF_PAD_PDSR0_PDSR17 (0x20000)
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88 #define MCF_PAD_PDSR0_PDSR18 (0x40000)
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89 #define MCF_PAD_PDSR0_PDSR19 (0x80000)
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90 #define MCF_PAD_PDSR0_PDSR20 (0x100000)
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91 #define MCF_PAD_PDSR0_PDSR21 (0x200000)
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92 #define MCF_PAD_PDSR0_PDSR22 (0x400000)
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93 #define MCF_PAD_PDSR0_PDSR23 (0x800000)
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94 #define MCF_PAD_PDSR0_PDSR24 (0x1000000)
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95 #define MCF_PAD_PDSR0_PDSR25 (0x2000000)
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96 #define MCF_PAD_PDSR0_PDSR26 (0x4000000)
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97 #define MCF_PAD_PDSR0_PDSR27 (0x8000000)
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98 #define MCF_PAD_PDSR0_PDSR28 (0x10000000)
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99 #define MCF_PAD_PDSR0_PDSR29 (0x20000000)
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100 #define MCF_PAD_PDSR0_PDSR30 (0x40000000)
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101 #define MCF_PAD_PDSR0_PDSR31 (0x80000000)
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103 /* Bit definitions and macros for MCF_PAD_PSRR1 */
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104 #define MCF_PAD_PSRR1_PSRR32 (0x1)
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105 #define MCF_PAD_PSRR1_PSRR33 (0x2)
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106 #define MCF_PAD_PSRR1_PSRR34 (0x4)
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107 #define MCF_PAD_PSRR1_PSRR35 (0x8)
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108 #define MCF_PAD_PSRR1_PSRR36 (0x10)
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109 #define MCF_PAD_PSRR1_PSRR37 (0x20)
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110 #define MCF_PAD_PSRR1_PSRR38 (0x40)
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111 #define MCF_PAD_PSRR1_PSRR39 (0x80)
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112 #define MCF_PAD_PSRR1_PSRR40 (0x100)
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113 #define MCF_PAD_PSRR1_PSRR41 (0x200)
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114 #define MCF_PAD_PSRR1_PSRR42 (0x400)
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115 #define MCF_PAD_PSRR1_PSRR43 (0x800)
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116 #define MCF_PAD_PSRR1_PSRR44 (0x1000)
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117 #define MCF_PAD_PSRR1_PSRR45 (0x2000)
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118 #define MCF_PAD_PSRR1_PSRR46 (0x4000)
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119 #define MCF_PAD_PSRR1_PSRR47 (0x8000)
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120 #define MCF_PAD_PSRR1_PSRR48 (0x10000)
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121 #define MCF_PAD_PSRR1_PSRR49 (0x20000)
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122 #define MCF_PAD_PSRR1_PSRR50 (0x40000)
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123 #define MCF_PAD_PSRR1_PSRR51 (0x80000)
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124 #define MCF_PAD_PSRR1_PSRR52 (0x100000)
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125 #define MCF_PAD_PSRR1_PSRR53 (0x200000)
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126 #define MCF_PAD_PSRR1_PSRR54 (0x400000)
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127 #define MCF_PAD_PSRR1_PSRR55 (0x800000)
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128 #define MCF_PAD_PSRR1_PSRR56 (0x1000000)
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129 #define MCF_PAD_PSRR1_PSRR57 (0x2000000)
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130 #define MCF_PAD_PSRR1_PSRR58 (0x4000000)
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131 #define MCF_PAD_PSRR1_PSRR59 (0x8000000)
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132 #define MCF_PAD_PSRR1_PSRR60 (0x10000000)
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133 #define MCF_PAD_PSRR1_PSRR61 (0x20000000)
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134 #define MCF_PAD_PSRR1_PSRR62 (0x40000000)
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135 #define MCF_PAD_PSRR1_PSRR63 (0x80000000)
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137 /* Bit definitions and macros for MCF_PAD_PSRR2 */
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138 #define MCF_PAD_PSRR2_PSRR64 (0x1)
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139 #define MCF_PAD_PSRR2_PSRR65 (0x2)
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140 #define MCF_PAD_PSRR2_PSRR66 (0x4)
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141 #define MCF_PAD_PSRR2_PSRR67 (0x8)
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142 #define MCF_PAD_PSRR2_PSRR68 (0x10)
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143 #define MCF_PAD_PSRR2_PSRR69 (0x20)
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144 #define MCF_PAD_PSRR2_PSRR70 (0x40)
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145 #define MCF_PAD_PSRR2_PSRR71 (0x80)
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146 #define MCF_PAD_PSRR2_PSRR72 (0x100)
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147 #define MCF_PAD_PSRR2_PSRR73 (0x200)
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148 #define MCF_PAD_PSRR2_PSRR74 (0x400)
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149 #define MCF_PAD_PSRR2_PSRR75 (0x800)
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150 #define MCF_PAD_PSRR2_PSRR76 (0x1000)
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151 #define MCF_PAD_PSRR2_PSRR77 (0x2000)
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152 #define MCF_PAD_PSRR2_PSRR78 (0x4000)
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153 #define MCF_PAD_PSRR2_PSRR79 (0x8000)
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155 /* Bit definitions and macros for MCF_PAD_PDSR1 */
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156 #define MCF_PAD_PDSR1_PDSR32 (0x1)
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157 #define MCF_PAD_PDSR1_PDSR33 (0x2)
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158 #define MCF_PAD_PDSR1_PDSR34 (0x4)
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159 #define MCF_PAD_PDSR1_PDSR35 (0x8)
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160 #define MCF_PAD_PDSR1_PDSR36 (0x10)
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161 #define MCF_PAD_PDSR1_PDSR37 (0x20)
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162 #define MCF_PAD_PDSR1_PDSR38 (0x40)
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163 #define MCF_PAD_PDSR1_PDSR39 (0x80)
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164 #define MCF_PAD_PDSR1_PDSR40 (0x100)
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165 #define MCF_PAD_PDSR1_PDSR41 (0x200)
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166 #define MCF_PAD_PDSR1_PDSR42 (0x400)
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167 #define MCF_PAD_PDSR1_PDSR43 (0x800)
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168 #define MCF_PAD_PDSR1_PDSR44 (0x1000)
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169 #define MCF_PAD_PDSR1_PDSR45 (0x2000)
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170 #define MCF_PAD_PDSR1_PDSR46 (0x4000)
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171 #define MCF_PAD_PDSR1_PDSR47 (0x8000)
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172 #define MCF_PAD_PDSR1_PDSR48 (0x10000)
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173 #define MCF_PAD_PDSR1_PDSR49 (0x20000)
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174 #define MCF_PAD_PDSR1_PDSR50 (0x40000)
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175 #define MCF_PAD_PDSR1_PDSR51 (0x80000)
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176 #define MCF_PAD_PDSR1_PDSR52 (0x100000)
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177 #define MCF_PAD_PDSR1_PDSR53 (0x200000)
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178 #define MCF_PAD_PDSR1_PDSR54 (0x400000)
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179 #define MCF_PAD_PDSR1_PDSR55 (0x800000)
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180 #define MCF_PAD_PDSR1_PDSR56 (0x1000000)
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181 #define MCF_PAD_PDSR1_PDSR57 (0x2000000)
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182 #define MCF_PAD_PDSR1_PDSR58 (0x4000000)
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183 #define MCF_PAD_PDSR1_PDSR59 (0x8000000)
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184 #define MCF_PAD_PDSR1_PDSR60 (0x10000000)
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185 #define MCF_PAD_PDSR1_PDSR61 (0x20000000)
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186 #define MCF_PAD_PDSR1_PDSR62 (0x40000000)
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187 #define MCF_PAD_PDSR1_PDSR63 (0x80000000)
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189 /* Bit definitions and macros for MCF_PAD_PDSR2 */
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190 #define MCF_PAD_PDSR2_PDSR64 (0x1)
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191 #define MCF_PAD_PDSR2_PDSR65 (0x2)
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192 #define MCF_PAD_PDSR2_PDSR66 (0x4)
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193 #define MCF_PAD_PDSR2_PDSR67 (0x8)
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194 #define MCF_PAD_PDSR2_PDSR68 (0x10)
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195 #define MCF_PAD_PDSR2_PDSR69 (0x20)
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196 #define MCF_PAD_PDSR2_PDSR70 (0x40)
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197 #define MCF_PAD_PDSR2_PDSR71 (0x80)
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198 #define MCF_PAD_PDSR2_PDSR72 (0x100)
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199 #define MCF_PAD_PDSR2_PDSR73 (0x200)
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200 #define MCF_PAD_PDSR2_PDSR74 (0x400)
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201 #define MCF_PAD_PDSR2_PDSR75 (0x800)
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202 #define MCF_PAD_PDSR2_PDSR76 (0x1000)
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203 #define MCF_PAD_PDSR2_PDSR77 (0x2000)
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204 #define MCF_PAD_PDSR2_PDSR78 (0x4000)
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205 #define MCF_PAD_PDSR2_PDSR79 (0x8000)
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208 #endif /* __MCF52259_PAD_H__ */
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