3 ; Set VBR to the beginning of what will be SRAM
\r
4 ; VBR is an absolute CPU register
\r
5 writecontrolreg 0x0801 0x20000000
\r
8 writecontrolreg 0x0C05 0x20000021
\r
10 ; Set FLASHBAR (Flash)
\r
11 writecontrolreg 0x0C04 0x00000061
\r
13 ; Enable PST[3:0] signals
\r
14 writemem.b 0x40100074 0x0F
\r