3 * Purpose: Reset configuration of the M52259EVB
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5 * License: All software covered by license agreement in -
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6 * docs/Freescale_Software_License.pdf
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11 /********************************************************************/
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13 void mcf5225x_init(void);
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14 void mcf5225x_wtm_init(void);
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15 void mcf5225x_pll_init(void);
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16 void mcf5225x_uart_init(void);
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17 void mcf5225x_scm_init(void);
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18 void mcf5225x_gpio_init(void);
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20 /********************************************************************/
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25 register uint8 *dp, *sp;
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29 * Allow interrupts from ABORT, SW1, SW2 (IRQ[1,5,7])
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30 * and USB (IRQ[2,6])
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34 /* Enable IRQ signals on the port */
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36 | MCF_GPIO_PNQPAR_IRQ1_IRQ1
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37 | MCF_GPIO_PNQPAR_IRQ5_IRQ5
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38 | MCF_GPIO_PNQPAR_IRQ7_IRQ7;
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40 /* Set EPORT to look for falling edges */
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42 | MCF_EPORT_EPPAR_EPPA1_FALLING
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43 | MCF_EPORT_EPPAR_EPPA2_FALLING
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44 | MCF_EPORT_EPPAR_EPPA5_FALLING
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45 | MCF_EPORT_EPPAR_EPPA6_FALLING
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46 | MCF_EPORT_EPPAR_EPPA7_FALLING;
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48 /* Clear any currently triggered events on the EPORT */
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50 | MCF_EPORT_EPIER_EPIE1
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51 | MCF_EPORT_EPIER_EPIE2
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52 | MCF_EPORT_EPIER_EPIE5
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53 | MCF_EPORT_EPIER_EPIE6
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54 | MCF_EPORT_EPIER_EPIE7;
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56 /* Enable interrupts in the interrupt controller */
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57 MCF_INTC0_IMRL &= ~(0
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58 | MCF_INTC_IMRL_INT_MASK1
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59 | MCF_INTC_IMRL_INT_MASK2
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60 | MCF_INTC_IMRL_INT_MASK5
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61 | MCF_INTC_IMRL_INT_MASK6
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62 | MCF_INTC_IMRL_INT_MASK7
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63 | MCF_INTC_IMRL_MASKALL);
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67 MCF_GPIO_PDDPAR = 0x0F;
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69 /* Set real time clock freq */
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71 MCF_CLOCK_RTCCR = 48000000;
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73 /* Copy the vector table to RAM */
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74 if (__VECTOR_RAM != VECTOR_TABLE)
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76 for (n = 0; n < 256; n++)
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77 __VECTOR_RAM[n] = VECTOR_TABLE[n];
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79 mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);
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83 * Move initialized data from ROM to RAM.
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85 if (__DATA_ROM != __DATA_RAM)
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87 dp = (uint8 *)__DATA_RAM;
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88 sp = (uint8 *)__DATA_ROM;
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89 n = (uint32)(__DATA_END - __DATA_RAM);
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95 * Zero uninitialized data
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97 if (__BSS_START != __BSS_END)
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99 sp = (uint8 *)__BSS_START;
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100 n = (uint32)(__BSS_END - __BSS_START);
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104 mcf5225x_wtm_init();
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106 mcf5225x_pll_init();
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107 mcf5225x_scm_init();
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108 mcf5225x_uart_init();
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110 /********************************************************************/
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112 mcf5225x_wtm_init(void)
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115 * Disable Software Watchdog Timer
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119 /********************************************************************/
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121 mcf5225x_pll_init(void)
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123 /*Required if booting with internal relaxation oscillator & pll off, clkmod[1:0]=00 & xtal=1 */
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124 #ifndef OMIT_OCLR_CONFIGURATION
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125 MCF_CLOCK_OCLR = 0xC0; //turn on crystal
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126 MCF_CLOCK_CCLR = 0x00; //switch to crystal
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127 MCF_CLOCK_OCHR = 0x00; //turn off relaxation osc
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130 /* The PLL pre divider - 48MHz / 6 = 8MHz */
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131 MCF_CLOCK_CCHR =0x05;
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134 /* The PLL pre-divider affects this!!!
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135 * Multiply 48Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz
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138 MCF_CLOCK_SYNCR &= ~(MCF_CLOCK_SYNCR_PLLEN);
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140 MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_CLKSRC | MCF_CLOCK_SYNCR_PLLMODE;
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143 MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_RFD(0);
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145 //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(0);
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147 //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(2);
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149 //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(3);
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151 //MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(2) | MCF_CLOCK_SYNCR_RFD(6);
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153 MCF_CLOCK_SYNCR |= MCF_CLOCK_SYNCR_PLLEN;
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156 while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
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160 /********************************************************************/
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162 mcf5225x_scm_init(void)
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165 * Enable on-chip modules to access internal SRAM
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167 MCF_SCM_RAMBAR = (0
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168 | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS)
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169 | MCF_SCM_RAMBAR_BDE);
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171 /********************************************************************/
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173 mcf5225x_gpio_init(void)
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176 * Initialize Port TA to enable Axcel control
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178 MCF_GPIO_PTAPAR = 0x00;
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179 MCF_GPIO_DDRTA = 0x0F;
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180 MCF_GPIO_PORTTA = 0x04;
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183 /********************************************************************/
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185 mcf5225x_uart_init(void)
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188 * Initialize all three UARTs for serial communications
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191 register uint16 ubgs;
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194 * Set Port UA to initialize URXD0/UTXD0
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196 MCF_GPIO_PUAPAR = 0
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197 | MCF_GPIO_PUAPAR_URXD0_URXD0
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198 | MCF_GPIO_PUAPAR_UTXD0_UTXD0;
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200 MCF_GPIO_PUBPAR = 0
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201 | MCF_GPIO_PUBPAR_URXD1_URXD1
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202 | MCF_GPIO_PUBPAR_UTXD1_UTXD1;
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204 MCF_GPIO_PUCPAR = 0
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205 | MCF_GPIO_PUCPAR_URXD2_URXD2
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206 | MCF_GPIO_PUCPAR_UTXD2_UTXD2;
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209 * Reset Transmitter
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211 MCF_UART0_UCR = MCF_UART_UCR_RESET_TX;
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212 MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;
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213 MCF_UART2_UCR = MCF_UART_UCR_RESET_TX;
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218 MCF_UART0_UCR = MCF_UART_UCR_RESET_RX;
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219 MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;
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220 MCF_UART2_UCR = MCF_UART_UCR_RESET_RX;
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223 * Reset Mode Register
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225 MCF_UART0_UCR = MCF_UART_UCR_RESET_MR;
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226 MCF_UART1_UCR = MCF_UART_UCR_RESET_MR;
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227 MCF_UART2_UCR = MCF_UART_UCR_RESET_MR;
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230 * No parity, 8-bits per character
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232 MCF_UART0_UMR1 = (0
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233 | MCF_UART_UMR_PM_NONE
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234 | MCF_UART_UMR_BC_8 );
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235 MCF_UART1_UMR1 = (0
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236 | MCF_UART_UMR_PM_NONE
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237 | MCF_UART_UMR_BC_8 );
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238 MCF_UART2_UMR1 = (0
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239 | MCF_UART_UMR_PM_NONE
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240 | MCF_UART_UMR_BC_8 );
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243 * No echo or loopback, 1 stop bit
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245 MCF_UART0_UMR2 = (0
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246 | MCF_UART_UMR_CM_NORMAL
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247 | MCF_UART_UMR_SB_STOP_BITS_1);
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248 MCF_UART1_UMR2 = (0
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249 | MCF_UART_UMR_CM_NORMAL
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250 | MCF_UART_UMR_SB_STOP_BITS_1);
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251 MCF_UART2_UMR2 = (0
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252 | MCF_UART_UMR_CM_NORMAL
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253 | MCF_UART_UMR_SB_STOP_BITS_1);
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256 * Set Rx and Tx baud by SYSTEM CLOCK
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258 MCF_UART0_UCSR = (0
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259 | MCF_UART_UCSR_RCS_SYS_CLK
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260 | MCF_UART_UCSR_TCS_SYS_CLK);
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261 MCF_UART1_UCSR = (0
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262 | MCF_UART_UCSR_RCS_SYS_CLK
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263 | MCF_UART_UCSR_TCS_SYS_CLK);
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264 MCF_UART2_UCSR = (0
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265 | MCF_UART_UCSR_RCS_SYS_CLK
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266 | MCF_UART_UCSR_TCS_SYS_CLK);
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269 * Mask all UART interrupts
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271 MCF_UART0_UIMR = 0;
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272 MCF_UART1_UIMR = 0;
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273 MCF_UART2_UIMR = 0;
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276 * Calculate baud settings
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278 ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));
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280 MCF_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
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281 MCF_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
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282 MCF_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
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283 MCF_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
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284 MCF_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
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285 MCF_UART2_UBG2 = (uint8)(ubgs & 0x00FF);
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288 * Enable receiver and transmitter
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291 | MCF_UART_UCR_TX_ENABLED
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292 | MCF_UART_UCR_RX_ENABLED);
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294 | MCF_UART_UCR_TX_ENABLED
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295 | MCF_UART_UCR_RX_ENABLED);
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297 | MCF_UART_UCR_TX_ENABLED
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298 | MCF_UART_UCR_RX_ENABLED);
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301 /********************************************************************/
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