3 * Purpose: Lowest level routines for all ColdFire processors.
\r
7 * License: All software covered by license agreement in -
\r
8 * docs/Freescale_Software_License.pdf
\r
11 #define mcf5xxx_exception_handler _mcf5xxx_exception_handler
\r
13 .extern mcf5xxx_exception_handler
\r
15 .global asm_exception_handler
\r
16 .global _asm_exception_handler
\r
18 .global _asm_set_ipl
\r
19 .global mcf5xxx_exe_wdebug
\r
20 .global _mcf5xxx_exe_wdebug
\r
21 .global mcf5xxx_move_line //added by Mac
\r
22 .global _mcf5xxx_move_line //added by Mac
\r
23 .global mcf5xxx_wr_cacr
\r
24 .global _mcf5xxx_wr_cacr
\r
25 .global mcf5xxx_wr_asid
\r
26 .global _mcf5xxx_wr_asid
\r
27 .global mcf5xxx_wr_acr0
\r
28 .global _mcf5xxx_wr_acr0
\r
29 .global mcf5xxx_wr_acr1
\r
30 .global _mcf5xxx_wr_acr1
\r
31 .global mcf5xxx_wr_acr2
\r
32 .global _mcf5xxx_wr_acr2
\r
33 .global mcf5xxx_wr_acr3
\r
34 .global _mcf5xxx_wr_acr3
\r
35 .global mcf5xxx_wr_mmubar
\r
36 .global _mcf5xxx_wr_mmubar
\r
37 .global mcf5xxx_wr_other_a7
\r
38 .global _mcf5xxx_wr_other_a7
\r
39 .global mcf5xxx_wr_vbr
\r
40 .global _mcf5xxx_wr_vbr
\r
41 .global mcf5xxx_wr_macsr
\r
42 .global _mcf5xxx_wr_macsr
\r
43 .global mcf5xxx_wr_mask
\r
44 .global _mcf5xxx_wr_mask
\r
45 .global mcf5xxx_wr_acc0
\r
46 .global _mcf5xxx_wr_acc0
\r
47 .global mcf5xxx_wr_accext01
\r
48 .global _mcf5xxx_wr_accext01
\r
49 .global mcf5xxx_wr_accext23
\r
50 .global _mcf5xxx_wr_accext23
\r
51 .global mcf5xxx_wr_acc1
\r
52 .global _mcf5xxx_wr_acc1
\r
53 .global mcf5xxx_wr_acc2
\r
54 .global _mcf5xxx_wr_acc2
\r
55 .global mcf5xxx_wr_acc3
\r
56 .global _mcf5xxx_wr_acc3
\r
57 .global mcf5xxx_wr_sr
\r
58 .global _mcf5xxx_wr_sr
\r
59 .global mcf5xxx_wr_pc
\r
60 .global _mcf5xxx_wr_pc
\r
61 .global mcf5xxx_wr_rombar0
\r
62 .global _mcf5xxx_wr_rombar0
\r
63 .global mcf5xxx_wr_rombar1
\r
64 .global _mcf5xxx_wr_rombar1
\r
65 .global mcf5xxx_wr_rambar0
\r
66 .global _mcf5xxx_wr_rambar0
\r
67 .global mcf5xxx_wr_rambar1
\r
68 .global _mcf5xxx_wr_rambar1
\r
69 .global mcf5xxx_wr_mpcr
\r
70 .global _mcf5xxx_wr_mpcr
\r
71 .global mcf5xxx_wr_secmbar
\r
72 .global _mcf5xxx_wr_secmbar
\r
73 .global mcf5xxx_wr_mbar
\r
74 .global _mcf5xxx_wr_mbar
\r
78 /********************************************************************
\r
79 * This routine is the lowest-level exception handler.
\r
82 asm_exception_handler:
\r
83 _asm_exception_handler:
\r
85 movem.l D0-D1/A0-A1,(SP)
\r
88 jsr mcf5xxx_exception_handler
\r
90 movem.l (SP),D0-D1/A0-A1
\r
94 /********************************************************************/
\r
96 * This routines changes the IPL to the value passed into the routine.
\r
97 * It also returns the old IPL value back.
\r
98 * Calling convention from C:
\r
99 * old_ipl = asm_set_ipl(new_ipl);
\r
100 * For the Diab Data C compiler, it passes return value thru D0.
\r
101 * Note that only the least significant three bits of the passed
\r
110 move.w SR,D7 /* current sr */
\r
112 move.l D7,D0 /* prepare return value */
\r
113 andi.l #0x0700,D0 /* mask out IPL */
\r
114 lsr.l #8,D0 /* IPL */
\r
116 move.l 8(A6),D6 /* get argument */
\r
117 andi.l #0x07,D6 /* least significant three bits */
\r
118 lsl.l #8,D6 /* move over to make mask */
\r
120 andi.l #0x0000F8FF,D7 /* zero out current IPL */
\r
121 or.l D6,D7 /* place new IPL in sr */
\r
129 /********************************************************************/
\r
131 * These routines execute special ColdFire instructions
\r
134 mcf5xxx_exe_wdebug:
\r
135 _mcf5xxx_exe_wdebug:
\r
141 _mcf5xxx_move_line:
\r
143 movem.l d0-d3/a0-a1,(sp)
\r
144 movea.l 28(sp),a0 /* source in a0 */
\r
145 movea.l 32(sp),a1 /* destination in a1 */
\r
146 movem.l (a0),d0-d3 /* move line from source */
\r
147 movem.l d0-d3,(a1) /* move line to destination */
\r
148 movem.l (sp),d0-d3/a0-a1
\r
153 /********************************************************************/
\r
155 * These routines write to the special purpose registers in the ColdFire
\r
156 * core. Since these registers are write-only in the supervisor model,
\r
157 * no corresponding read routines exist.
\r
169 .long 0x4e7b0002 /* movec d0,cacr */
\r
176 .long 0x4e7b0003 /* movec d0,asid */
\r
183 .long 0x4e7b0004 /* movec d0,ACR0 */
\r
190 .long 0x4e7b0005 /* movec d0,ACR1 */
\r
197 .long 0x4e7b0006 /* movec d0,ACR2 */
\r
204 .long 0x4e7b0007 /* movec d0,ACR3 */
\r
209 _mcf5xxx_wr_mmubar:
\r
211 .long 0x4e7b0008 /* movec d0,MBAR */
\r
215 mcf5xxx_wr_other_a7:
\r
216 _mcf5xxx_wr_other_a7:
\r
218 .long 0x4e7b0800 /* movec d0,OTHER_A7 */
\r
225 .long 0x4e7b0801 /* movec d0,VBR */
\r
232 .long 0x4e7b0804 /* movec d0,MACSR */
\r
239 .long 0x4e7b0805 /* movec d0,MASK */
\r
246 .long 0x4e7b0806 /* movec d0,ACC0 */
\r
250 mcf5xxx_wr_accext01:
\r
251 _mcf5xxx_wr_accext01:
\r
253 .long 0x4e7b0807 /* movec d0,ACCEXT01 */
\r
257 mcf5xxx_wr_accext23:
\r
258 _mcf5xxx_wr_accext23:
\r
260 .long 0x4e7b0808 /* movec d0,ACCEXT23 */
\r
267 .long 0x4e7b0809 /* movec d0,ACC1 */
\r
274 .long 0x4e7b080A /* movec d0,ACC2 */
\r
281 .long 0x4e7b080B /* movec d0,ACC3 */
\r
288 .long 0x4e7b080F /* movec d0,PC */
\r
292 mcf5xxx_wr_rombar0:
\r
293 _mcf5xxx_wr_rombar0:
\r
295 .long 0x4e7b0C00 /* movec d0,ROMBAR0 */
\r
299 mcf5xxx_wr_rombar1:
\r
300 _mcf5xxx_wr_rombar1:
\r
302 .long 0x4e7b0C01 /* movec d0,ROMBAR1 */
\r
306 mcf5xxx_wr_rambar0:
\r
307 _mcf5xxx_wr_rambar0:
\r
309 .long 0x4e7b0C04 /* movec d0,RAMBAR0 */
\r
313 mcf5xxx_wr_rambar1:
\r
314 _mcf5xxx_wr_rambar1:
\r
316 .long 0x4e7b0C05 /* movec d0,RAMBAR1 */
\r
323 .long 0x4e7b0C0C /* movec d0,MPCR */
\r
327 mcf5xxx_wr_secmbar:
\r
328 _mcf5xxx_wr_secmbar:
\r
330 .long 0x4e7b0C0E /* movec d0,MBAR1 */
\r
337 .long 0x4e7b0C0F /* movec d0,MBAR0 */
\r
341 /********************************************************************/
\r