]> git.sur5r.net Git - freertos/blob - Demo/ColdFire_MCF52259_CodeWarrior/main.c
Remove unnecessary use of portLONG, portCHAR and portSHORT.
[freertos] / Demo / ColdFire_MCF52259_CodeWarrior / main.c
1 /*\r
2     FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.\r
3 \r
4     This file is part of the FreeRTOS distribution.\r
5 \r
6     FreeRTOS is free software; you can redistribute it and/or modify it    under\r
7     the terms of the GNU General Public License (version 2) as published by the\r
8     Free Software Foundation and modified by the FreeRTOS exception.\r
9     **NOTE** The exception to the GPL is included to allow you to distribute a\r
10     combined work that includes FreeRTOS without being obliged to provide the\r
11     source code for proprietary components outside of the FreeRTOS kernel.\r
12     Alternative commercial license and support terms are also available upon\r
13     request.  See the licensing section of http://www.FreeRTOS.org for full\r
14     license details.\r
15 \r
16     FreeRTOS is distributed in the hope that it will be useful,    but WITHOUT\r
17     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
18     FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
19     more details.\r
20 \r
21     You should have received a copy of the GNU General Public License along\r
22     with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
23     Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
24 \r
25 \r
26     ***************************************************************************\r
27     *                                                                         *\r
28     * The FreeRTOS eBook and reference manual are available to purchase for a *\r
29     * small fee. Help yourself get started quickly while also helping the     *\r
30     * FreeRTOS project! See http://www.FreeRTOS.org/Documentation for details *\r
31     *                                                                         *\r
32     ***************************************************************************\r
33 \r
34     1 tab == 4 spaces!\r
35 \r
36     Please ensure to read the configuration and relevant port sections of the\r
37     online documentation.\r
38 \r
39     http://www.FreeRTOS.org - Documentation, latest information, license and\r
40     contact details.\r
41 \r
42     http://www.SafeRTOS.com - A version that is certified for use in safety\r
43     critical systems.\r
44 \r
45     http://www.OpenRTOS.com - Commercial support, development, porting,\r
46     licensing and training services.\r
47 */\r
48 \r
49 \r
50 /*\r
51  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
52  * documentation provides more details of the standard demo application tasks.\r
53  * In addition to the standard demo tasks, the following tasks and tests are\r
54  * defined and/or created within this file:\r
55  *\r
56  * "Web server" - Very basic demonstration of the lwIP stack.  The WEB server\r
57  * simply generates a page that shows the current state of all the tasks within\r
58  * the system, including the high water mark of each task stack. The high water\r
59  * mark is displayed as the amount of stack that has never been used, so the\r
60  * closer the value is to zero the closer the task has come to overflowing its\r
61  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.\r
62  *\r
63  * "Check" task -  This only executes every five seconds but has a high priority\r
64  * to ensure it gets processor time.  Its main function is to check that all the\r
65  * standard demo tasks are still operational.  While no errors have been\r
66  * discovered the check task will toggle an LED every 5 seconds - the toggle\r
67  * rate increasing to 500ms being a visual indication that at least one task has\r
68  * reported unexpected behaviour.\r
69  *\r
70  * "Reg test" tasks - These fill the registers with known values, then check\r
71  * that each register still contains its expected value.  Each task uses\r
72  * different values.  The tasks run with very low priority so get preempted very\r
73  * frequently.  A register containing an unexpected value is indicative of an\r
74  * error in the context switching mechanism.\r
75  *\r
76  */\r
77 \r
78 /* Standard includes. */\r
79 #include <stdio.h>\r
80 \r
81 /* Scheduler includes. */\r
82 #include "FreeRTOS.h"\r
83 #include "task.h"\r
84 #include "queue.h"\r
85 #include "semphr.h"\r
86 \r
87 /* Demo app includes. */\r
88 #include "BlockQ.h"\r
89 #include "death.h"\r
90 #include "flash.h"\r
91 #include "partest.h"\r
92 #include "semtest.h"\r
93 #include "PollQ.h"\r
94 #include "GenQTest.h"\r
95 #include "QPeek.h"\r
96 #include "recmutex.h"\r
97 \r
98 /*-----------------------------------------------------------*/\r
99 \r
100 /* The time between cycles of the 'check' functionality - as described at the\r
101 top of this file. */\r
102 #define mainNO_ERROR_PERIOD                                     ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
103 \r
104 /* The rate at which the LED controlled by the 'check' task will flash should an\r
105 error have been detected. */\r
106 #define mainERROR_PERIOD                                        ( ( portTickType ) 500 / portTICK_RATE_MS )\r
107 \r
108 /* The LED controlled by the 'check' task. */\r
109 #define mainCHECK_LED                                           ( 3 )\r
110 \r
111 /* ComTest constants - there is no free LED for the comtest tasks. */\r
112 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned portLONG ) 19200 )\r
113 #define mainCOM_TEST_LED                                        ( 5 )\r
114 \r
115 /* Task priorities. */\r
116 #define mainCOM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
117 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
118 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
119 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
120 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
121 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
122 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
123 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
124 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
125 \r
126 /*\r
127  * Configure the hardware for the demo.\r
128  */\r
129 static void prvSetupHardware( void );\r
130 \r
131 /*\r
132  * Implements the 'check' task functionality as described at the top of this\r
133  * file.\r
134  */\r
135 static void prvCheckTask( void *pvParameters );\r
136 \r
137 /*\r
138  * Implement the 'Reg test' functionality as described at the top of this file.\r
139  */\r
140 static void vRegTest1Task( void *pvParameters );\r
141 static void vRegTest2Task( void *pvParameters );\r
142 \r
143 /*-----------------------------------------------------------*/\r
144 \r
145 /* Counters used to detect errors within the reg test tasks. */\r
146 static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
147 \r
148 /*-----------------------------------------------------------*/\r
149 \r
150 int main( void )\r
151 {\r
152 extern void vBasicWEBServer( void *pv );\r
153 \r
154         /* Setup the hardware ready for this demo. */\r
155         prvSetupHardware();\r
156         ( void )sys_thread_new("HTTPD", vBasicWEBServer, NULL, 320, mainWEB_TASK_PRIORITY );\r
157 \r
158         /* Start the standard demo tasks. */\r
159         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
160         vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
161         vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
162         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
163         vStartQueuePeekTasks();\r
164         vStartRecursiveMutexTasks();\r
165         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
166 \r
167         /* Start the reg test tasks - defined in this file. */\r
168         xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
169         xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
170 \r
171         /* Create the check task. */\r
172         xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
173 \r
174         /* The suicide tasks must be created last as they need to know how many\r
175         tasks were running prior to their creation in order to ascertain whether\r
176         or not the correct/expected number of tasks are running at any given time. */\r
177     vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
178 \r
179         /* Start the scheduler. */\r
180         vTaskStartScheduler();\r
181 \r
182     /* Will only get here if there was insufficient memory to create the idle\r
183     task. */\r
184         for( ;; )\r
185         {\r
186         }\r
187 }\r
188 /*-----------------------------------------------------------*/\r
189 \r
190 static void prvCheckTask( void *pvParameters )\r
191 {\r
192 unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
193 portTickType xLastExecutionTime;\r
194 \r
195         ( void ) pvParameters;\r
196 \r
197         /* Initialise the variable used to control our iteration rate prior to\r
198         its first use. */\r
199         xLastExecutionTime = xTaskGetTickCount();\r
200 \r
201         for( ;; )\r
202         {\r
203                 /* Wait until it is time to run the tests again. */\r
204                 vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
205 \r
206                 /* Has an error been found in any task? */\r
207                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
208                 {\r
209                         ulError |= 0x01UL;\r
210                 }\r
211 \r
212                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
213                 {\r
214                         ulError |= 0x02UL;\r
215                 }\r
216 \r
217                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
218                 {\r
219                         ulError |= 0x04UL;\r
220                 }\r
221 \r
222                 if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
223             {\r
224                 ulError |= 0x20UL;\r
225             }\r
226 \r
227                 if( xArePollingQueuesStillRunning() != pdTRUE )\r
228             {\r
229                 ulError |= 0x40UL;\r
230             }\r
231 \r
232                 if( xIsCreateTaskStillRunning() != pdTRUE )\r
233             {\r
234                 ulError |= 0x80UL;\r
235             }\r
236 \r
237                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
238             {\r
239                 ulError |= 0x200UL;\r
240             }\r
241 \r
242                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
243                 {\r
244                         ulError |= 0x1000UL;\r
245                 }\r
246 \r
247                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
248                 {\r
249                         ulError |= 0x1000UL;\r
250                 }\r
251 \r
252                 ulLastRegTest1Count = ulRegTest1Counter;\r
253                 ulLastRegTest2Count = ulRegTest2Counter;\r
254 \r
255                 /* If an error has been found then increase our cycle rate, and in so\r
256                 going increase the rate at which the check task LED toggles. */\r
257                 if( ulError != 0 )\r
258                 {\r
259                 ulTicksToWait = mainERROR_PERIOD;\r
260                 }\r
261 \r
262                 /* Toggle the LED each itteration. */\r
263                 vParTestToggleLED( mainCHECK_LED );\r
264         }\r
265 }\r
266 /*-----------------------------------------------------------*/\r
267 \r
268 void prvSetupHardware( void )\r
269 {\r
270         portDISABLE_INTERRUPTS();\r
271 \r
272         /* Setup the port used to toggle LEDs. */\r
273         vParTestInitialise();\r
274 }\r
275 /*-----------------------------------------------------------*/\r
276 \r
277 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
278 {\r
279         /* This will get called if a stack overflow is detected during the context\r
280         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
281         problems within nested interrupts, but only do this for debug purposes as\r
282         it will increase the context switch time. */\r
283 \r
284         ( void ) pxTask;\r
285         ( void ) pcTaskName;\r
286 \r
287         for( ;; )\r
288         {\r
289         }\r
290 }\r
291 /*-----------------------------------------------------------*/\r
292 \r
293 static void vRegTest1Task( void *pvParameters )\r
294 {\r
295         /* Sanity check - did we receive the parameter expected? */\r
296         if( pvParameters != &ulRegTest1Counter )\r
297         {\r
298                 /* Change here so the check task can detect that an error occurred. */\r
299                 for( ;; )\r
300                 {\r
301                 }\r
302         }\r
303 \r
304         /* Set all the registers to known values, then check that each retains its\r
305         expected value - as described at the top of this file.  If an error is\r
306         found then the loop counter will no longer be incremented allowing the check\r
307         task to recognise the error. */\r
308         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
309                                                 "       moveq           #1, d0                                  \n\t"\r
310                                                 "       moveq           #2, d1                                  \n\t"\r
311                                                 "       moveq           #3, d2                                  \n\t"\r
312                                                 "       moveq           #4, d3                                  \n\t"\r
313                                                 "       moveq           #5, d4                                  \n\t"\r
314                                                 "       moveq           #6, d5                                  \n\t"\r
315                                                 "       moveq           #7, d6                                  \n\t"\r
316                                                 "       moveq           #8, d7                                  \n\t"\r
317                                                 "       move            #9, a0                                  \n\t"\r
318                                                 "       move            #10, a1                                 \n\t"\r
319                                                 "       move            #11, a2                                 \n\t"\r
320                                                 "       move            #12, a3                                 \n\t"\r
321                                                 "       move            #13, a4                                 \n\t"\r
322                                                 "       move            #14, a5                                 \n\t"\r
323                                                 "       move            #15, a6                                 \n\t"\r
324                                                 "                                                                               \n\t"\r
325                                                 "       cmpi.l          #1, d0                                  \n\t"\r
326                                                 "       bne                     reg_test_1_error                \n\t"\r
327                                                 "       cmpi.l          #2, d1                                  \n\t"\r
328                                                 "       bne                     reg_test_1_error                \n\t"\r
329                                                 "       cmpi.l          #3, d2                                  \n\t"\r
330                                                 "       bne                     reg_test_1_error                \n\t"\r
331                                                 "       cmpi.l          #4, d3                                  \n\t"\r
332                                                 "       bne                     reg_test_1_error                \n\t"\r
333                                                 "       cmpi.l          #5, d4                                  \n\t"\r
334                                                 "       bne                     reg_test_1_error                \n\t"\r
335                                                 "       cmpi.l          #6, d5                                  \n\t"\r
336                                                 "       bne                     reg_test_1_error                \n\t"\r
337                                                 "       cmpi.l          #7, d6                                  \n\t"\r
338                                                 "       bne                     reg_test_1_error                \n\t"\r
339                                                 "       cmpi.l          #8, d7                                  \n\t"\r
340                                                 "       bne                     reg_test_1_error                \n\t"\r
341                                                 "       move            a0, d0                                  \n\t"\r
342                                                 "       cmpi.l          #9, d0                                  \n\t"\r
343                                                 "       bne                     reg_test_1_error                \n\t"\r
344                                                 "       move            a1, d0                                  \n\t"\r
345                                                 "       cmpi.l          #10, d0                                 \n\t"\r
346                                                 "       bne                     reg_test_1_error                \n\t"\r
347                                                 "       move            a2, d0                                  \n\t"\r
348                                                 "       cmpi.l          #11, d0                                 \n\t"\r
349                                                 "       bne                     reg_test_1_error                \n\t"\r
350                                                 "       move            a3, d0                                  \n\t"\r
351                                                 "       cmpi.l          #12, d0                                 \n\t"\r
352                                                 "       bne                     reg_test_1_error                \n\t"\r
353                                                 "       move            a4, d0                                  \n\t"\r
354                                                 "       cmpi.l          #13, d0                                 \n\t"\r
355                                                 "       bne                     reg_test_1_error                \n\t"\r
356                                                 "       move            a5, d0                                  \n\t"\r
357                                                 "       cmpi.l          #14, d0                                 \n\t"\r
358                                                 "       bne                     reg_test_1_error                \n\t"\r
359                                                 "       move            a6, d0                                  \n\t"\r
360                                                 "       cmpi.l          #15, d0                                 \n\t"\r
361                                                 "       bne                     reg_test_1_error                \n\t"\r
362                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
363                                                 "       addq            #1, d0                                  \n\t"\r
364                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
365                                                 "       bra                     reg_test_1_start                \n\t"\r
366                                                 "reg_test_1_error:                                              \n\t"\r
367                                                 "       bra                     reg_test_1_error                \n\t"\r
368                                         );\r
369 }\r
370 /*-----------------------------------------------------------*/\r
371 \r
372 static void vRegTest2Task( void *pvParameters )\r
373 {\r
374         /* Sanity check - did we receive the parameter expected? */\r
375         if( pvParameters != &ulRegTest2Counter )\r
376         {\r
377                 /* Change here so the check task can detect that an error occurred. */\r
378                 for( ;; )\r
379                 {\r
380                 }\r
381         }\r
382 \r
383         /* Set all the registers to known values, then check that each retains its\r
384         expected value - as described at the top of this file.  If an error is\r
385         found then the loop counter will no longer be incremented allowing the check\r
386         task to recognise the error. */\r
387         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
388                                                 "       moveq           #10, d0                                 \n\t"\r
389                                                 "       moveq           #20, d1                                 \n\t"\r
390                                                 "       moveq           #30, d2                                 \n\t"\r
391                                                 "       moveq           #40, d3                                 \n\t"\r
392                                                 "       moveq           #50, d4                                 \n\t"\r
393                                                 "       moveq           #60, d5                                 \n\t"\r
394                                                 "       moveq           #70, d6                                 \n\t"\r
395                                                 "       moveq           #80, d7                                 \n\t"\r
396                                                 "       move            #90, a0                                 \n\t"\r
397                                                 "       move            #100, a1                                \n\t"\r
398                                                 "       move            #110, a2                                \n\t"\r
399                                                 "       move            #120, a3                                \n\t"\r
400                                                 "       move            #130, a4                                \n\t"\r
401                                                 "       move            #140, a5                                \n\t"\r
402                                                 "       move            #150, a6                                \n\t"\r
403                                                 "                                                                               \n\t"\r
404                                                 "       cmpi.l          #10, d0                                 \n\t"\r
405                                                 "       bne                     reg_test_2_error                \n\t"\r
406                                                 "       cmpi.l          #20, d1                                 \n\t"\r
407                                                 "       bne                     reg_test_2_error                \n\t"\r
408                                                 "       cmpi.l          #30, d2                                 \n\t"\r
409                                                 "       bne                     reg_test_2_error                \n\t"\r
410                                                 "       cmpi.l          #40, d3                                 \n\t"\r
411                                                 "       bne                     reg_test_2_error                \n\t"\r
412                                                 "       cmpi.l          #50, d4                                 \n\t"\r
413                                                 "       bne                     reg_test_2_error                \n\t"\r
414                                                 "       cmpi.l          #60, d5                                 \n\t"\r
415                                                 "       bne                     reg_test_2_error                \n\t"\r
416                                                 "       cmpi.l          #70, d6                                 \n\t"\r
417                                                 "       bne                     reg_test_2_error                \n\t"\r
418                                                 "       cmpi.l          #80, d7                                 \n\t"\r
419                                                 "       bne                     reg_test_2_error                \n\t"\r
420                                                 "       move            a0, d0                                  \n\t"\r
421                                                 "       cmpi.l          #90, d0                                 \n\t"\r
422                                                 "       bne                     reg_test_2_error                \n\t"\r
423                                                 "       move            a1, d0                                  \n\t"\r
424                                                 "       cmpi.l          #100, d0                                \n\t"\r
425                                                 "       bne                     reg_test_2_error                \n\t"\r
426                                                 "       move            a2, d0                                  \n\t"\r
427                                                 "       cmpi.l          #110, d0                                \n\t"\r
428                                                 "       bne                     reg_test_2_error                \n\t"\r
429                                                 "       move            a3, d0                                  \n\t"\r
430                                                 "       cmpi.l          #120, d0                                \n\t"\r
431                                                 "       bne                     reg_test_2_error                \n\t"\r
432                                                 "       move            a4, d0                                  \n\t"\r
433                                                 "       cmpi.l          #130, d0                                \n\t"\r
434                                                 "       bne                     reg_test_2_error                \n\t"\r
435                                                 "       move            a5, d0                                  \n\t"\r
436                                                 "       cmpi.l          #140, d0                                \n\t"\r
437                                                 "       bne                     reg_test_2_error                \n\t"\r
438                                                 "       move            a6, d0                                  \n\t"\r
439                                                 "       cmpi.l          #150, d0                                \n\t"\r
440                                                 "       bne                     reg_test_2_error                \n\t"\r
441                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
442                                                 "       addq            #1, d0                                  \n\t"\r
443                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
444                                                 "       bra                     reg_test_2_start                \n\t"\r
445                                                 "reg_test_2_error:                                              \n\t"\r
446                                                 "       bra                     reg_test_2_error                \n\t"\r
447                                         );\r
448 }\r
449 /*-----------------------------------------------------------*/\r
450 \r
451 \r
452 \r