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1 /*\r
2         FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.\r
3 \r
4         This file is part of the FreeRTOS distribution.\r
5 \r
6         FreeRTOS is free software; you can redistribute it and/or modify it     under \r
7         the terms of the GNU General Public License (version 2) as published by the \r
8         Free Software Foundation and modified by the FreeRTOS exception.\r
9         **NOTE** The exception to the GPL is included to allow you to distribute a\r
10         combined work that includes FreeRTOS without being obliged to provide the \r
11         source code for proprietary components outside of the FreeRTOS kernel.  \r
12         Alternative commercial license and support terms are also available upon \r
13         request.  See the licensing section of http://www.FreeRTOS.org for full \r
14         license details.\r
15 \r
16         FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
17         ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
18         FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
19         more details.\r
20 \r
21         You should have received a copy of the GNU General Public License along\r
22         with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
23         Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
24 \r
25 \r
26         ***************************************************************************\r
27         *                                                                         *\r
28         * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
29         * See http://www.FreeRTOS.org/Documentation for details                   *\r
30         *                                                                         *\r
31         ***************************************************************************\r
32 \r
33         1 tab == 4 spaces!\r
34 \r
35         Please ensure to read the configuration and relevant port sections of the\r
36         online documentation.\r
37 \r
38         http://www.FreeRTOS.org - Documentation, latest information, license and\r
39         contact details.\r
40 \r
41         http://www.SafeRTOS.com - A version that is certified for use in safety\r
42         critical systems.\r
43 \r
44         http://www.OpenRTOS.com - Commercial support, development, porting,\r
45         licensing and training services.\r
46 */\r
47 \r
48 \r
49 /*\r
50  * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
51  * documentation provides more details of the standard demo application tasks.\r
52  * In addition to the standard demo tasks, the following tasks and tests are\r
53  * defined and/or created within this file:\r
54  *\r
55  * "Web server" - Very basic demonstration of the lwIP stack.  The WEB server\r
56  * simply generates a page that shows the current state of all the tasks within\r
57  * the system, including the high water mark of each task stack. The high water\r
58  * mark is displayed as the amount of stack that has never been used, so the\r
59  * closer the value is to zero the closer the task has come to overflowing its\r
60  * stack.  The IP address and net mask are set within FreeRTOSConfig.h.\r
61  *\r
62  * "Check" task -  This only executes every five seconds but has a high priority\r
63  * to ensure it gets processor time.  Its main function is to check that all the\r
64  * standard demo tasks are still operational.  While no errors have been\r
65  * discovered the check task will toggle an LED every 5 seconds - the toggle\r
66  * rate increasing to 500ms being a visual indication that at least one task has\r
67  * reported unexpected behaviour.\r
68  *\r
69  * "Reg test" tasks - These fill the registers with known values, then check\r
70  * that each register still contains its expected value.  Each task uses\r
71  * different values.  The tasks run with very low priority so get preempted very\r
72  * frequently.  A register containing an unexpected value is indicative of an\r
73  * error in the context switching mechanism.\r
74  *\r
75  */\r
76 \r
77 /* Standard includes. */\r
78 #include <stdio.h>\r
79 \r
80 /* Scheduler includes. */\r
81 #include "FreeRTOS.h"\r
82 #include "task.h"\r
83 #include "queue.h"\r
84 #include "semphr.h"\r
85 \r
86 /* Demo app includes. */\r
87 #include "BlockQ.h"\r
88 #include "death.h"\r
89 #include "flash.h"\r
90 #include "partest.h"\r
91 #include "semtest.h"\r
92 #include "PollQ.h"\r
93 #include "GenQTest.h"\r
94 #include "QPeek.h"\r
95 #include "recmutex.h"\r
96 \r
97 /*-----------------------------------------------------------*/\r
98 \r
99 /* The time between cycles of the 'check' functionality - as described at the\r
100 top of this file. */\r
101 #define mainNO_ERROR_PERIOD                                     ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
102 \r
103 /* The rate at which the LED controlled by the 'check' task will flash should an\r
104 error have been detected. */\r
105 #define mainERROR_PERIOD                                        ( ( portTickType ) 500 / portTICK_RATE_MS )\r
106 \r
107 /* The LED controlled by the 'check' task. */\r
108 #define mainCHECK_LED                                           ( 3 )\r
109 \r
110 /* ComTest constants - there is no free LED for the comtest tasks. */\r
111 #define mainCOM_TEST_BAUD_RATE                          ( ( unsigned portLONG ) 19200 )\r
112 #define mainCOM_TEST_LED                                        ( 5 )\r
113 \r
114 /* Task priorities. */\r
115 #define mainCOM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
116 #define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )\r
117 #define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )\r
118 #define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )\r
119 #define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )\r
120 #define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
121 #define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
122 #define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )\r
123 #define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )\r
124 \r
125 /*\r
126  * Configure the hardware for the demo.\r
127  */\r
128 static void prvSetupHardware( void );\r
129 \r
130 /*\r
131  * Implements the 'check' task functionality as described at the top of this\r
132  * file.\r
133  */\r
134 static void prvCheckTask( void *pvParameters );\r
135 \r
136 /*\r
137  * Implement the 'Reg test' functionality as described at the top of this file.\r
138  */\r
139 static void vRegTest1Task( void *pvParameters );\r
140 static void vRegTest2Task( void *pvParameters );\r
141 \r
142 /*-----------------------------------------------------------*/\r
143 \r
144 /* Counters used to detect errors within the reg test tasks. */\r
145 static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
146 \r
147 /*-----------------------------------------------------------*/\r
148 \r
149 int main( void )\r
150 {\r
151 extern void vBasicWEBServer( void *pv );\r
152 \r
153         /* Setup the hardware ready for this demo. */\r
154         prvSetupHardware();\r
155         ( void )sys_thread_new("HTTPD", vBasicWEBServer, NULL, 320, mainWEB_TASK_PRIORITY );\r
156 \r
157         /* Start the standard demo tasks. */\r
158         vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
159         vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
160         vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
161         vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
162         vStartQueuePeekTasks();\r
163         vStartRecursiveMutexTasks();\r
164         vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
165 \r
166         /* Start the reg test tasks - defined in this file. */\r
167         xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
168         xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
169 \r
170         /* Create the check task. */\r
171         xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
172 \r
173         /* The suicide tasks must be created last as they need to know how many\r
174         tasks were running prior to their creation in order to ascertain whether\r
175         or not the correct/expected number of tasks are running at any given time. */\r
176     vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
177 \r
178         /* Start the scheduler. */\r
179         vTaskStartScheduler();\r
180 \r
181     /* Will only get here if there was insufficient memory to create the idle\r
182     task. */\r
183         for( ;; )\r
184         {\r
185         }\r
186 }\r
187 /*-----------------------------------------------------------*/\r
188 \r
189 static void prvCheckTask( void *pvParameters )\r
190 {\r
191 unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
192 portTickType xLastExecutionTime;\r
193 \r
194         ( void ) pvParameters;\r
195 \r
196         /* Initialise the variable used to control our iteration rate prior to\r
197         its first use. */\r
198         xLastExecutionTime = xTaskGetTickCount();\r
199 \r
200         for( ;; )\r
201         {\r
202                 /* Wait until it is time to run the tests again. */\r
203                 vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
204 \r
205                 /* Has an error been found in any task? */\r
206                 if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
207                 {\r
208                         ulError |= 0x01UL;\r
209                 }\r
210 \r
211                 if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
212                 {\r
213                         ulError |= 0x02UL;\r
214                 }\r
215 \r
216                 if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
217                 {\r
218                         ulError |= 0x04UL;\r
219                 }\r
220 \r
221                 if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
222             {\r
223                 ulError |= 0x20UL;\r
224             }\r
225 \r
226                 if( xArePollingQueuesStillRunning() != pdTRUE )\r
227             {\r
228                 ulError |= 0x40UL;\r
229             }\r
230 \r
231                 if( xIsCreateTaskStillRunning() != pdTRUE )\r
232             {\r
233                 ulError |= 0x80UL;\r
234             }\r
235 \r
236                 if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
237             {\r
238                 ulError |= 0x200UL;\r
239             }\r
240 \r
241                 if( ulLastRegTest1Count == ulRegTest1Counter )\r
242                 {\r
243                         ulError |= 0x1000UL;\r
244                 }\r
245 \r
246                 if( ulLastRegTest2Count == ulRegTest2Counter )\r
247                 {\r
248                         ulError |= 0x1000UL;\r
249                 }\r
250 \r
251                 ulLastRegTest1Count = ulRegTest1Counter;\r
252                 ulLastRegTest2Count = ulRegTest2Counter;\r
253 \r
254                 /* If an error has been found then increase our cycle rate, and in so\r
255                 going increase the rate at which the check task LED toggles. */\r
256                 if( ulError != 0 )\r
257                 {\r
258                 ulTicksToWait = mainERROR_PERIOD;\r
259                 }\r
260 \r
261                 /* Toggle the LED each itteration. */\r
262                 vParTestToggleLED( mainCHECK_LED );\r
263         }\r
264 }\r
265 /*-----------------------------------------------------------*/\r
266 \r
267 void prvSetupHardware( void )\r
268 {\r
269         portDISABLE_INTERRUPTS();\r
270 \r
271         /* Setup the port used to toggle LEDs. */\r
272         vParTestInitialise();\r
273 }\r
274 /*-----------------------------------------------------------*/\r
275 \r
276 void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
277 {\r
278         /* This will get called if a stack overflow is detected during the context\r
279         switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
280         problems within nested interrupts, but only do this for debug purposes as\r
281         it will increase the context switch time. */\r
282 \r
283         ( void ) pxTask;\r
284         ( void ) pcTaskName;\r
285 \r
286         for( ;; )\r
287         {\r
288         }\r
289 }\r
290 /*-----------------------------------------------------------*/\r
291 \r
292 static void vRegTest1Task( void *pvParameters )\r
293 {\r
294         /* Sanity check - did we receive the parameter expected? */\r
295         if( pvParameters != &ulRegTest1Counter )\r
296         {\r
297                 /* Change here so the check task can detect that an error occurred. */\r
298                 for( ;; )\r
299                 {\r
300                 }\r
301         }\r
302 \r
303         /* Set all the registers to known values, then check that each retains its\r
304         expected value - as described at the top of this file.  If an error is\r
305         found then the loop counter will no longer be incremented allowing the check\r
306         task to recognise the error. */\r
307         asm volatile    (       "reg_test_1_start:                                              \n\t"\r
308                                                 "       moveq           #1, d0                                  \n\t"\r
309                                                 "       moveq           #2, d1                                  \n\t"\r
310                                                 "       moveq           #3, d2                                  \n\t"\r
311                                                 "       moveq           #4, d3                                  \n\t"\r
312                                                 "       moveq           #5, d4                                  \n\t"\r
313                                                 "       moveq           #6, d5                                  \n\t"\r
314                                                 "       moveq           #7, d6                                  \n\t"\r
315                                                 "       moveq           #8, d7                                  \n\t"\r
316                                                 "       move            #9, a0                                  \n\t"\r
317                                                 "       move            #10, a1                                 \n\t"\r
318                                                 "       move            #11, a2                                 \n\t"\r
319                                                 "       move            #12, a3                                 \n\t"\r
320                                                 "       move            #13, a4                                 \n\t"\r
321                                                 "       move            #14, a5                                 \n\t"\r
322                                                 "       move            #15, a6                                 \n\t"\r
323                                                 "                                                                               \n\t"\r
324                                                 "       cmpi.l          #1, d0                                  \n\t"\r
325                                                 "       bne                     reg_test_1_error                \n\t"\r
326                                                 "       cmpi.l          #2, d1                                  \n\t"\r
327                                                 "       bne                     reg_test_1_error                \n\t"\r
328                                                 "       cmpi.l          #3, d2                                  \n\t"\r
329                                                 "       bne                     reg_test_1_error                \n\t"\r
330                                                 "       cmpi.l          #4, d3                                  \n\t"\r
331                                                 "       bne                     reg_test_1_error                \n\t"\r
332                                                 "       cmpi.l          #5, d4                                  \n\t"\r
333                                                 "       bne                     reg_test_1_error                \n\t"\r
334                                                 "       cmpi.l          #6, d5                                  \n\t"\r
335                                                 "       bne                     reg_test_1_error                \n\t"\r
336                                                 "       cmpi.l          #7, d6                                  \n\t"\r
337                                                 "       bne                     reg_test_1_error                \n\t"\r
338                                                 "       cmpi.l          #8, d7                                  \n\t"\r
339                                                 "       bne                     reg_test_1_error                \n\t"\r
340                                                 "       move            a0, d0                                  \n\t"\r
341                                                 "       cmpi.l          #9, d0                                  \n\t"\r
342                                                 "       bne                     reg_test_1_error                \n\t"\r
343                                                 "       move            a1, d0                                  \n\t"\r
344                                                 "       cmpi.l          #10, d0                                 \n\t"\r
345                                                 "       bne                     reg_test_1_error                \n\t"\r
346                                                 "       move            a2, d0                                  \n\t"\r
347                                                 "       cmpi.l          #11, d0                                 \n\t"\r
348                                                 "       bne                     reg_test_1_error                \n\t"\r
349                                                 "       move            a3, d0                                  \n\t"\r
350                                                 "       cmpi.l          #12, d0                                 \n\t"\r
351                                                 "       bne                     reg_test_1_error                \n\t"\r
352                                                 "       move            a4, d0                                  \n\t"\r
353                                                 "       cmpi.l          #13, d0                                 \n\t"\r
354                                                 "       bne                     reg_test_1_error                \n\t"\r
355                                                 "       move            a5, d0                                  \n\t"\r
356                                                 "       cmpi.l          #14, d0                                 \n\t"\r
357                                                 "       bne                     reg_test_1_error                \n\t"\r
358                                                 "       move            a6, d0                                  \n\t"\r
359                                                 "       cmpi.l          #15, d0                                 \n\t"\r
360                                                 "       bne                     reg_test_1_error                \n\t"\r
361                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
362                                                 "       addq            #1, d0                                  \n\t"\r
363                                                 "       move            d0, ulRegTest1Counter   \n\t"\r
364                                                 "       bra                     reg_test_1_start                \n\t"\r
365                                                 "reg_test_1_error:                                              \n\t"\r
366                                                 "       bra                     reg_test_1_error                \n\t"\r
367                                         );\r
368 }\r
369 /*-----------------------------------------------------------*/\r
370 \r
371 static void vRegTest2Task( void *pvParameters )\r
372 {\r
373         /* Sanity check - did we receive the parameter expected? */\r
374         if( pvParameters != &ulRegTest2Counter )\r
375         {\r
376                 /* Change here so the check task can detect that an error occurred. */\r
377                 for( ;; )\r
378                 {\r
379                 }\r
380         }\r
381 \r
382         /* Set all the registers to known values, then check that each retains its\r
383         expected value - as described at the top of this file.  If an error is\r
384         found then the loop counter will no longer be incremented allowing the check\r
385         task to recognise the error. */\r
386         asm volatile    (       "reg_test_2_start:                                              \n\t"\r
387                                                 "       moveq           #10, d0                                 \n\t"\r
388                                                 "       moveq           #20, d1                                 \n\t"\r
389                                                 "       moveq           #30, d2                                 \n\t"\r
390                                                 "       moveq           #40, d3                                 \n\t"\r
391                                                 "       moveq           #50, d4                                 \n\t"\r
392                                                 "       moveq           #60, d5                                 \n\t"\r
393                                                 "       moveq           #70, d6                                 \n\t"\r
394                                                 "       moveq           #80, d7                                 \n\t"\r
395                                                 "       move            #90, a0                                 \n\t"\r
396                                                 "       move            #100, a1                                \n\t"\r
397                                                 "       move            #110, a2                                \n\t"\r
398                                                 "       move            #120, a3                                \n\t"\r
399                                                 "       move            #130, a4                                \n\t"\r
400                                                 "       move            #140, a5                                \n\t"\r
401                                                 "       move            #150, a6                                \n\t"\r
402                                                 "                                                                               \n\t"\r
403                                                 "       cmpi.l          #10, d0                                 \n\t"\r
404                                                 "       bne                     reg_test_2_error                \n\t"\r
405                                                 "       cmpi.l          #20, d1                                 \n\t"\r
406                                                 "       bne                     reg_test_2_error                \n\t"\r
407                                                 "       cmpi.l          #30, d2                                 \n\t"\r
408                                                 "       bne                     reg_test_2_error                \n\t"\r
409                                                 "       cmpi.l          #40, d3                                 \n\t"\r
410                                                 "       bne                     reg_test_2_error                \n\t"\r
411                                                 "       cmpi.l          #50, d4                                 \n\t"\r
412                                                 "       bne                     reg_test_2_error                \n\t"\r
413                                                 "       cmpi.l          #60, d5                                 \n\t"\r
414                                                 "       bne                     reg_test_2_error                \n\t"\r
415                                                 "       cmpi.l          #70, d6                                 \n\t"\r
416                                                 "       bne                     reg_test_2_error                \n\t"\r
417                                                 "       cmpi.l          #80, d7                                 \n\t"\r
418                                                 "       bne                     reg_test_2_error                \n\t"\r
419                                                 "       move            a0, d0                                  \n\t"\r
420                                                 "       cmpi.l          #90, d0                                 \n\t"\r
421                                                 "       bne                     reg_test_2_error                \n\t"\r
422                                                 "       move            a1, d0                                  \n\t"\r
423                                                 "       cmpi.l          #100, d0                                \n\t"\r
424                                                 "       bne                     reg_test_2_error                \n\t"\r
425                                                 "       move            a2, d0                                  \n\t"\r
426                                                 "       cmpi.l          #110, d0                                \n\t"\r
427                                                 "       bne                     reg_test_2_error                \n\t"\r
428                                                 "       move            a3, d0                                  \n\t"\r
429                                                 "       cmpi.l          #120, d0                                \n\t"\r
430                                                 "       bne                     reg_test_2_error                \n\t"\r
431                                                 "       move            a4, d0                                  \n\t"\r
432                                                 "       cmpi.l          #130, d0                                \n\t"\r
433                                                 "       bne                     reg_test_2_error                \n\t"\r
434                                                 "       move            a5, d0                                  \n\t"\r
435                                                 "       cmpi.l          #140, d0                                \n\t"\r
436                                                 "       bne                     reg_test_2_error                \n\t"\r
437                                                 "       move            a6, d0                                  \n\t"\r
438                                                 "       cmpi.l          #150, d0                                \n\t"\r
439                                                 "       bne                     reg_test_2_error                \n\t"\r
440                                                 "       move            ulRegTest1Counter, d0   \n\t"\r
441                                                 "       addq            #1, d0                                  \n\t"\r
442                                                 "       move            d0, ulRegTest2Counter   \n\t"\r
443                                                 "       bra                     reg_test_2_start                \n\t"\r
444                                                 "reg_test_2_error:                                              \n\t"\r
445                                                 "       bra                     reg_test_2_error                \n\t"\r
446                                         );\r
447 }\r
448 /*-----------------------------------------------------------*/\r
449 \r
450 \r
451 \r