1 /* Coldfire C Header File
\r
2 * Copyright Freescale Semiconductor Inc
\r
3 * All rights reserved.
\r
5 * 2007/03/19 Revision: 0.9
\r
8 #ifndef __MCF5282_FEC_H__
\r
9 #define __MCF5282_FEC_H__
\r
12 /*********************************************************************
\r
14 * Fast Ethernet Controller(FEC)
\r
16 *********************************************************************/
\r
18 /* Register read/write macros */
\r
19 #define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x1004]))
\r
20 #define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x1008]))
\r
21 #define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x1010]))
\r
22 #define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x1014]))
\r
23 #define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x1024]))
\r
24 #define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x1040]))
\r
25 #define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x1044]))
\r
26 #define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x1064]))
\r
27 #define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x1084]))
\r
28 #define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x10C4]))
\r
29 #define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x10E4]))
\r
30 #define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x10E8]))
\r
31 #define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x10EC]))
\r
32 #define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x1118]))
\r
33 #define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x111C]))
\r
34 #define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x1120]))
\r
35 #define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x1124]))
\r
36 #define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x1144]))
\r
37 #define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x114C]))
\r
38 #define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x1150]))
\r
39 #define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x1180]))
\r
40 #define MCF_FEC_ETSDR (*(vuint32*)(&__IPSBAR[0x1184]))
\r
41 #define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x1188]))
\r
42 #define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x1200]))
\r
43 #define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x1204]))
\r
44 #define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x1208]))
\r
45 #define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x120C]))
\r
46 #define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1210]))
\r
47 #define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1214]))
\r
48 #define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1218]))
\r
49 #define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x121C]))
\r
50 #define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x1220]))
\r
51 #define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x1224]))
\r
52 #define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x1228]))
\r
53 #define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x122C]))
\r
54 #define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x1230]))
\r
55 #define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x1234]))
\r
56 #define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x1238]))
\r
57 #define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x123C]))
\r
58 #define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x1240]))
\r
59 #define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x1244]))
\r
60 #define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x1248]))
\r
61 #define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x124C]))
\r
62 #define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x1250]))
\r
63 #define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x1254]))
\r
64 #define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x1258]))
\r
65 #define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x125C]))
\r
66 #define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x1260]))
\r
67 #define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x1264]))
\r
68 #define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x1268]))
\r
69 #define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x126C]))
\r
70 #define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x1270]))
\r
71 #define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x1274]))
\r
72 #define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x1284]))
\r
73 #define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x1288]))
\r
74 #define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x128C]))
\r
75 #define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1290]))
\r
76 #define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1294]))
\r
77 #define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1298]))
\r
78 #define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x129C]))
\r
79 #define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x12A0]))
\r
80 #define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x12A4]))
\r
81 #define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x12A8]))
\r
82 #define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x12AC]))
\r
83 #define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x12B0]))
\r
84 #define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x12B4]))
\r
85 #define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(&__IPSBAR[0x12B8]))
\r
86 #define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x12BC]))
\r
87 #define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x12C0]))
\r
88 #define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x12C4]))
\r
89 #define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x12C8]))
\r
90 #define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x12CC]))
\r
91 #define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x12D0]))
\r
92 #define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x12D4]))
\r
93 #define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x12D8]))
\r
94 #define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x12DC]))
\r
95 #define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x12E0]))
\r
99 /* Bit definitions and macros for MCF_FEC_EIR */
\r
100 #define MCF_FEC_EIR_UN (0x80000)
\r
101 #define MCF_FEC_EIR_RL (0x100000)
\r
102 #define MCF_FEC_EIR_LC (0x200000)
\r
103 #define MCF_FEC_EIR_EBERR (0x400000)
\r
104 #define MCF_FEC_EIR_MII (0x800000)
\r
105 #define MCF_FEC_EIR_RXB (0x1000000)
\r
106 #define MCF_FEC_EIR_RXF (0x2000000)
\r
107 #define MCF_FEC_EIR_TXB (0x4000000)
\r
108 #define MCF_FEC_EIR_TXF (0x8000000)
\r
109 #define MCF_FEC_EIR_GRA (0x10000000)
\r
110 #define MCF_FEC_EIR_BABT (0x20000000)
\r
111 #define MCF_FEC_EIR_BABR (0x40000000)
\r
112 #define MCF_FEC_EIR_HBERR (0x80000000)
\r
113 #define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
\r
115 /* Bit definitions and macros for MCF_FEC_EIMR */
\r
116 #define MCF_FEC_EIMR_UN (0x80000)
\r
117 #define MCF_FEC_EIMR_RL (0x100000)
\r
118 #define MCF_FEC_EIMR_LC (0x200000)
\r
119 #define MCF_FEC_EIMR_EBERR (0x400000)
\r
120 #define MCF_FEC_EIMR_MII (0x800000)
\r
121 #define MCF_FEC_EIMR_RXB (0x1000000)
\r
122 #define MCF_FEC_EIMR_RXF (0x2000000)
\r
123 #define MCF_FEC_EIMR_TXB (0x4000000)
\r
124 #define MCF_FEC_EIMR_TXF (0x8000000)
\r
125 #define MCF_FEC_EIMR_GRA (0x10000000)
\r
126 #define MCF_FEC_EIMR_BABT (0x20000000)
\r
127 #define MCF_FEC_EIMR_BABR (0x40000000)
\r
128 #define MCF_FEC_EIMR_HBERR (0x80000000)
\r
129 #define MCF_FEC_EIMR_MASK_ALL (0)
\r
130 #define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
\r
132 /* Bit definitions and macros for MCF_FEC_RDAR */
\r
133 #define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)
\r
135 /* Bit definitions and macros for MCF_FEC_TDAR */
\r
136 #define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)
\r
138 /* Bit definitions and macros for MCF_FEC_ECR */
\r
139 #define MCF_FEC_ECR_RESET (0x1)
\r
140 #define MCF_FEC_ECR_ETHER_EN (0x2)
\r
142 /* Bit definitions and macros for MCF_FEC_MMFR */
\r
143 #define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
\r
144 #define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
\r
145 #define MCF_FEC_MMFR_TA_10 (0x20000)
\r
146 #define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
\r
147 #define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
\r
148 #define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
\r
149 #define MCF_FEC_MMFR_OP_READ (0x20000000)
\r
150 #define MCF_FEC_MMFR_OP_WRITE (0x10000000)
\r
151 #define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
\r
152 #define MCF_FEC_MMFR_ST_01 (0x40000000)
\r
154 /* Bit definitions and macros for MCF_FEC_MSCR */
\r
155 #define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
\r
156 #define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
\r
158 /* Bit definitions and macros for MCF_FEC_MIBC */
\r
159 #define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
\r
160 #define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
\r
162 /* Bit definitions and macros for MCF_FEC_RCR */
\r
163 #define MCF_FEC_RCR_LOOP (0x1)
\r
164 #define MCF_FEC_RCR_DRT (0x2)
\r
165 #define MCF_FEC_RCR_MII_MODE (0x4)
\r
166 #define MCF_FEC_RCR_PROM (0x8)
\r
167 #define MCF_FEC_RCR_BC_REJ (0x10)
\r
168 #define MCF_FEC_RCR_FCE (0x20)
\r
169 #define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
\r
171 /* Bit definitions and macros for MCF_FEC_TCR */
\r
172 #define MCF_FEC_TCR_GTS (0x1)
\r
173 #define MCF_FEC_TCR_HBC (0x2)
\r
174 #define MCF_FEC_TCR_FDEN (0x4)
\r
175 #define MCF_FEC_TCR_TFC_PAUSE (0x8)
\r
176 #define MCF_FEC_TCR_RFC_PAUSE (0x10)
\r
178 /* Bit definitions and macros for MCF_FEC_PALR */
\r
179 #define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
\r
181 /* Bit definitions and macros for MCF_FEC_PAUR */
\r
182 #define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)
\r
183 #define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)
\r
185 /* Bit definitions and macros for MCF_FEC_OPD */
\r
186 #define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
\r
187 #define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
\r
189 /* Bit definitions and macros for MCF_FEC_IAUR */
\r
190 #define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
\r
192 /* Bit definitions and macros for MCF_FEC_IALR */
\r
193 #define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
\r
195 /* Bit definitions and macros for MCF_FEC_GAUR */
\r
196 #define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
\r
198 /* Bit definitions and macros for MCF_FEC_GALR */
\r
199 #define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
\r
201 /* Bit definitions and macros for MCF_FEC_TFWR */
\r
202 #define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)
\r
203 #define MCF_FEC_TFWR_X_WMRK_64 (0)
\r
204 #define MCF_FEC_TFWR_X_WMRK_128 (0x2)
\r
205 #define MCF_FEC_TFWR_X_WMRK_192 (0x3)
\r
207 /* Bit definitions and macros for MCF_FEC_FRBR */
\r
208 #define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)
\r
210 /* Bit definitions and macros for MCF_FEC_FRSR */
\r
211 #define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)
\r
213 /* Bit definitions and macros for MCF_FEC_ERDSR */
\r
214 #define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
\r
216 /* Bit definitions and macros for MCF_FEC_ETSDR */
\r
217 #define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
\r
219 /* Bit definitions and macros for MCF_FEC_EMRBR */
\r
220 #define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)
\r
222 /* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
\r
223 #define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
225 /* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
\r
226 #define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
228 /* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
\r
229 #define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
231 /* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
\r
232 #define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
234 /* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
\r
235 #define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
237 /* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
\r
238 #define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
240 /* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
\r
241 #define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
243 /* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
\r
244 #define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
246 /* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
\r
247 #define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
249 /* Bit definitions and macros for MCF_FEC_RMON_T_COL */
\r
250 #define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
252 /* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
\r
253 #define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
255 /* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
\r
256 #define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
258 /* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
\r
259 #define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
261 /* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
\r
262 #define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
264 /* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
\r
265 #define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
267 /* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
\r
268 #define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
270 /* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
\r
271 #define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
273 /* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
\r
274 #define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
276 /* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
\r
277 #define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
279 /* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
\r
280 #define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
282 /* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
\r
283 #define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
285 /* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
\r
286 #define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
288 /* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
\r
289 #define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
291 /* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
\r
292 #define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
294 /* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
\r
295 #define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
297 /* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
\r
298 #define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
300 /* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
\r
301 #define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
303 /* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
\r
304 #define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
306 /* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
\r
307 #define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
309 /* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
\r
310 #define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
312 /* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
\r
313 #define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
315 /* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
\r
316 #define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
318 /* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
\r
319 #define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
321 /* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
\r
322 #define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
324 /* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
\r
325 #define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
327 /* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
\r
328 #define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
330 /* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
\r
331 #define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
333 /* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
\r
334 #define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
336 /* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
\r
337 #define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
339 /* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
\r
340 #define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
342 /* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
\r
343 #define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
345 /* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
\r
346 #define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
348 /* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
\r
349 #define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
351 /* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
\r
352 #define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
354 /* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
\r
355 #define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
357 /* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
\r
358 #define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
360 /* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
\r
361 #define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
363 /* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
\r
364 #define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
366 /* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
\r
367 #define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
369 /* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
\r
370 #define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
372 /* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
\r
373 #define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
375 /* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
\r
376 #define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
378 /* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
\r
379 #define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
381 /* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
\r
382 #define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
\r
385 #endif /* __MCF5282_FEC_H__ */
\r