git.sur5r.net Git - freertos/blob - Demo/Common/drivers/Atmel/at91lib/boards/at91sam9xe-ek/board_memories.c

   1 /* ----------------------------------------------------------------------------\r
   2  *         ATMEL Microcontroller Software Support \r
   3  * ----------------------------------------------------------------------------\r
   4  * Copyright (c) 2008, Atmel Corporation\r
   5  *\r
   6  * All rights reserved.\r
   7  *\r
   8  * Redistribution and use in source and binary forms, with or without\r
   9  * modification, are permitted provided that the following conditions are met:\r
  10  *\r
  11  * - Redistributions of source code must retain the above copyright notice,\r
  12  * this list of conditions and the disclaimer below.\r
  13  *\r
  14  * Atmel's name may not be used to endorse or promote products derived from\r
  15  * this software without specific prior written permission.\r
  16  *\r
  17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
  20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
  23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
  24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
  25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  27  * ----------------------------------------------------------------------------\r
  28  */\r
  29 \r
  30 //------------------------------------------------------------------------------\r
  31 //         Headers\r
  32 //------------------------------------------------------------------------------\r
  33 \r
  34 #include <board.h>\r
  35 #include <pio/pio.h>\r
  36 \r
  37 //------------------------------------------------------------------------------\r
  38 //         Local macros\r
  39 //------------------------------------------------------------------------------\r
  40 \r
  41 /// Reads a register value. Useful to add trace information to read  accesses.\r
  42 #define READ(peripheral, register)          (peripheral->register)\r
  43 /// Writes data in a register. Useful to add trace information to write accesses.\r
  44 #define WRITE(peripheral, register, value)  (peripheral->register = value)\r
  45 \r
  46 //------------------------------------------------------------------------------\r
  47 //         Global functions\r
  48 //------------------------------------------------------------------------------\r
  49 \r
  50 //------------------------------------------------------------------------------\r
  51 /// Changes the mapping of the chip so that the remap area mirrors the\r
  52 /// internal ROM or the EBI CS0 (depending on the BMS input).\r
  53 //------------------------------------------------------------------------------\r
  54 void BOARD_RemapRom(void)\r
  55 {\r
  56     WRITE(AT91C_BASE_MATRIX, MATRIX_MRCR, 0);\r
  57 }\r
  58 \r
  59 //------------------------------------------------------------------------------\r
  60 /// Changes the mapping of the chip so that the remap area mirrors the\r
  61 /// internal RAM.\r
  62 //------------------------------------------------------------------------------\r
  63 void BOARD_RemapRam(void)\r
  64 {\r
  65     WRITE(AT91C_BASE_MATRIX,\r
  66           MATRIX_MRCR,\r
  67           (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));\r
  68 }\r
  69 \r
  70 //------------------------------------------------------------------------------\r
  71 /// Initialize and configure the external SDRAM.\r
  72 //------------------------------------------------------------------------------\r
  73 void BOARD_ConfigureSdram(void)\r
  74 {\r
  75         volatile unsigned int i;\r
  76         static const Pin pinsSdram = PINS_SDRAM;\r
  77         volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;\r
  78         \r
  79         // Enable corresponding PIOs\r
  80     PIO_Configure(&pinsSdram, 1);\r
  81     \r
  82         // Enable EBI chip select for the SDRAM\r
  83         WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);\r
  84         \r
  85 \r
  86         // CFG Control Register\r
  87         WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9\r
  88                                                         | AT91C_SDRAMC_NR_13 \r
  89                                                         | AT91C_SDRAMC_CAS_2 \r
  90                                                         | AT91C_SDRAMC_NB_4_BANKS\r
  91                                                         | AT91C_SDRAMC_DBW_32_BITS\r
  92                                                         | AT91C_SDRAMC_TWR_2\r
  93                                                         | AT91C_SDRAMC_TRC_7\r
  94                                                         | AT91C_SDRAMC_TRP_2\r
  95                                                         | AT91C_SDRAMC_TRCD_2\r
  96                                                         | AT91C_SDRAMC_TRAS_5\r
  97                                                         | AT91C_SDRAMC_TXSR_8);\r
  98 \r
  99         for (i = 0; i < 1000; i++);\r
 100 \r
 101         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP\r
 102         pSdram[0] = 0x00000000;\r
 103 \r
 104         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD);     // Set PRCHG AL\r
 105         pSdram[0] = 0x00000000;                                         // Perform PRCHG\r
 106 \r
 107         for (i = 0; i < 10000; i++);\r
 108 \r
 109         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 1st CBR\r
 110         pSdram[1] = 0x00000001;                                         // Perform CBR\r
 111 \r
 112         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 2 CBR\r
 113         pSdram[2] = 0x00000002;                                         // Perform CBR\r
 114 \r
 115         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 3 CBR\r
 116         pSdram[3] = 0x00000003;                                    // Perform CBR\r
 117 \r
 118         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 4 CBR\r
 119         pSdram[4] = 0x00000004;                                   // Perform CBR\r
 120 \r
 121         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 5 CBR\r
 122         pSdram[5] = 0x00000005;                                   // Perform CBR\r
 123 \r
 124         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 6 CBR\r
 125         pSdram[6] = 0x00000006;                                 // Perform CBR\r
 126 \r
 127         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 7 CBR\r
 128         pSdram[7] = 0x00000007;                                 // Perform CBR\r
 129 \r
 130         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);        // Set 8 CBR\r
 131         pSdram[8] = 0x00000008;                                 // Perform CBR\r
 132 \r
 133         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);         // Set LMR operation\r
 134         pSdram[9] = 0xcafedede;                                 // Perform LMR burst=1, lat=2\r
 135 \r
 136         WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000);         // Set Refresh Timer\r
 137 \r
 138         WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD);      // Set Normal mode\r
 139         pSdram[0] = 0x00000000;                                         // Perform Normal mode\r
 140 }\r
 141 \r
 142 //------------------------------------------------------------------------------\r
 143 /// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings).\r
 144 //------------------------------------------------------------------------------\r
 145 void BOARD_ConfigureSdram48MHz(void)\r
 146 {\r
 147     volatile unsigned int i;\r
 148     static const Pin pinsSdram = PINS_SDRAM;\r
 149     volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;\r
 150     \r
 151     // Enable corresponding PIOs\r
 152     PIO_Configure(&pinsSdram, 1);\r
 153     \r
 154     // Enable EBI chip select for the SDRAM\r
 155     WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, AT91C_MATRIX_CS1A_SDRAMC);\r
 156     \r
 157 \r
 158     // CFG Control Register\r
 159     WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9\r
 160                                         | AT91C_SDRAMC_NR_13 \r
 161                                         | AT91C_SDRAMC_CAS_2 \r
 162                                         | AT91C_SDRAMC_NB_4_BANKS\r
 163                                         | AT91C_SDRAMC_DBW_32_BITS\r
 164                                         | AT91C_SDRAMC_TWR_1\r
 165                                         | AT91C_SDRAMC_TRC_4\r
 166                                         | AT91C_SDRAMC_TRP_1\r
 167                                         | AT91C_SDRAMC_TRCD_1\r
 168                                         | AT91C_SDRAMC_TRAS_2\r
 169                                         | AT91C_SDRAMC_TXSR_3);\r
 170 \r
 171     for (i = 0; i < 1000; i++);\r
 172 \r
 173     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP\r
 174     pSdram[0] = 0x00000000;\r
 175 \r
 176     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL\r
 177     pSdram[0] = 0x00000000;                     // Perform PRCHG\r
 178 \r
 179     for (i = 0; i < 10000; i++);\r
 180 \r
 181     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 1st CBR\r
 182     pSdram[1] = 0x00000001;                     // Perform CBR\r
 183 \r
 184     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 2 CBR\r
 185     pSdram[2] = 0x00000002;                     // Perform CBR\r
 186 \r
 187     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 3 CBR\r
 188     pSdram[3] = 0x00000003;                    // Perform CBR\r
 189 \r
 190     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 4 CBR\r
 191     pSdram[4] = 0x00000004;                   // Perform CBR\r
 192 \r
 193     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 5 CBR\r
 194     pSdram[5] = 0x00000005;                   // Perform CBR\r
 195 \r
 196     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 6 CBR\r
 197     pSdram[6] = 0x00000006;                 // Perform CBR\r
 198 \r
 199     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 7 CBR\r
 200     pSdram[7] = 0x00000007;                 // Perform CBR\r
 201 \r
 202     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD);    // Set 8 CBR\r
 203     pSdram[8] = 0x00000008;                 // Perform CBR\r
 204 \r
 205     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD);     // Set LMR operation\r
 206     pSdram[9] = 0xcafedede;                 // Perform LMR burst=1, lat=2\r
 207 \r
 208     WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000);      // Set Refresh Timer\r
 209 \r
 210     WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD);  // Set Normal mode\r
 211     pSdram[0] = 0x00000000;                     // Perform Normal mode\r
 212 }\r
 213 \r
 214 //------------------------------------------------------------------------------\r
 215 /// Configures the EBI for NandFlash access. Pins must be configured after or\r
 216 /// before calling this function.\r
 217 //------------------------------------------------------------------------------\r
 218 void BOARD_ConfigureNandFlash(unsigned char busWidth)\r
 219 {\r
 220     // Configure EBI\r
 221     AT91C_BASE_MATRIX->MATRIX_EBI |= AT91C_MATRIX_CS3A_SM;\r
 222 \r
 223     // Configure SMC\r
 224     AT91C_BASE_SMC->SMC_SETUP3 = 0x00000000;\r
 225     AT91C_BASE_SMC->SMC_PULSE3 = 0x00030003;\r
 226     AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;\r
 227     AT91C_BASE_SMC->SMC_CTRL3  = 0x00002003;\r
 228 \r
 229     if (busWidth == 8) {\r
 230 \r
 231         AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;\r
 232     }\r
 233     else if (busWidth == 16) {\r
 234  \r
 235         AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;\r
 236     }\r
 237 }\r
 238 \r
 239 //------------------------------------------------------------------------------\r
 240 /// Configures the EBI for NandFlash access at 48MHz. Pins must be configured\r
 241 /// after or before calling this function.\r
 242 //------------------------------------------------------------------------------\r
 243 void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)\r
 244 {\r
 245     // Configure EBI\r
 246     AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM;\r
 247 \r
 248     // Configure SMC\r
 249     AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;\r
 250     AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;\r
 251     AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;\r
 252     AT91C_BASE_SMC->SMC_CTRL3  = (AT91C_SMC_READMODE\r
 253                                  | AT91C_SMC_WRITEMODE\r
 254                                  | AT91C_SMC_NWAITM_NWAIT_DISABLE\r
 255                                  | ((0x1 << 16) & AT91C_SMC_TDF));\r
 256     \r
 257     if (busWidth == 8) {\r
 258 \r
 259         AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;\r
 260     }\r
 261     else if (busWidth == 16) {\r
 262  \r
 263         AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;\r
 264     }\r
 265 }\r
 266 \r
 267 //------------------------------------------------------------------------------\r
 268 /// Configures the EBI for NorFlash access at 48MHz.\r
 269 /// \Param busWidth Bus width \r
 270 //------------------------------------------------------------------------------\r
 271 void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)\r
 272 {\r
 273     // Configure SMC\r
 274     AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;\r
 275     AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;\r
 276     AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;\r
 277     AT91C_BASE_SMC->SMC_CTRL0  = (AT91C_SMC_READMODE\r
 278                                   | AT91C_SMC_WRITEMODE\r
 279                                   | AT91C_SMC_NWAITM_NWAIT_DISABLE\r
 280                                   | ((0x1 << 16) & AT91C_SMC_TDF));\r
 281                            \r
 282     if (busWidth == 8) {\r
 283 \r
 284         AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;\r
 285     }\r
 286     else if (busWidth == 16) {\r
 287  \r
 288         AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;\r
 289     }\r
 290     else if (busWidth == 32) {\r
 291  \r
 292         AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;\r
 293     }\r
 294 }\r
 295 \r
 296 //------------------------------------------------------------------------------\r
 297 /// Set flash wait states in the EFC for 48MHz\r
 298 //------------------------------------------------------------------------------\r
 299 void BOARD_ConfigureFlash48MHz(void)\r
 300 {\r
 301     // Set flash wait states\r
 302     //----------------------\r
 303     AT91C_BASE_EFC->EFC_FMR = 6 << 8;\r
 304 }\r