1 //*****************************************************************************
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3 // hw_usb.h - Macros for use in accessing the USB registers.
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5 // Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. You may not combine
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14 // this software with "viral" open-source software in order to form a larger
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15 // program. Any use in violation of the foregoing restrictions may subject
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16 // the user to criminal sanctions under applicable laws, as well as to civil
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17 // liability for the breach of the terms and conditions of this license.
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19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
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27 //*****************************************************************************
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29 #ifndef __HW_USB_H__
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30 #define __HW_USB_H__
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32 //*****************************************************************************
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34 // The following are defines for the Univeral Serial Bus (USB) Controller
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37 //*****************************************************************************
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38 #define USB_O_FADDR 0x00000000 // USB Device Functional Address
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39 #define USB_O_POWER 0x00000001 // USB Power
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40 #define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
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41 #define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
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42 #define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
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43 #define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
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44 #define USB_O_IS 0x0000000A // USB General Interrupt Status
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45 #define USB_O_IE 0x0000000B // USB Interrupt Enable
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46 #define USB_O_FRAME 0x0000000C // USB Frame Value
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47 #define USB_O_EPIDX 0x0000000E // USB Endpoint Index
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48 #define USB_O_TEST 0x0000000F // USB Test Mode
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49 #define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
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50 #define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
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51 #define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
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52 #define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
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53 #define USB_O_DEVCTL 0x00000060 // USB Device Control
\r
54 #define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
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55 #define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
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56 #define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
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57 #define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
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58 #define USB_O_CONTIM 0x0000007A // USB Connect Timing
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59 #define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing
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60 #define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
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61 // to End of Frame Timing
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62 #define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
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63 // to End of Frame Timing
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64 #define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
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66 #define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
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68 #define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
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69 #define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
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71 #define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
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73 #define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
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74 #define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
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76 #define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
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78 #define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
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79 #define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
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81 #define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
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83 #define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
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84 #define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
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86 #define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
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88 #define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
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89 #define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
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91 #define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
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93 #define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
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94 #define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
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96 #define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
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98 #define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
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99 #define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
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101 #define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
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103 #define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
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105 #define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
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106 #define USB_O_NAKLMT 0x0000010B // USB NAK Limit
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107 #define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
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109 #define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
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111 #define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
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113 #define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
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115 #define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
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117 #define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
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119 #define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
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121 #define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
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123 #define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
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125 #define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
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127 #define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
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128 // Interval Endpoint 1
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129 #define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
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131 #define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
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133 #define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
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135 #define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
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137 #define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
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139 #define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
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141 #define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
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143 #define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
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145 #define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
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147 #define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
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149 #define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
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150 // Interval Endpoint 2
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151 #define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
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153 #define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
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155 #define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
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157 #define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
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159 #define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
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161 #define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
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163 #define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
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165 #define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
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167 #define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
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169 #define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
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171 #define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
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172 // Interval Endpoint 3
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173 #define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
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174 // Block Transfer Endpoint 1
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175 #define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
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176 // Block Transfer Endpoint 2
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177 #define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
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178 // Block Transfer Endpoint 3
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179 #define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
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181 #define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
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183 #define USB_O_EPC 0x00000400 // USB External Power Control
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184 #define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
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185 // Interrupt Status
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186 #define USB_O_EPCIM 0x00000408 // USB External Power Control
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188 #define USB_O_EPCISC 0x0000040C // USB External Power Control
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189 // Interrupt Status and Clear
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190 #define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt
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192 #define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask
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193 #define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt
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194 // Status and Clear
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195 #define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
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198 //*****************************************************************************
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200 // The following are defines for the bit fields in the USB_O_FADDR register.
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202 //*****************************************************************************
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203 #define USB_FADDR_M 0x0000007F // Function Address.
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204 #define USB_FADDR_S 0
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206 //*****************************************************************************
\r
208 // The following are defines for the bit fields in the USB_O_POWER register.
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210 //*****************************************************************************
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211 #define USB_POWER_ISOUP 0x00000080 // ISO Update.
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212 #define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect.
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213 #define USB_POWER_RESET 0x00000008 // Reset.
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214 #define USB_POWER_RESUME 0x00000004 // Resume Signaling.
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215 #define USB_POWER_SUSPEND 0x00000002 // Suspend Mode.
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216 #define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY.
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218 //*****************************************************************************
\r
220 // The following are defines for the bit fields in the USB_O_TXIS register.
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222 //*****************************************************************************
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223 #define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt.
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224 #define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt.
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225 #define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt.
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226 #define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt.
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228 //*****************************************************************************
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230 // The following are defines for the bit fields in the USB_O_RXIS register.
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232 //*****************************************************************************
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233 #define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt.
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234 #define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt.
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235 #define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt.
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237 //*****************************************************************************
\r
239 // The following are defines for the bit fields in the USB_O_TXIE register.
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241 //*****************************************************************************
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242 #define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable.
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243 #define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable.
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244 #define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable.
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245 #define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
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248 //*****************************************************************************
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250 // The following are defines for the bit fields in the USB_O_RXIE register.
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252 //*****************************************************************************
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253 #define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable.
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254 #define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable.
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255 #define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable.
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257 //*****************************************************************************
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259 // The following are defines for the bit fields in the USB_O_IS register.
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261 //*****************************************************************************
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262 #define USB_IS_VBUSERR 0x00000080 // VBus Error.
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263 #define USB_IS_SESREQ 0x00000040 // Session Request.
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264 #define USB_IS_DISCON 0x00000020 // Session Disconnect.
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265 #define USB_IS_CONN 0x00000010 // Session Connect.
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266 #define USB_IS_SOF 0x00000008 // Start of Frame.
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267 #define USB_IS_BABBLE 0x00000004 // Babble Detected.
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268 #define USB_IS_RESET 0x00000004 // Reset Signal Detected.
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269 #define USB_IS_RESUME 0x00000002 // Resume Signal Detected.
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270 #define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected.
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272 //*****************************************************************************
\r
274 // The following are defines for the bit fields in the USB_O_IE register.
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276 //*****************************************************************************
\r
277 #define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt.
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278 #define USB_IE_SESREQ 0x00000040 // Enable Session Request
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280 #define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt.
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281 #define USB_IE_CONN 0x00000010 // Enable Connect Interrupt.
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282 #define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt.
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283 #define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt.
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284 #define USB_IE_RESET 0x00000004 // Enable Reset Interrupt.
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285 #define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt.
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286 #define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt.
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288 //*****************************************************************************
\r
290 // The following are defines for the bit fields in the USB_O_FRAME register.
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292 //*****************************************************************************
\r
293 #define USB_FRAME_M 0x000007FF // Frame Number.
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294 #define USB_FRAME_S 0
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296 //*****************************************************************************
\r
298 // The following are defines for the bit fields in the USB_O_EPIDX register.
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300 //*****************************************************************************
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301 #define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index.
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302 #define USB_EPIDX_EPIDX_S 0
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304 //*****************************************************************************
\r
306 // The following are defines for the bit fields in the USB_O_TEST register.
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308 //*****************************************************************************
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309 #define USB_TEST_FORCEH 0x00000080 // Force Host Mode.
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310 #define USB_TEST_FIFOACC 0x00000040 // FIFO Access.
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311 #define USB_TEST_FORCEFS 0x00000020 // Force Full Speed.
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313 //*****************************************************************************
\r
315 // The following are defines for the bit fields in the USB_O_FIFO0 register.
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317 //*****************************************************************************
\r
318 #define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data.
\r
319 #define USB_FIFO0_EPDATA_S 0
\r
321 //*****************************************************************************
\r
323 // The following are defines for the bit fields in the USB_O_FIFO1 register.
\r
325 //*****************************************************************************
\r
326 #define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data.
\r
327 #define USB_FIFO1_EPDATA_S 0
\r
329 //*****************************************************************************
\r
331 // The following are defines for the bit fields in the USB_O_FIFO2 register.
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333 //*****************************************************************************
\r
334 #define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data.
\r
335 #define USB_FIFO2_EPDATA_S 0
\r
337 //*****************************************************************************
\r
339 // The following are defines for the bit fields in the USB_O_FIFO3 register.
\r
341 //*****************************************************************************
\r
342 #define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data.
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343 #define USB_FIFO3_EPDATA_S 0
\r
345 //*****************************************************************************
\r
347 // The following are defines for the bit fields in the USB_O_DEVCTL register.
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349 //*****************************************************************************
\r
350 #define USB_DEVCTL_DEV 0x00000080 // Device Mode.
\r
351 #define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected.
\r
352 #define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected.
\r
353 #define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level.
\r
354 #define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
\r
355 #define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
\r
356 #define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid
\r
357 #define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid
\r
358 #define USB_DEVCTL_HOST 0x00000004 // Host Mode.
\r
359 #define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request.
\r
360 #define USB_DEVCTL_SESSION 0x00000001 // Session Start/End.
\r
362 //*****************************************************************************
\r
364 // The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
\r
366 //*****************************************************************************
\r
367 #define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
\r
368 #define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
\r
369 #define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
\r
370 #define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
\r
371 #define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
\r
372 #define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
\r
373 #define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
\r
374 #define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
\r
375 #define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
\r
376 #define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
\r
377 #define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
\r
379 //*****************************************************************************
\r
381 // The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
\r
383 //*****************************************************************************
\r
384 #define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.
\r
385 #define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.
\r
386 #define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
\r
387 #define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
\r
388 #define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
\r
389 #define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
\r
390 #define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
\r
391 #define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
\r
392 #define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
\r
393 #define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
\r
394 #define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
\r
396 //*****************************************************************************
\r
398 // The following are defines for the bit fields in the USB_O_TXFIFOADD
\r
401 //*****************************************************************************
\r
402 #define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
\r
403 #define USB_TXFIFOADD_ADDR_0 0x00000000 // 0
\r
404 #define USB_TXFIFOADD_ADDR_8 0x00000001 // 8
\r
405 #define USB_TXFIFOADD_ADDR_16 0x00000002 // 16
\r
406 #define USB_TXFIFOADD_ADDR_32 0x00000003 // 32
\r
407 #define USB_TXFIFOADD_ADDR_64 0x00000004 // 64
\r
408 #define USB_TXFIFOADD_ADDR_128 0x00000005 // 128
\r
409 #define USB_TXFIFOADD_ADDR_256 0x00000006 // 256
\r
410 #define USB_TXFIFOADD_ADDR_512 0x00000007 // 512
\r
411 #define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024
\r
412 #define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048
\r
414 //*****************************************************************************
\r
416 // The following are defines for the bit fields in the USB_O_RXFIFOADD
\r
419 //*****************************************************************************
\r
420 #define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.
\r
421 #define USB_RXFIFOADD_ADDR_0 0x00000000 // 0
\r
422 #define USB_RXFIFOADD_ADDR_8 0x00000001 // 8
\r
423 #define USB_RXFIFOADD_ADDR_16 0x00000002 // 16
\r
424 #define USB_RXFIFOADD_ADDR_32 0x00000003 // 32
\r
425 #define USB_RXFIFOADD_ADDR_64 0x00000004 // 64
\r
426 #define USB_RXFIFOADD_ADDR_128 0x00000005 // 128
\r
427 #define USB_RXFIFOADD_ADDR_256 0x00000006 // 256
\r
428 #define USB_RXFIFOADD_ADDR_512 0x00000007 // 512
\r
429 #define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024
\r
430 #define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048
\r
432 //*****************************************************************************
\r
434 // The following are defines for the bit fields in the USB_O_CONTIM register.
\r
436 //*****************************************************************************
\r
437 #define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait.
\r
438 #define USB_CONTIM_WTID_M 0x0000000F // Wait ID.
\r
439 #define USB_CONTIM_WTCON_S 4
\r
440 #define USB_CONTIM_WTID_S 0
\r
442 //*****************************************************************************
\r
444 // The following are defines for the bit fields in the USB_O_FSEOF register.
\r
446 //*****************************************************************************
\r
447 #define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap.
\r
448 #define USB_FSEOF_FSEOFG_S 0
\r
450 //*****************************************************************************
\r
452 // The following are defines for the bit fields in the USB_O_LSEOF register.
\r
454 //*****************************************************************************
\r
455 #define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap.
\r
456 #define USB_LSEOF_LSEOFG_S 0
\r
458 //*****************************************************************************
\r
460 // The following are defines for the bit fields in the USB_O_TXFUNCADDR0
\r
463 //*****************************************************************************
\r
464 #define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address.
\r
465 #define USB_TXFUNCADDR0_ADDR_S 0
\r
467 //*****************************************************************************
\r
469 // The following are defines for the bit fields in the USB_O_TXHUBADDR0
\r
472 //*****************************************************************************
\r
473 #define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators.
\r
474 #define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address.
\r
475 #define USB_TXHUBADDR0_ADDR_S 0
\r
477 //*****************************************************************************
\r
479 // The following are defines for the bit fields in the USB_O_TXHUBPORT0
\r
482 //*****************************************************************************
\r
483 #define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port.
\r
484 #define USB_TXHUBPORT0_PORT_S 0
\r
486 //*****************************************************************************
\r
488 // The following are defines for the bit fields in the USB_O_TXFUNCADDR1
\r
491 //*****************************************************************************
\r
492 #define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
\r
493 #define USB_TXFUNCADDR1_ADDR_S 0
\r
495 //*****************************************************************************
\r
497 // The following are defines for the bit fields in the USB_O_TXHUBADDR1
\r
500 //*****************************************************************************
\r
501 #define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
\r
502 #define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
\r
503 #define USB_TXHUBADDR1_ADDR_S 0
\r
505 //*****************************************************************************
\r
507 // The following are defines for the bit fields in the USB_O_TXHUBPORT1
\r
510 //*****************************************************************************
\r
511 #define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port.
\r
512 #define USB_TXHUBPORT1_PORT_S 0
\r
514 //*****************************************************************************
\r
516 // The following are defines for the bit fields in the USB_O_RXFUNCADDR1
\r
519 //*****************************************************************************
\r
520 #define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address.
\r
521 #define USB_RXFUNCADDR1_ADDR_S 0
\r
523 //*****************************************************************************
\r
525 // The following are defines for the bit fields in the USB_O_RXHUBADDR1
\r
528 //*****************************************************************************
\r
529 #define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.
\r
530 #define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address.
\r
531 #define USB_RXHUBADDR1_ADDR_S 0
\r
533 //*****************************************************************************
\r
535 // The following are defines for the bit fields in the USB_O_RXHUBPORT1
\r
538 //*****************************************************************************
\r
539 #define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port.
\r
540 #define USB_RXHUBPORT1_PORT_S 0
\r
542 //*****************************************************************************
\r
544 // The following are defines for the bit fields in the USB_O_TXFUNCADDR2
\r
547 //*****************************************************************************
\r
548 #define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
\r
549 #define USB_TXFUNCADDR2_ADDR_S 0
\r
551 //*****************************************************************************
\r
553 // The following are defines for the bit fields in the USB_O_TXHUBADDR2
\r
556 //*****************************************************************************
\r
557 #define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
\r
558 #define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
\r
559 #define USB_TXHUBADDR2_ADDR_S 0
\r
561 //*****************************************************************************
\r
563 // The following are defines for the bit fields in the USB_O_TXHUBPORT2
\r
566 //*****************************************************************************
\r
567 #define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port.
\r
568 #define USB_TXHUBPORT2_PORT_S 0
\r
570 //*****************************************************************************
\r
572 // The following are defines for the bit fields in the USB_O_RXFUNCADDR2
\r
575 //*****************************************************************************
\r
576 #define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address.
\r
577 #define USB_RXFUNCADDR2_ADDR_S 0
\r
579 //*****************************************************************************
\r
581 // The following are defines for the bit fields in the USB_O_RXHUBADDR2
\r
584 //*****************************************************************************
\r
585 #define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.
\r
586 #define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address.
\r
587 #define USB_RXHUBADDR2_ADDR_S 0
\r
589 //*****************************************************************************
\r
591 // The following are defines for the bit fields in the USB_O_RXHUBPORT2
\r
594 //*****************************************************************************
\r
595 #define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port.
\r
596 #define USB_RXHUBPORT2_PORT_S 0
\r
598 //*****************************************************************************
\r
600 // The following are defines for the bit fields in the USB_O_TXFUNCADDR3
\r
603 //*****************************************************************************
\r
604 #define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
\r
605 #define USB_TXFUNCADDR3_ADDR_S 0
\r
607 //*****************************************************************************
\r
609 // The following are defines for the bit fields in the USB_O_TXHUBADDR3
\r
612 //*****************************************************************************
\r
613 #define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
\r
614 #define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
\r
615 #define USB_TXHUBADDR3_ADDR_S 0
\r
617 //*****************************************************************************
\r
619 // The following are defines for the bit fields in the USB_O_TXHUBPORT3
\r
622 //*****************************************************************************
\r
623 #define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port.
\r
624 #define USB_TXHUBPORT3_PORT_S 0
\r
626 //*****************************************************************************
\r
628 // The following are defines for the bit fields in the USB_O_RXFUNCADDR3
\r
631 //*****************************************************************************
\r
632 #define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address.
\r
633 #define USB_RXFUNCADDR3_ADDR_S 0
\r
635 //*****************************************************************************
\r
637 // The following are defines for the bit fields in the USB_O_RXHUBADDR3
\r
640 //*****************************************************************************
\r
641 #define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.
\r
642 #define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address.
\r
643 #define USB_RXHUBADDR3_ADDR_S 0
\r
645 //*****************************************************************************
\r
647 // The following are defines for the bit fields in the USB_O_RXHUBPORT3
\r
650 //*****************************************************************************
\r
651 #define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port.
\r
652 #define USB_RXHUBPORT3_PORT_S 0
\r
654 //*****************************************************************************
\r
656 // The following are defines for the bit fields in the USB_O_CSRL0 register.
\r
658 //*****************************************************************************
\r
659 #define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout.
\r
660 #define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear.
\r
661 #define USB_CSRL0_STATUS 0x00000040 // Status Packet.
\r
662 #define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear.
\r
663 #define USB_CSRL0_REQPKT 0x00000020 // Request Packet.
\r
664 #define USB_CSRL0_STALL 0x00000020 // Send Stall.
\r
665 #define USB_CSRL0_SETEND 0x00000010 // Setup End.
\r
666 #define USB_CSRL0_ERROR 0x00000010 // Error.
\r
667 #define USB_CSRL0_DATAEND 0x00000008 // Data End.
\r
668 #define USB_CSRL0_SETUP 0x00000008 // Setup Packet.
\r
669 #define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled.
\r
670 #define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready.
\r
671 #define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready.
\r
673 //*****************************************************************************
\r
675 // The following are defines for the bit fields in the USB_O_CSRH0 register.
\r
677 //*****************************************************************************
\r
678 #define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable.
\r
679 #define USB_CSRH0_DT 0x00000002 // Data Toggle.
\r
680 #define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO.
\r
682 //*****************************************************************************
\r
684 // The following are defines for the bit fields in the USB_O_COUNT0 register.
\r
686 //*****************************************************************************
\r
687 #define USB_COUNT0_COUNT_M 0x0000007F // Count.
\r
688 #define USB_COUNT0_COUNT_S 0
\r
690 //*****************************************************************************
\r
692 // The following are defines for the bit fields in the USB_O_TYPE0 register.
\r
694 //*****************************************************************************
\r
695 #define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed.
\r
696 #define USB_TYPE0_SPEED_FULL 0x00000080 // Full
\r
697 #define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
\r
699 //*****************************************************************************
\r
701 // The following are defines for the bit fields in the USB_O_NAKLMT register.
\r
703 //*****************************************************************************
\r
704 #define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit.
\r
705 #define USB_NAKLMT_NAKLMT_S 0
\r
707 //*****************************************************************************
\r
709 // The following are defines for the bit fields in the USB_O_TXMAXP1 register.
\r
711 //*****************************************************************************
\r
712 #define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier.
\r
713 #define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
\r
714 #define USB_TXMAXP1_MULT_S 11
\r
715 #define USB_TXMAXP1_MAXLOAD_S 0
\r
717 //*****************************************************************************
\r
719 // The following are defines for the bit fields in the USB_O_TXCSRL1 register.
\r
721 //*****************************************************************************
\r
722 #define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
\r
723 #define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit.
\r
724 #define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle.
\r
725 #define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled.
\r
726 #define USB_TXCSRL1_STALL 0x00000010 // Send Stall.
\r
727 #define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet.
\r
728 #define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO.
\r
729 #define USB_TXCSRL1_ERROR 0x00000004 // Error.
\r
730 #define USB_TXCSRL1_UNDRN 0x00000004 // Underrun.
\r
731 #define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty.
\r
732 #define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready.
\r
734 //*****************************************************************************
\r
736 // The following are defines for the bit fields in the USB_O_TXCSRH1 register.
\r
738 //*****************************************************************************
\r
739 #define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set.
\r
740 #define USB_TXCSRH1_ISO 0x00000040 // ISO.
\r
741 #define USB_TXCSRH1_MODE 0x00000020 // Mode.
\r
742 #define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable.
\r
743 #define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle.
\r
744 #define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode.
\r
745 #define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable.
\r
746 #define USB_TXCSRH1_DT 0x00000001 // Data Toggle.
\r
748 //*****************************************************************************
\r
750 // The following are defines for the bit fields in the USB_O_RXMAXP1 register.
\r
752 //*****************************************************************************
\r
753 #define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier.
\r
754 #define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.
\r
755 #define USB_RXMAXP1_MULT_S 11
\r
756 #define USB_RXMAXP1_MAXLOAD_S 0
\r
758 //*****************************************************************************
\r
760 // The following are defines for the bit fields in the USB_O_RXCSRL1 register.
\r
762 //*****************************************************************************
\r
763 #define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle.
\r
764 #define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled.
\r
765 #define USB_RXCSRL1_STALL 0x00000020 // Send Stall.
\r
766 #define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet.
\r
767 #define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO.
\r
768 #define USB_RXCSRL1_DATAERR 0x00000008 // Data Error.
\r
769 #define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout.
\r
770 #define USB_RXCSRL1_OVER 0x00000004 // Overrun.
\r
771 #define USB_RXCSRL1_ERROR 0x00000004 // Error.
\r
772 #define USB_RXCSRL1_FULL 0x00000002 // FIFO Full.
\r
773 #define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready.
\r
775 //*****************************************************************************
\r
777 // The following are defines for the bit fields in the USB_O_RXCSRH1 register.
\r
779 //*****************************************************************************
\r
780 #define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear.
\r
781 #define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request.
\r
782 #define USB_RXCSRH1_ISO 0x00000040 // ISO.
\r
783 #define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable.
\r
784 #define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
\r
785 #define USB_RXCSRH1_PIDERR 0x00000010 // PID Error.
\r
786 #define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode.
\r
787 #define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable.
\r
788 #define USB_RXCSRH1_DT 0x00000002 // Data Toggle.
\r
789 #define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive.
\r
791 //*****************************************************************************
\r
793 // The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
\r
795 //*****************************************************************************
\r
796 #define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count.
\r
797 #define USB_RXCOUNT1_COUNT_S 0
\r
799 //*****************************************************************************
\r
801 // The following are defines for the bit fields in the USB_O_TXTYPE1 register.
\r
803 //*****************************************************************************
\r
804 #define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
\r
805 #define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
\r
806 #define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
\r
807 #define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
\r
808 #define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol.
\r
809 #define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
\r
810 #define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
\r
811 #define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
\r
812 #define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
\r
813 #define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
\r
814 #define USB_TXTYPE1_TEP_S 0
\r
816 //*****************************************************************************
\r
818 // The following are defines for the bit fields in the USB_O_TXINTERVAL1
\r
821 //*****************************************************************************
\r
822 #define USB_TXINTERVAL1_NAKLMT_M \
\r
823 0x000000FF // NAK Limit.
\r
824 #define USB_TXINTERVAL1_TXPOLL_M \
\r
825 0x000000FF // TX Polling
\r
826 #define USB_TXINTERVAL1_TXPOLL_S \
\r
828 #define USB_TXINTERVAL1_NAKLMT_S \
\r
831 //*****************************************************************************
\r
833 // The following are defines for the bit fields in the USB_O_RXTYPE1 register.
\r
835 //*****************************************************************************
\r
836 #define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed.
\r
837 #define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
\r
838 #define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
\r
839 #define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
\r
840 #define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol.
\r
841 #define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
\r
842 #define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
\r
843 #define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
\r
844 #define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
\r
845 #define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.
\r
846 #define USB_RXTYPE1_TEP_S 0
\r
848 //*****************************************************************************
\r
850 // The following are defines for the bit fields in the USB_O_RXINTERVAL1
\r
853 //*****************************************************************************
\r
854 #define USB_RXINTERVAL1_TXPOLL_M \
\r
855 0x000000FF // RX Polling
\r
856 #define USB_RXINTERVAL1_NAKLMT_M \
\r
857 0x000000FF // NAK Limit.
\r
858 #define USB_RXINTERVAL1_TXPOLL_S \
\r
860 #define USB_RXINTERVAL1_NAKLMT_S \
\r
863 //*****************************************************************************
\r
865 // The following are defines for the bit fields in the USB_O_TXMAXP2 register.
\r
867 //*****************************************************************************
\r
868 #define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier.
\r
869 #define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
\r
870 #define USB_TXMAXP2_MULT_S 11
\r
871 #define USB_TXMAXP2_MAXLOAD_S 0
\r
873 //*****************************************************************************
\r
875 // The following are defines for the bit fields in the USB_O_TXCSRL2 register.
\r
877 //*****************************************************************************
\r
878 #define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit.
\r
879 #define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
\r
880 #define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle.
\r
881 #define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled.
\r
882 #define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet.
\r
883 #define USB_TXCSRL2_STALL 0x00000010 // Send Stall.
\r
884 #define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO.
\r
885 #define USB_TXCSRL2_ERROR 0x00000004 // Error.
\r
886 #define USB_TXCSRL2_UNDRN 0x00000004 // Underrun.
\r
887 #define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty.
\r
888 #define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready.
\r
890 //*****************************************************************************
\r
892 // The following are defines for the bit fields in the USB_O_TXCSRH2 register.
\r
894 //*****************************************************************************
\r
895 #define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set.
\r
896 #define USB_TXCSRH2_ISO 0x00000040 // ISO.
\r
897 #define USB_TXCSRH2_MODE 0x00000020 // Mode.
\r
898 #define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable.
\r
899 #define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle.
\r
900 #define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode.
\r
901 #define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable.
\r
902 #define USB_TXCSRH2_DT 0x00000001 // Data Toggle.
\r
904 //*****************************************************************************
\r
906 // The following are defines for the bit fields in the USB_O_RXMAXP2 register.
\r
908 //*****************************************************************************
\r
909 #define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier.
\r
910 #define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.
\r
911 #define USB_RXMAXP2_MULT_S 11
\r
912 #define USB_RXMAXP2_MAXLOAD_S 0
\r
914 //*****************************************************************************
\r
916 // The following are defines for the bit fields in the USB_O_RXCSRL2 register.
\r
918 //*****************************************************************************
\r
919 #define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle.
\r
920 #define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled.
\r
921 #define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet.
\r
922 #define USB_RXCSRL2_STALL 0x00000020 // Send Stall.
\r
923 #define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO.
\r
924 #define USB_RXCSRL2_DATAERR 0x00000008 // Data Error.
\r
925 #define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout.
\r
926 #define USB_RXCSRL2_ERROR 0x00000004 // Error.
\r
927 #define USB_RXCSRL2_OVER 0x00000004 // Overrun.
\r
928 #define USB_RXCSRL2_FULL 0x00000002 // FIFO Full.
\r
929 #define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready.
\r
931 //*****************************************************************************
\r
933 // The following are defines for the bit fields in the USB_O_RXCSRH2 register.
\r
935 //*****************************************************************************
\r
936 #define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear.
\r
937 #define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request.
\r
938 #define USB_RXCSRH2_ISO 0x00000040 // ISO.
\r
939 #define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable.
\r
940 #define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
\r
941 #define USB_RXCSRH2_PIDERR 0x00000010 // PID Error.
\r
942 #define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode.
\r
943 #define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable.
\r
944 #define USB_RXCSRH2_DT 0x00000002 // Data Toggle.
\r
945 #define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive.
\r
947 //*****************************************************************************
\r
949 // The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
\r
951 //*****************************************************************************
\r
952 #define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count.
\r
953 #define USB_RXCOUNT2_COUNT_S 0
\r
955 //*****************************************************************************
\r
957 // The following are defines for the bit fields in the USB_O_TXTYPE2 register.
\r
959 //*****************************************************************************
\r
960 #define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
\r
961 #define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
\r
962 #define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
\r
963 #define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
\r
964 #define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol.
\r
965 #define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
\r
966 #define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
\r
967 #define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
\r
968 #define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
\r
969 #define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
\r
970 #define USB_TXTYPE2_TEP_S 0
\r
972 //*****************************************************************************
\r
974 // The following are defines for the bit fields in the USB_O_TXINTERVAL2
\r
977 //*****************************************************************************
\r
978 #define USB_TXINTERVAL2_TXPOLL_M \
\r
979 0x000000FF // TX Polling
\r
980 #define USB_TXINTERVAL2_NAKLMT_M \
\r
981 0x000000FF // NAK Limit.
\r
982 #define USB_TXINTERVAL2_NAKLMT_S \
\r
984 #define USB_TXINTERVAL2_TXPOLL_S \
\r
987 //*****************************************************************************
\r
989 // The following are defines for the bit fields in the USB_O_RXTYPE2 register.
\r
991 //*****************************************************************************
\r
992 #define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed.
\r
993 #define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
\r
994 #define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
\r
995 #define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
\r
996 #define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol.
\r
997 #define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
\r
998 #define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
\r
999 #define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
\r
1000 #define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
\r
1001 #define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.
\r
1002 #define USB_RXTYPE2_TEP_S 0
\r
1004 //*****************************************************************************
\r
1006 // The following are defines for the bit fields in the USB_O_RXINTERVAL2
\r
1009 //*****************************************************************************
\r
1010 #define USB_RXINTERVAL2_TXPOLL_M \
\r
1011 0x000000FF // RX Polling
\r
1012 #define USB_RXINTERVAL2_NAKLMT_M \
\r
1013 0x000000FF // NAK Limit.
\r
1014 #define USB_RXINTERVAL2_TXPOLL_S \
\r
1016 #define USB_RXINTERVAL2_NAKLMT_S \
\r
1019 //*****************************************************************************
\r
1021 // The following are defines for the bit fields in the USB_O_TXMAXP3 register.
\r
1023 //*****************************************************************************
\r
1024 #define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier.
\r
1025 #define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
\r
1026 #define USB_TXMAXP3_MULT_S 11
\r
1027 #define USB_TXMAXP3_MAXLOAD_S 0
\r
1029 //*****************************************************************************
\r
1031 // The following are defines for the bit fields in the USB_O_TXCSRL3 register.
\r
1033 //*****************************************************************************
\r
1034 #define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit.
\r
1035 #define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
\r
1036 #define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle.
\r
1037 #define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled.
\r
1038 #define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet.
\r
1039 #define USB_TXCSRL3_STALL 0x00000010 // Send Stall.
\r
1040 #define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO.
\r
1041 #define USB_TXCSRL3_ERROR 0x00000004 // Error.
\r
1042 #define USB_TXCSRL3_UNDRN 0x00000004 // Underrun.
\r
1043 #define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty.
\r
1044 #define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready.
\r
1046 //*****************************************************************************
\r
1048 // The following are defines for the bit fields in the USB_O_TXCSRH3 register.
\r
1050 //*****************************************************************************
\r
1051 #define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set.
\r
1052 #define USB_TXCSRH3_ISO 0x00000040 // ISO.
\r
1053 #define USB_TXCSRH3_MODE 0x00000020 // Mode.
\r
1054 #define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable.
\r
1055 #define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle.
\r
1056 #define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode.
\r
1057 #define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable.
\r
1058 #define USB_TXCSRH3_DT 0x00000001 // Data Toggle.
\r
1060 //*****************************************************************************
\r
1062 // The following are defines for the bit fields in the USB_O_RXMAXP3 register.
\r
1064 //*****************************************************************************
\r
1065 #define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier.
\r
1066 #define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.
\r
1067 #define USB_RXMAXP3_MULT_S 11
\r
1068 #define USB_RXMAXP3_MAXLOAD_S 0
\r
1070 //*****************************************************************************
\r
1072 // The following are defines for the bit fields in the USB_O_RXCSRL3 register.
\r
1074 //*****************************************************************************
\r
1075 #define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle.
\r
1076 #define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled.
\r
1077 #define USB_RXCSRL3_STALL 0x00000020 // Send Stall.
\r
1078 #define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet.
\r
1079 #define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO.
\r
1080 #define USB_RXCSRL3_DATAERR 0x00000008 // Data Error.
\r
1081 #define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout.
\r
1082 #define USB_RXCSRL3_ERROR 0x00000004 // Error.
\r
1083 #define USB_RXCSRL3_OVER 0x00000004 // Overrun.
\r
1084 #define USB_RXCSRL3_FULL 0x00000002 // FIFO Full.
\r
1085 #define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready.
\r
1087 //*****************************************************************************
\r
1089 // The following are defines for the bit fields in the USB_O_RXCSRH3 register.
\r
1091 //*****************************************************************************
\r
1092 #define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear.
\r
1093 #define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request.
\r
1094 #define USB_RXCSRH3_ISO 0x00000040 // ISO.
\r
1095 #define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable.
\r
1096 #define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
\r
1097 #define USB_RXCSRH3_PIDERR 0x00000010 // PID Error.
\r
1098 #define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode.
\r
1099 #define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable.
\r
1100 #define USB_RXCSRH3_DT 0x00000002 // Data Toggle.
\r
1101 #define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive.
\r
1103 //*****************************************************************************
\r
1105 // The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
\r
1107 //*****************************************************************************
\r
1108 #define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count.
\r
1109 #define USB_RXCOUNT3_COUNT_S 0
\r
1111 //*****************************************************************************
\r
1113 // The following are defines for the bit fields in the USB_O_TXTYPE3 register.
\r
1115 //*****************************************************************************
\r
1116 #define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
\r
1117 #define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
\r
1118 #define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
\r
1119 #define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
\r
1120 #define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol.
\r
1121 #define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
\r
1122 #define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
\r
1123 #define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
\r
1124 #define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
\r
1125 #define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
\r
1126 #define USB_TXTYPE3_TEP_S 0
\r
1128 //*****************************************************************************
\r
1130 // The following are defines for the bit fields in the USB_O_TXINTERVAL3
\r
1133 //*****************************************************************************
\r
1134 #define USB_TXINTERVAL3_TXPOLL_M \
\r
1135 0x000000FF // TX Polling
\r
1136 #define USB_TXINTERVAL3_NAKLMT_M \
\r
1137 0x000000FF // NAK Limit.
\r
1138 #define USB_TXINTERVAL3_TXPOLL_S \
\r
1140 #define USB_TXINTERVAL3_NAKLMT_S \
\r
1143 //*****************************************************************************
\r
1145 // The following are defines for the bit fields in the USB_O_RXTYPE3 register.
\r
1147 //*****************************************************************************
\r
1148 #define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed.
\r
1149 #define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
\r
1150 #define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
\r
1151 #define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
\r
1152 #define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol.
\r
1153 #define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
\r
1154 #define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
\r
1155 #define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
\r
1156 #define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
\r
1157 #define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.
\r
1158 #define USB_RXTYPE3_TEP_S 0
\r
1160 //*****************************************************************************
\r
1162 // The following are defines for the bit fields in the USB_O_RXINTERVAL3
\r
1165 //*****************************************************************************
\r
1166 #define USB_RXINTERVAL3_TXPOLL_M \
\r
1167 0x000000FF // RX Polling
\r
1168 #define USB_RXINTERVAL3_NAKLMT_M \
\r
1169 0x000000FF // NAK Limit.
\r
1170 #define USB_RXINTERVAL3_TXPOLL_S \
\r
1172 #define USB_RXINTERVAL3_NAKLMT_S \
\r
1175 //*****************************************************************************
\r
1177 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
\r
1180 //*****************************************************************************
\r
1181 #define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count.
\r
1182 #define USB_RQPKTCOUNT1_S 0
\r
1184 //*****************************************************************************
\r
1186 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
\r
1189 //*****************************************************************************
\r
1190 #define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count.
\r
1191 #define USB_RQPKTCOUNT2_S 0
\r
1193 //*****************************************************************************
\r
1195 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
\r
1198 //*****************************************************************************
\r
1199 #define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count.
\r
1200 #define USB_RQPKTCOUNT3_S 0
\r
1202 //*****************************************************************************
\r
1204 // The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
\r
1207 //*****************************************************************************
\r
1208 #define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
\r
1210 #define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
\r
1212 #define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
\r
1215 //*****************************************************************************
\r
1217 // The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
\r
1220 //*****************************************************************************
\r
1221 #define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
\r
1223 #define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
\r
1225 #define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
\r
1228 //*****************************************************************************
\r
1230 // The following are defines for the bit fields in the USB_O_EPC register.
\r
1232 //*****************************************************************************
\r
1233 #define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action.
\r
1234 #define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
\r
1235 #define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
\r
1236 #define USB_EPC_PFLTACT_LOW 0x00000200 // Low
\r
1237 #define USB_EPC_PFLTACT_HIGH 0x00000300 // High
\r
1238 #define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable.
\r
1239 #define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense.
\r
1240 #define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable.
\r
1241 #define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable.
\r
1242 #define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
\r
1244 #define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
\r
1245 #define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
\r
1246 #define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
\r
1247 #define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
\r
1249 //*****************************************************************************
\r
1251 // The following are defines for the bit fields in the USB_O_EPCRIS register.
\r
1253 //*****************************************************************************
\r
1254 #define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt
\r
1257 //*****************************************************************************
\r
1259 // The following are defines for the bit fields in the USB_O_EPCIM register.
\r
1261 //*****************************************************************************
\r
1262 #define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask.
\r
1264 //*****************************************************************************
\r
1266 // The following are defines for the bit fields in the USB_O_EPCISC register.
\r
1268 //*****************************************************************************
\r
1269 #define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
\r
1272 //*****************************************************************************
\r
1274 // The following are defines for the bit fields in the USB_O_DRRIS register.
\r
1276 //*****************************************************************************
\r
1277 #define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status.
\r
1279 //*****************************************************************************
\r
1281 // The following are defines for the bit fields in the USB_O_DRIM register.
\r
1283 //*****************************************************************************
\r
1284 #define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask.
\r
1286 //*****************************************************************************
\r
1288 // The following are defines for the bit fields in the USB_O_DRISC register.
\r
1290 //*****************************************************************************
\r
1291 #define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and
\r
1294 //*****************************************************************************
\r
1296 // The following are defines for the bit fields in the USB_O_GPCS register.
\r
1298 //*****************************************************************************
\r
1299 #define USB_GPCS_DEVMOD 0x00000001 // Device Mode.
\r
1301 //*****************************************************************************
\r
1303 // The following are defines for the bit fields in the USB_O_VPLEN register.
\r
1305 //*****************************************************************************
\r
1306 #define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length.
\r
1307 #define USB_VPLEN_VPLEN_S 0
\r
1309 #endif // __HW_USB_H__
\r