git.sur5r.net Git - freertos/blob - Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h

   1 /**\r
   2   ******************************************************************************\r
   3   * @file  stm32f10x_fsmc.h\r
   4   * @author  MCD Application Team\r
   5   * @version  V3.0.0\r
   6   * @date  04/06/2009\r
   7   * @brief  This file contains all the functions prototypes for the FSMC \r
   8   *         firmware library.\r
   9   ******************************************************************************\r
  10   * @copy\r
  11   *\r
  12   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  13   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
  14   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
  15   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
  16   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
  17   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  18   *\r
  19   * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>\r
  20   */ \r
  21 \r
  22 /* Define to prevent recursive inclusion -------------------------------------*/\r
  23 #ifndef __STM32F10x_FSMC_H\r
  24 #define __STM32F10x_FSMC_H\r
  25 \r
  26 /* Includes ------------------------------------------------------------------*/\r
  27 #include "stm32f10x.h"\r
  28 \r
  29 /** @addtogroup StdPeriph_Driver\r
  30   * @{\r
  31   */\r
  32 \r
  33 /** @addtogroup FSMC\r
  34   * @{\r
  35   */\r
  36 \r
  37 /** @defgroup FSMC_Exported_Types\r
  38   * @{\r
  39   */\r
  40 \r
  41 /** \r
  42   * @brief  Timing parameters For NOR/SRAM Banks  \r
  43   */\r
  44 \r
  45 typedef struct\r
  46 {\r
  47   uint32_t FSMC_AddressSetupTime;\r
  48   uint32_t FSMC_AddressHoldTime;\r
  49   uint32_t FSMC_DataSetupTime;\r
  50   uint32_t FSMC_BusTurnAroundDuration;\r
  51   uint32_t FSMC_CLKDivision;\r
  52   uint32_t FSMC_DataLatency;\r
  53   uint32_t FSMC_AccessMode;\r
  54 }FSMC_NORSRAMTimingInitTypeDef;\r
  55 \r
  56 /** \r
  57   * @brief  FSMC NOR/SRAM Init structure definition\r
  58   */\r
  59 \r
  60 typedef struct\r
  61 {\r
  62   uint32_t FSMC_Bank;\r
  63   uint32_t FSMC_DataAddressMux;\r
  64   uint32_t FSMC_MemoryType;\r
  65   uint32_t FSMC_MemoryDataWidth;\r
  66   uint32_t FSMC_BurstAccessMode;\r
  67   uint32_t FSMC_WaitSignalPolarity;\r
  68   uint32_t FSMC_WrapMode;\r
  69   uint32_t FSMC_WaitSignalActive;\r
  70   uint32_t FSMC_WriteOperation;\r
  71   uint32_t FSMC_WaitSignal;\r
  72   uint32_t FSMC_ExtendedMode;\r
  73   uint32_t FSMC_WriteBurst;  \r
  74   FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the  ExtendedMode is not used*/\r
  75   FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the  ExtendedMode is used*/\r
  76 }FSMC_NORSRAMInitTypeDef;\r
  77 \r
  78 /** \r
  79   * @brief  Timing parameters For FSMC NAND and PCCARD Banks\r
  80   */\r
  81 \r
  82 typedef struct\r
  83 {\r
  84   uint32_t FSMC_SetupTime;\r
  85   uint32_t FSMC_WaitSetupTime;\r
  86   uint32_t FSMC_HoldSetupTime;\r
  87   uint32_t FSMC_HiZSetupTime;\r
  88 }FSMC_NAND_PCCARDTimingInitTypeDef;\r
  89 \r
  90 /** \r
  91   * @brief  FSMC NAND Init structure definition\r
  92   */\r
  93 \r
  94 typedef struct\r
  95 {\r
  96   uint32_t FSMC_Bank;\r
  97   uint32_t FSMC_Waitfeature;\r
  98   uint32_t FSMC_MemoryDataWidth;\r
  99   uint32_t FSMC_ECC;\r
 100   uint32_t FSMC_ECCPageSize;\r
 101   uint32_t FSMC_TCLRSetupTime;\r
 102   uint32_t FSMC_TARSetupTime;  \r
 103   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ \r
 104   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */\r
 105 }FSMC_NANDInitTypeDef;\r
 106 \r
 107 /** \r
 108   * @brief  FSMC PCCARD Init structure definition\r
 109   */\r
 110 \r
 111 typedef struct\r
 112 {\r
 113   uint32_t FSMC_Waitfeature;\r
 114   uint32_t FSMC_TCLRSetupTime;\r
 115   uint32_t FSMC_TARSetupTime;  \r
 116   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */\r
 117   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /* FSMC Attribute Space Timing */\r
 118   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct;  /* FSMC IO Space Timing */\r
 119 }FSMC_PCCARDInitTypeDef;\r
 120 \r
 121 /**\r
 122   * @}\r
 123   */\r
 124 \r
 125 /** @defgroup FSMC_Exported_Constants\r
 126   * @{\r
 127   */\r
 128 \r
 129 /** @defgroup FSMC_Banks_definitions \r
 130   * @{\r
 131   */\r
 132 \r
 133 #define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)\r
 134 #define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)\r
 135 #define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)\r
 136 #define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)\r
 137 #define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)\r
 138 #define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)\r
 139 #define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)\r
 140 \r
 141 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
 142                                     ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
 143                                     ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
 144                                     ((BANK) == FSMC_Bank1_NORSRAM4))\r
 145 \r
 146 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
 147                                  ((BANK) == FSMC_Bank3_NAND))\r
 148 \r
 149 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
 150                                     ((BANK) == FSMC_Bank3_NAND) || \\r
 151                                     ((BANK) == FSMC_Bank4_PCCARD))\r
 152 \r
 153 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
 154                                ((BANK) == FSMC_Bank3_NAND) || \\r
 155                                ((BANK) == FSMC_Bank4_PCCARD))\r
 156 /**\r
 157   * @}\r
 158   */\r
 159 \r
 160 /** @defgroup NOR_SRAM_Banks \r
 161   * @{\r
 162   */\r
 163 \r
 164 /** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
 165   * @{\r
 166   */\r
 167 \r
 168 #define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)\r
 169 #define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)\r
 170 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
 171                           ((MUX) == FSMC_DataAddressMux_Enable))\r
 172 \r
 173 /**\r
 174   * @}\r
 175   */\r
 176 \r
 177 /** @defgroup FSMC_Memory_Type \r
 178   * @{\r
 179   */\r
 180 \r
 181 #define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)\r
 182 #define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)\r
 183 #define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)\r
 184 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
 185                                 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
 186                                 ((MEMORY) == FSMC_MemoryType_NOR))\r
 187 \r
 188 /**\r
 189   * @}\r
 190   */\r
 191 \r
 192 /** @defgroup FSMC_Data_Width \r
 193   * @{\r
 194   */\r
 195 \r
 196 #define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)\r
 197 #define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)\r
 198 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
 199                                      ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
 200 \r
 201 /**\r
 202   * @}\r
 203   */\r
 204 \r
 205 /** @defgroup FSMC_Burst_Access_Mode \r
 206   * @{\r
 207   */\r
 208 \r
 209 #define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) \r
 210 #define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)\r
 211 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
 212                                   ((STATE) == FSMC_BurstAccessMode_Enable))\r
 213 /**\r
 214   * @}\r
 215   */\r
 216 \r
 217 /** @defgroup FSMC_Wait_Signal_Polarity \r
 218   * @{\r
 219   */\r
 220 \r
 221 #define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)\r
 222 #define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)\r
 223 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
 224                                          ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
 225 \r
 226 /**\r
 227   * @}\r
 228   */\r
 229 \r
 230 /** @defgroup FSMC_Wrap_Mode \r
 231   * @{\r
 232   */\r
 233 \r
 234 #define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)\r
 235 #define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) \r
 236 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
 237                                  ((MODE) == FSMC_WrapMode_Enable))\r
 238 \r
 239 /**\r
 240   * @}\r
 241   */\r
 242 \r
 243 /** @defgroup FSMC_Wait_Timing \r
 244   * @{\r
 245   */\r
 246 \r
 247 #define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)\r
 248 #define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) \r
 249 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
 250                                             ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
 251 \r
 252 /**\r
 253   * @}\r
 254   */\r
 255 \r
 256 /** @defgroup FSMC_Write_Operation \r
 257   * @{\r
 258   */\r
 259 \r
 260 #define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)\r
 261 #define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)\r
 262 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
 263                                             ((OPERATION) == FSMC_WriteOperation_Enable))\r
 264                               \r
 265 /**\r
 266   * @}\r
 267   */\r
 268 \r
 269 /** @defgroup FSMC_Wait_Signal \r
 270   * @{\r
 271   */\r
 272 \r
 273 #define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)\r
 274 #define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) \r
 275 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
 276                                       ((SIGNAL) == FSMC_WaitSignal_Enable))\r
 277 /**\r
 278   * @}\r
 279   */\r
 280 \r
 281 /** @defgroup FSMC_Extended_Mode \r
 282   * @{\r
 283   */\r
 284 \r
 285 #define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)\r
 286 #define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)\r
 287 \r
 288 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
 289                                      ((MODE) == FSMC_ExtendedMode_Enable)) \r
 290 \r
 291 /**\r
 292   * @}\r
 293   */\r
 294 \r
 295 /** @defgroup FSMC_Write_Burst \r
 296   * @{\r
 297   */\r
 298 \r
 299 #define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)\r
 300 #define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) \r
 301 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
 302                                     ((BURST) == FSMC_WriteBurst_Enable))\r
 303 /**\r
 304   * @}\r
 305   */\r
 306 \r
 307 /** @defgroup FSMC_Address_Setup_Time \r
 308   * @{\r
 309   */\r
 310 \r
 311 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
 312 \r
 313 /**\r
 314   * @}\r
 315   */\r
 316 \r
 317 /** @defgroup FSMC_Address_Hold_Time \r
 318   * @{\r
 319   */\r
 320 \r
 321 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
 322 \r
 323 /**\r
 324   * @}\r
 325   */\r
 326 \r
 327 /** @defgroup FSMC_Data_Setup_Time \r
 328   * @{\r
 329   */\r
 330 \r
 331 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
 332 \r
 333 /**\r
 334   * @}\r
 335   */\r
 336 \r
 337 /** @defgroup FSMC_Bus_Turn_around_Duration \r
 338   * @{\r
 339   */\r
 340 \r
 341 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
 342 \r
 343 /**\r
 344   * @}\r
 345   */\r
 346 \r
 347 /** @defgroup FSMC_CLK_Division \r
 348   * @{\r
 349   */\r
 350 \r
 351 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
 352 \r
 353 /**\r
 354   * @}\r
 355   */\r
 356 \r
 357 /** @defgroup FSMC_Data_Latency \r
 358   * @{\r
 359   */\r
 360 \r
 361 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
 362 \r
 363 /**\r
 364   * @}\r
 365   */\r
 366 \r
 367 /** @defgroup FSMC_Access_Mode \r
 368   * @{\r
 369   */\r
 370 \r
 371 #define FSMC_AccessMode_A                               ((uint32_t)0x00000000)\r
 372 #define FSMC_AccessMode_B                               ((uint32_t)0x10000000) \r
 373 #define FSMC_AccessMode_C                               ((uint32_t)0x20000000)\r
 374 #define FSMC_AccessMode_D                               ((uint32_t)0x30000000)\r
 375 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
 376                                    ((MODE) == FSMC_AccessMode_B) || \\r
 377                                    ((MODE) == FSMC_AccessMode_C) || \\r
 378                                    ((MODE) == FSMC_AccessMode_D)) \r
 379 \r
 380 /**\r
 381   * @}\r
 382   */\r
 383 \r
 384 /**\r
 385   * @}\r
 386   */\r
 387   \r
 388 /** @defgroup NAND_and_PCCARD_Banks \r
 389   * @{\r
 390   */\r
 391 \r
 392 /** @defgroup FSMC_Wait_feature \r
 393   * @{\r
 394   */\r
 395 \r
 396 #define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)\r
 397 #define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)\r
 398 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
 399                                        ((FEATURE) == FSMC_Waitfeature_Enable))\r
 400 \r
 401 /**\r
 402   * @}\r
 403   */\r
 404 \r
 405 /** @defgroup FSMC_Memory_Data_Width \r
 406   * @{\r
 407   */ \r
 408 #define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)\r
 409 #define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)\r
 410 #define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
 411                                    ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
 412 \r
 413 /**\r
 414   * @}\r
 415   */\r
 416 \r
 417 /** @defgroup FSMC_ECC \r
 418   * @{\r
 419   */\r
 420 \r
 421 #define FSMC_ECC_Disable                                ((uint32_t)0x00000000)\r
 422 #define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)\r
 423 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
 424                                   ((STATE) == FSMC_ECC_Enable))\r
 425 \r
 426 /**\r
 427   * @}\r
 428   */\r
 429 \r
 430 /** @defgroup FSMC_ECC_Page_Size \r
 431   * @{\r
 432   */\r
 433 \r
 434 #define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)\r
 435 #define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)\r
 436 #define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)\r
 437 #define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)\r
 438 #define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)\r
 439 #define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)\r
 440 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
 441                                     ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
 442                                     ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
 443                                     ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
 444                                     ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
 445                                     ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
 446 \r
 447 /**\r
 448   * @}\r
 449   */\r
 450 \r
 451 /** @defgroup FSMC_TCLR_Setup_Time \r
 452   * @{\r
 453   */\r
 454 \r
 455 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
 456 \r
 457 /**\r
 458   * @}\r
 459   */\r
 460 \r
 461 /** @defgroup FSMC_TAR_Setup_Time \r
 462   * @{\r
 463   */\r
 464 \r
 465 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
 466 \r
 467 /**\r
 468   * @}\r
 469   */\r
 470 \r
 471 /** @defgroup FSMC_Setup_Time \r
 472   * @{\r
 473   */\r
 474 \r
 475 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
 476 \r
 477 /**\r
 478   * @}\r
 479   */\r
 480 \r
 481 /** @defgroup FSMC_Wait_Setup_Time \r
 482   * @{\r
 483   */\r
 484 \r
 485 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
 486 \r
 487 /**\r
 488   * @}\r
 489   */\r
 490 \r
 491 /** @defgroup FSMC_Hold_Setup_Time \r
 492   * @{\r
 493   */\r
 494 \r
 495 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
 496 \r
 497 /**\r
 498   * @}\r
 499   */\r
 500 \r
 501 /** @defgroup FSMC_HiZ_Setup_Time \r
 502   * @{\r
 503   */\r
 504 \r
 505 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
 506 \r
 507 /**\r
 508   * @}\r
 509   */\r
 510 \r
 511 /** @defgroup FSMC_Interrupt_sources \r
 512   * @{\r
 513   */\r
 514 \r
 515 #define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)\r
 516 #define FSMC_IT_Level                                   ((uint32_t)0x00000010)\r
 517 #define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)\r
 518 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
 519 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
 520                             ((IT) == FSMC_IT_Level) || \\r
 521                             ((IT) == FSMC_IT_FallingEdge)) \r
 522 /**\r
 523   * @}\r
 524   */\r
 525 \r
 526 /** @defgroup FSMC_Flags \r
 527   * @{\r
 528   */\r
 529 \r
 530 #define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)\r
 531 #define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)\r
 532 #define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)\r
 533 #define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)\r
 534 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
 535                                 ((FLAG) == FSMC_FLAG_Level) || \\r
 536                                 ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
 537                                 ((FLAG) == FSMC_FLAG_FEMPT))\r
 538 \r
 539 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
 540 \r
 541 /**\r
 542   * @}\r
 543   */\r
 544 \r
 545 /**\r
 546   * @}\r
 547   */\r
 548 \r
 549 /**\r
 550   * @}\r
 551   */\r
 552 \r
 553 /** @defgroup FSMC_Exported_Macros\r
 554   * @{\r
 555   */\r
 556 \r
 557 /**\r
 558   * @}\r
 559   */\r
 560 \r
 561 /** @defgroup FSMC_Exported_Functions\r
 562   * @{\r
 563   */\r
 564 \r
 565 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
 566 void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
 567 void FSMC_PCCARDDeInit(void);\r
 568 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
 569 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
 570 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
 571 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
 572 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
 573 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
 574 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
 575 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
 576 void FSMC_PCCARDCmd(FunctionalState NewState);\r
 577 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
 578 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
 579 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
 580 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
 581 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
 582 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
 583 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
 584 \r
 585 #endif /*__STM32F10x_FSMC_H */\r
 586 /**\r
 587   * @}\r
 588   */\r
 589 \r
 590 /**\r
 591   * @}\r
 592   */\r
 593 \r
 594 /**\r
 595   * @}\r
 596   */ \r
 597 \r
 598 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r