1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
\r
2 * File Name : stm32f10x_tim.h
\r
3 * Author : MCD Application Team
\r
4 * Date First Issued : 09/29/2006
\r
5 * Description : This file contains all the functions prototypes for the
\r
6 * TIM firmware library.
\r
7 ********************************************************************************
\r
12 ********************************************************************************
\r
13 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
\r
15 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
\r
16 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
\r
17 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
\r
18 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
19 *******************************************************************************/
\r
21 /* Define to prevent recursive inclusion -------------------------------------*/
\r
22 #ifndef __STM32F10x_TIM_H
\r
23 #define __STM32F10x_TIM_H
\r
25 /* Includes ------------------------------------------------------------------*/
\r
26 #include "stm32f10x_map.h"
\r
28 /* Exported types ------------------------------------------------------------*/
\r
30 /* TIM Base Init structure definition */
\r
33 u16 TIM_Period; /* Period value */
\r
34 u16 TIM_Prescaler; /* Prescaler value */
\r
35 u16 TIM_ClockDivision; /* Timer clock division */
\r
36 u16 TIM_CounterMode; /* Timer Counter mode */
\r
37 } TIM_TimeBaseInitTypeDef;
\r
39 /* TIM Output Compare Init structure definition */
\r
42 u16 TIM_OCMode; /* Timer Output Compare Mode */
\r
43 u16 TIM_Channel; /* Timer Channel */
\r
44 u16 TIM_Pulse; /* PWM or OC Channel pulse length */
\r
45 u16 TIM_OCPolarity; /* PWM, OCM or OPM Channel polarity */
\r
46 } TIM_OCInitTypeDef;
\r
48 /* TIM Input Capture Init structure definition */
\r
51 u16 TIM_ICMode; /* Timer Input Capture Mode */
\r
52 u16 TIM_Channel; /* Timer Channel */
\r
53 u16 TIM_ICPolarity; /* Input Capture polarity */
\r
54 u16 TIM_ICSelection; /* Input Capture selection */
\r
55 u16 TIM_ICPrescaler; /* Input Capture prescaler */
\r
56 u8 TIM_ICFilter; /* Input Capture filter */
\r
57 } TIM_ICInitTypeDef;
\r
59 /* Exported constants -------------------------------------------------------*/
\r
60 /* TIM Ouput Compare modes --------------------------------------------------*/
\r
61 #define TIM_OCMode_Timing ((u16)0x0000)
\r
62 #define TIM_OCMode_Active ((u16)0x0010)
\r
63 #define TIM_OCMode_Inactive ((u16)0x0020)
\r
64 #define TIM_OCMode_Toggle ((u16)0x0030)
\r
65 #define TIM_OCMode_PWM1 ((u16)0x0060)
\r
66 #define TIM_OCMode_PWM2 ((u16)0x0070)
\r
68 #define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \
\r
69 (MODE == TIM_OCMode_Active) || \
\r
70 (MODE == TIM_OCMode_Inactive) || \
\r
71 (MODE == TIM_OCMode_Toggle)|| \
\r
72 (MODE == TIM_OCMode_PWM1) || \
\r
73 (MODE == TIM_OCMode_PWM2))
\r
75 /* TIM Input Capture modes --------------------------------------------------*/
\r
76 #define TIM_ICMode_ICAP ((u16)0x0007)
\r
77 #define TIM_ICMode_PWMI ((u16)0x0006)
\r
79 #define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \
\r
80 (MODE == TIM_ICMode_PWMI))
\r
82 /* TIM One Pulse Mode -------------------------------------------------------*/
\r
83 #define TIM_OPMode_Single ((u16)0x0008)
\r
84 #define TIM_OPMode_Repetitive ((u16)0x0000)
\r
86 #define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \
\r
87 (MODE == TIM_OPMode_Repetitive))
\r
89 /* TIM Channel --------------------------------------------------------------*/
\r
90 #define TIM_Channel_1 ((u16)0x0000)
\r
91 #define TIM_Channel_2 ((u16)0x0001)
\r
92 #define TIM_Channel_3 ((u16)0x0002)
\r
93 #define TIM_Channel_4 ((u16)0x0003)
\r
95 #define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \
\r
96 (CHANNEL == TIM_Channel_2) || \
\r
97 (CHANNEL == TIM_Channel_3) || \
\r
98 (CHANNEL == TIM_Channel_4))
\r
100 /* TIM Clock Division CKD ---------------------------------------------------*/
\r
101 #define TIM_CKD_DIV1 ((u16)0x0000)
\r
102 #define TIM_CKD_DIV2 ((u16)0x0100)
\r
103 #define TIM_CKD_DIV4 ((u16)0x0200)
\r
105 #define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \
\r
106 (DIV == TIM_CKD_DIV2) || \
\r
107 (DIV == TIM_CKD_DIV4))
\r
109 /* TIM Counter Mode ---------------------------------------------------------*/
\r
110 #define TIM_CounterMode_Up ((u16)0x0000)
\r
111 #define TIM_CounterMode_Down ((u16)0x0010)
\r
112 #define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
\r
113 #define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
\r
114 #define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
\r
116 #define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) || \
\r
117 (MODE == TIM_CounterMode_Down) || \
\r
118 (MODE == TIM_CounterMode_CenterAligned1) || \
\r
119 (MODE == TIM_CounterMode_CenterAligned2) || \
\r
120 (MODE == TIM_CounterMode_CenterAligned3))
\r
122 /* TIM Output Compare Polarity ----------------------------------------------*/
\r
123 #define TIM_OCPolarity_High ((u16)0x0000)
\r
124 #define TIM_OCPolarity_Low ((u16)0x0002)
\r
126 #define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \
\r
127 (POLARITY == TIM_OCPolarity_Low))
\r
129 /* TIM Input Capture Polarity -----------------------------------------------*/
\r
130 #define TIM_ICPolarity_Rising ((u16)0x0000)
\r
131 #define TIM_ICPolarity_Falling ((u16)0x0002)
\r
133 #define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \
\r
134 (POLARITY == TIM_ICPolarity_Falling))
\r
136 /* TIM Input Capture Channel Selection -------------------------------------*/
\r
137 #define TIM_ICSelection_DirectTI ((u16)0x0001)
\r
138 #define TIM_ICSelection_IndirectTI ((u16)0x0002)
\r
139 #define TIM_ICSelection_TRGI ((u16)0x0003)
\r
141 #define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \
\r
142 (SELECTION == TIM_ICSelection_IndirectTI) || \
\r
143 (SELECTION == TIM_ICSelection_TRGI))
\r
145 /* TIM Input Capture Prescaler ----------------------------------------------*/
\r
146 #define TIM_ICPSC_DIV1 ((u16)0x0000)
\r
147 #define TIM_ICPSC_DIV2 ((u16)0x0004)
\r
148 #define TIM_ICPSC_DIV4 ((u16)0x0008)
\r
149 #define TIM_ICPSC_DIV8 ((u16)0x000C)
\r
151 #define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \
\r
152 (PRESCALER == TIM_ICPSC_DIV2) || \
\r
153 (PRESCALER == TIM_ICPSC_DIV4) || \
\r
154 (PRESCALER == TIM_ICPSC_DIV8))
\r
156 /* TIM Input Capture Filer Value ---------------------------------------------*/
\r
157 #define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF)
\r
159 /* TIM interrupt sources ----------------------------------------------------*/
\r
160 #define TIM_IT_Update ((u16)0x0001)
\r
161 #define TIM_IT_CC1 ((u16)0x0002)
\r
162 #define TIM_IT_CC2 ((u16)0x0004)
\r
163 #define TIM_IT_CC3 ((u16)0x0008)
\r
164 #define TIM_IT_CC4 ((u16)0x0010)
\r
165 #define TIM_IT_Trigger ((u16)0x0040)
\r
167 #define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000))
\r
169 #define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \
\r
170 (IT == TIM_IT_CC1) || \
\r
171 (IT == TIM_IT_CC2) || \
\r
172 (IT == TIM_IT_CC3) || \
\r
173 (IT == TIM_IT_CC4) || \
\r
174 (IT == TIM_IT_Trigger))
\r
176 /* TIM DMA Base address -----------------------------------------------------*/
\r
177 #define TIM_DMABase_CR1 ((u16)0x0000)
\r
178 #define TIM_DMABase_CR2 ((u16)0x0001)
\r
179 #define TIM_DMABase_SMCR ((u16)0x0002)
\r
180 #define TIM_DMABase_DIER ((u16)0x0003)
\r
181 #define TIM_DMABase_SR ((u16)0x0004)
\r
182 #define TIM_DMABase_EGR ((u16)0x0005)
\r
183 #define TIM_DMABase_CCMR1 ((u16)0x0006)
\r
184 #define TIM_DMABase_CCMR2 ((u16)0x0007)
\r
185 #define TIM_DMABase_CCER ((u16)0x0008)
\r
186 #define TIM_DMABase_CNT ((u16)0x0009)
\r
187 #define TIM_DMABase_PSC ((u16)0x000A)
\r
188 #define TIM_DMABase_ARR ((u16)0x000B)
\r
189 #define TIM_DMABase_CCR1 ((u16)0x000D)
\r
190 #define TIM_DMABase_CCR2 ((u16)0x000E)
\r
191 #define TIM_DMABase_CCR3 ((u16)0x000F)
\r
192 #define TIM_DMABase_CCR4 ((u16)0x0010)
\r
193 #define TIM_DMABase_DCR ((u16)0x0012)
\r
195 #define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \
\r
196 (BASE == TIM_DMABase_CR2) || \
\r
197 (BASE == TIM_DMABase_SMCR) || \
\r
198 (BASE == TIM_DMABase_DIER) || \
\r
199 (BASE == TIM_DMABase_SR) || \
\r
200 (BASE == TIM_DMABase_EGR) || \
\r
201 (BASE == TIM_DMABase_CCMR1) || \
\r
202 (BASE == TIM_DMABase_CCMR2) || \
\r
203 (BASE == TIM_DMABase_CCER) || \
\r
204 (BASE == TIM_DMABase_CNT) || \
\r
205 (BASE == TIM_DMABase_PSC) || \
\r
206 (BASE == TIM_DMABase_ARR) || \
\r
207 (BASE == TIM_DMABase_CCR1) || \
\r
208 (BASE == TIM_DMABase_CCR2) || \
\r
209 (BASE == TIM_DMABase_CCR3) || \
\r
210 (BASE == TIM_DMABase_CCR4) || \
\r
211 (BASE == TIM_DMABase_DCR))
\r
213 /* TIM DMA Burst Length -----------------------------------------------------*/
\r
214 #define TIM_DMABurstLength_1Byte ((u16)0x0000)
\r
215 #define TIM_DMABurstLength_2Bytes ((u16)0x0100)
\r
216 #define TIM_DMABurstLength_3Bytes ((u16)0x0200)
\r
217 #define TIM_DMABurstLength_4Bytes ((u16)0x0300)
\r
218 #define TIM_DMABurstLength_5Bytes ((u16)0x0400)
\r
219 #define TIM_DMABurstLength_6Bytes ((u16)0x0500)
\r
220 #define TIM_DMABurstLength_7Bytes ((u16)0x0600)
\r
221 #define TIM_DMABurstLength_8Bytes ((u16)0x0700)
\r
222 #define TIM_DMABurstLength_9Bytes ((u16)0x0800)
\r
223 #define TIM_DMABurstLength_10Bytes ((u16)0x0900)
\r
224 #define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
\r
225 #define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
\r
226 #define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
\r
227 #define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
\r
228 #define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
\r
229 #define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
\r
230 #define TIM_DMABurstLength_17Bytes ((u16)0x1000)
\r
231 #define TIM_DMABurstLength_18Bytes ((u16)0x1100)
\r
233 #define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \
\r
234 (LENGTH == TIM_DMABurstLength_2Bytes) || \
\r
235 (LENGTH == TIM_DMABurstLength_3Bytes) || \
\r
236 (LENGTH == TIM_DMABurstLength_4Bytes) || \
\r
237 (LENGTH == TIM_DMABurstLength_5Bytes) || \
\r
238 (LENGTH == TIM_DMABurstLength_6Bytes) || \
\r
239 (LENGTH == TIM_DMABurstLength_7Bytes) || \
\r
240 (LENGTH == TIM_DMABurstLength_8Bytes) || \
\r
241 (LENGTH == TIM_DMABurstLength_9Bytes) || \
\r
242 (LENGTH == TIM_DMABurstLength_10Bytes) || \
\r
243 (LENGTH == TIM_DMABurstLength_11Bytes) || \
\r
244 (LENGTH == TIM_DMABurstLength_12Bytes) || \
\r
245 (LENGTH == TIM_DMABurstLength_13Bytes) || \
\r
246 (LENGTH == TIM_DMABurstLength_14Bytes) || \
\r
247 (LENGTH == TIM_DMABurstLength_15Bytes) || \
\r
248 (LENGTH == TIM_DMABurstLength_16Bytes) || \
\r
249 (LENGTH == TIM_DMABurstLength_17Bytes) || \
\r
250 (LENGTH == TIM_DMABurstLength_18Bytes))
\r
252 /* TIM DMA sources ----------------------------------------------------------*/
\r
253 #define TIM_DMA_Update ((u16)0x0100)
\r
254 #define TIM_DMA_CC1 ((u16)0x0200)
\r
255 #define TIM_DMA_CC2 ((u16)0x0400)
\r
256 #define TIM_DMA_CC3 ((u16)0x0800)
\r
257 #define TIM_DMA_CC4 ((u16)0x1000)
\r
258 #define TIM_DMA_Trigger ((u16)0x4000)
\r
260 #define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000))
\r
262 /* TIM External Trigger Prescaler -------------------------------------------*/
\r
263 #define TIM_ExtTRGPSC_OFF ((u16)0x0000)
\r
264 #define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
\r
265 #define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
\r
266 #define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
\r
268 #define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \
\r
269 (PRESCALER == TIM_ExtTRGPSC_DIV2) || \
\r
270 (PRESCALER == TIM_ExtTRGPSC_DIV4) || \
\r
271 (PRESCALER == TIM_ExtTRGPSC_DIV8))
\r
273 /* TIM Input Trigger Selection ---------------------------------------------*/
\r
274 #define TIM_TS_ITR0 ((u16)0x0000)
\r
275 #define TIM_TS_ITR1 ((u16)0x0010)
\r
276 #define TIM_TS_ITR2 ((u16)0x0020)
\r
277 #define TIM_TS_ITR3 ((u16)0x0030)
\r
278 #define TIM_TS_TI1F_ED ((u16)0x0040)
\r
279 #define TIM_TS_TI1FP1 ((u16)0x0050)
\r
280 #define TIM_TS_TI2FP2 ((u16)0x0060)
\r
281 #define TIM_TS_ETRF ((u16)0x0070)
\r
283 #define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
\r
284 (SELECTION == TIM_TS_ITR1) || \
\r
285 (SELECTION == TIM_TS_ITR2) || \
\r
286 (SELECTION == TIM_TS_ITR3) || \
\r
287 (SELECTION == TIM_TS_TI1F_ED) || \
\r
288 (SELECTION == TIM_TS_TI1FP1) || \
\r
289 (SELECTION == TIM_TS_TI2FP2) || \
\r
290 (SELECTION == TIM_TS_ETRF))
\r
292 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \
\r
293 (SELECTION == TIM_TS_ITR1) || \
\r
294 (SELECTION == TIM_TS_ITR2) || \
\r
295 (SELECTION == TIM_TS_ITR3))
\r
297 #define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \
\r
298 (SELECTION == TIM_TS_TI1FP1) || \
\r
299 (SELECTION == TIM_TS_TI2FP2))
\r
301 /* TIM External Trigger Polarity --------------------------------------------*/
\r
302 #define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
\r
303 #define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
\r
305 #define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \
\r
306 (POLARITY == TIM_ExtTRGPolarity_NonInverted))
\r
308 /* TIM Prescaler Reload Mode ------------------------------------------------*/
\r
309 #define TIM_PSCReloadMode_Update ((u16)0x0000)
\r
310 #define TIM_PSCReloadMode_Immediate ((u16)0x0001)
\r
312 #define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \
\r
313 (RELOAD == TIM_PSCReloadMode_Immediate))
\r
315 /* TIM Forced Action --------------------------------------------------------*/
\r
316 #define TIM_ForcedAction_Active ((u16)0x0050)
\r
317 #define TIM_ForcedAction_InActive ((u16)0x0040)
\r
319 #define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \
\r
320 (ACTION == TIM_ForcedAction_InActive))
\r
322 /* TIM Encoder Mode ---------------------------------------------------------*/
\r
323 #define TIM_EncoderMode_TI1 ((u16)0x0001)
\r
324 #define TIM_EncoderMode_TI2 ((u16)0x0002)
\r
325 #define TIM_EncoderMode_TI12 ((u16)0x0003)
\r
327 #define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \
\r
328 (MODE == TIM_EncoderMode_TI2) || \
\r
329 (MODE == TIM_EncoderMode_TI12))
\r
331 /* TIM Event Source ---------------------------------------------------------*/
\r
332 #define TIM_EventSource_Update ((u16)0x0001)
\r
333 #define TIM_EventSource_CC1 ((u16)0x0002)
\r
334 #define TIM_EventSource_CC2 ((u16)0x0004)
\r
335 #define TIM_EventSource_CC3 ((u16)0x0008)
\r
336 #define TIM_EventSource_CC4 ((u16)0x0010)
\r
337 #define TIM_EventSource_Trigger ((u16)0x0040)
\r
339 #define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000))
\r
342 /* TIM Update Source --------------------------------------------------------*/
\r
343 #define TIM_UpdateSource_Global ((u16)0x0000)
\r
344 #define TIM_UpdateSource_Regular ((u16)0x0001)
\r
346 #define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \
\r
347 (SOURCE == TIM_UpdateSource_Regular))
\r
349 /* TIM Ouput Compare Preload State ------------------------------------------*/
\r
350 #define TIM_OCPreload_Enable ((u16)0x0008)
\r
351 #define TIM_OCPreload_Disable ((u16)0x0000)
\r
353 #define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \
\r
354 (STATE == TIM_OCPreload_Disable))
\r
356 /* TIM Ouput Compare Fast State ---------------------------------------------*/
\r
357 #define TIM_OCFast_Enable ((u16)0x0004)
\r
358 #define TIM_OCFast_Disable ((u16)0x0000)
\r
360 #define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \
\r
361 (STATE == TIM_OCFast_Disable))
\r
363 /* TIM Trigger Output Source ------------------------------------------------*/
\r
364 #define TIM_TRGOSource_Reset ((u16)0x0000)
\r
365 #define TIM_TRGOSource_Enable ((u16)0x0010)
\r
366 #define TIM_TRGOSource_Update ((u16)0x0020)
\r
367 #define TIM_TRGOSource_OC1 ((u16)0x0030)
\r
368 #define TIM_TRGOSource_OC1Ref ((u16)0x0040)
\r
369 #define TIM_TRGOSource_OC2Ref ((u16)0x0050)
\r
370 #define TIM_TRGOSource_OC3Ref ((u16)0x0060)
\r
371 #define TIM_TRGOSource_OC4Ref ((u16)0x0070)
\r
373 #define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \
\r
374 (SOURCE == TIM_TRGOSource_Enable) || \
\r
375 (SOURCE == TIM_TRGOSource_Update) || \
\r
376 (SOURCE == TIM_TRGOSource_OC1) || \
\r
377 (SOURCE == TIM_TRGOSource_OC1Ref) || \
\r
378 (SOURCE == TIM_TRGOSource_OC2Ref) || \
\r
379 (SOURCE == TIM_TRGOSource_OC3Ref) || \
\r
380 (SOURCE == TIM_TRGOSource_OC4Ref))
\r
382 /* TIM Slave Mode -----------------------------------------------------------*/
\r
383 #define TIM_SlaveMode_Reset ((u16)0x0004)
\r
384 #define TIM_SlaveMode_Gated ((u16)0x0005)
\r
385 #define TIM_SlaveMode_Trigger ((u16)0x0006)
\r
386 #define TIM_SlaveMode_External1 ((u16)0x0007)
\r
389 #define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \
\r
390 (MODE == TIM_SlaveMode_Gated) || \
\r
391 (MODE == TIM_SlaveMode_Trigger) || \
\r
392 (MODE == TIM_SlaveMode_External1))
\r
394 /* TIM TIx External Clock Source --------------------------------------------*/
\r
395 #define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
\r
396 #define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
\r
397 #define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
\r
399 #define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \
\r
400 (SOURCE == TIM_TIxExternalCLK1Source_TI2) || \
\r
401 (SOURCE == TIM_TIxExternalCLK1Source_TI1ED))
\r
404 /* TIM Master Slave Mode ----------------------------------------------------*/
\r
405 #define TIM_MasterSlaveMode_Enable ((u16)0x0080)
\r
406 #define TIM_MasterSlaveMode_Disable ((u16)0x0000)
\r
408 #define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \
\r
409 (STATE == TIM_MasterSlaveMode_Disable))
\r
411 /* TIM Flags ----------------------------------------------------------------*/
\r
412 #define TIM_FLAG_Update ((u16)0x0001)
\r
413 #define TIM_FLAG_CC1 ((u16)0x0002)
\r
414 #define TIM_FLAG_CC2 ((u16)0x0004)
\r
415 #define TIM_FLAG_CC3 ((u16)0x0008)
\r
416 #define TIM_FLAG_CC4 ((u16)0x0010)
\r
417 #define TIM_FLAG_Trigger ((u16)0x0040)
\r
418 #define TIM_FLAG_CC1OF ((u16)0x0200)
\r
419 #define TIM_FLAG_CC2OF ((u16)0x0400)
\r
420 #define TIM_FLAG_CC3OF ((u16)0x0800)
\r
421 #define TIM_FLAG_CC4OF ((u16)0x1000)
\r
423 #define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \
\r
424 (FLAG == TIM_FLAG_CC1) || \
\r
425 (FLAG == TIM_FLAG_CC2) || \
\r
426 (FLAG == TIM_FLAG_CC3) || \
\r
427 (FLAG == TIM_FLAG_CC4) || \
\r
428 (FLAG == TIM_FLAG_Trigger) || \
\r
429 (FLAG == TIM_FLAG_CC1OF) || \
\r
430 (FLAG == TIM_FLAG_CC2OF) || \
\r
431 (FLAG == TIM_FLAG_CC3OF) || \
\r
432 (FLAG == TIM_FLAG_CC4OF))
\r
434 #define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000))
\r
438 /* Exported macro ------------------------------------------------------------*/
\r
439 /* Exported functions --------------------------------------------------------*/
\r
440 void TIM_DeInit(TIM_TypeDef* TIMx);
\r
441 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
\r
442 void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
443 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
444 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
\r
445 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
446 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
447 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
448 void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
\r
449 void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
\r
450 void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate);
\r
451 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
\r
452 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
\r
453 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
\r
454 u16 TIM_ICPolarity, u8 ICFilter);
\r
455 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
\r
457 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
\r
459 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
\r
460 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
\r
461 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
\r
462 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
463 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
464 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
465 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
\r
466 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
\r
467 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate);
\r
468 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
469 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
470 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
471 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
\r
472 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
473 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
474 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
475 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
\r
476 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);
\r
477 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
\r
478 u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
\r
479 void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
\r
480 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
481 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
482 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
483 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
\r
484 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
\r
485 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate);
\r
486 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
\r
487 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
\r
488 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
\r
489 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
\r
490 void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
\r
491 void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
\r
492 void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
\r
493 void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
\r
494 void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
\r
495 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler);
\r
496 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler);
\r
497 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler);
\r
498 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler);
\r
499 void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
\r
500 u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
\r
501 u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
\r
502 u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
\r
503 u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
\r
504 u16 TIM_GetCounter(TIM_TypeDef* TIMx);
\r
505 u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
\r
506 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
\r
507 void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
\r
508 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
\r
509 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
\r
511 #endif /*__STM32F10x_TIM_H */
\r
513 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob