1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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2 * File Name : stm32fxxx_eth.h
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3 * Author : MCD Application Team
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6 * Desciption : This file contains all the functions prototypes for the
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7 * ETHERNET firmware library.
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8 ********************************************************************************
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9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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15 *******************************************************************************/
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17 /* Define to prevent recursive inclusion -------------------------------------*/
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18 #ifndef __STM32FXXX_ETH_H
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19 #define __STM32FXXX_ETH_H
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32fxxx_eth_map.h"
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24 /* Exported types ------------------------------------------------------------*/
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25 /* ETHERNET MAC Init structure definition */
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27 /* MAC ----------------------------------*/
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28 u32 ETH_AutoNegotiation; /* Selects or not the AutoNegotiation with the external PHY */
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29 u32 ETH_Watchdog; /* Enable/disable Watchdog timer */
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30 u32 ETH_Jabber; /* Enable/disable Jabber timer */
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31 u32 ETH_JumboFrame; /* Enable/disable Jumbo frame */
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32 u32 ETH_InterFrameGap; /* Selects minimum IFG between frames during transmission */
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33 u32 ETH_CarrierSense; /* Enable/disable Carrier Sense */
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34 u32 ETH_Speed; /* Indicates the Ethernet speed: 10/100 Mbps */
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35 u32 ETH_ReceiveOwn; /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
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36 u32 ETH_LoopbackMode; /* Enable/disable internal MAC MII Loopback mode */
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37 u32 ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
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38 u32 ETH_ChecksumOffload; /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */
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39 u32 ETH_RetryTransmission; /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */
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40 u32 ETH_AutomaticPadCRCStrip; /* Enable/disable Automatic MAC Pad/CRC Stripping */
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41 u32 ETH_BackOffLimit; /* Selects the BackOff limit value */
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42 u32 ETH_DeferralCheck; /* Enable/disable deferral check function (Half-Duplex mode) */
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43 u32 ETH_ReceiveAll; /* Enable/disable all frames reception by the MAC (No fitering)*/
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44 u32 ETH_SourceAddrFilter; /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */
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45 u32 ETH_PassControlFrames; /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */
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46 u32 ETH_BroadcastFramesReception; /* Enable/disable reception of Broadcast Frames */
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47 u32 ETH_DestinationAddrFilter; /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */
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48 u32 ETH_PromiscuousMode; /* Enable/disable Promiscuous Mode */
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49 u32 ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */
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50 u32 ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */
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51 u32 ETH_HashTableHigh; /* This field contains the higher 32 bits of Hash table. */
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52 u32 ETH_HashTableLow; /* This field contains the lower 32 bits of Hash table. */
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53 u32 ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the transmit control frame */
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54 u32 ETH_ZeroQuantaPause; /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */
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55 u32 ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
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56 u32 ETH_UnicastPauseFrameDetect; /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */
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57 u32 ETH_ReceiveFlowControl; /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */
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58 u32 ETH_TransmitFlowControl; /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */
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59 u32 ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */
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60 u32 ETH_VLANTagIdentifier; /* VLAN tag identifier for receive frames */
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62 /* DMA --------------------------*/
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63 u32 ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */
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64 u32 ETH_ReceiveStoreForward; /* Enable/disable Receive store and forward */
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65 u32 ETH_FlushReceivedFrame; /* Enable/disable flushing of received frames */
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66 u32 ETH_TransmitStoreForward; /* Enable/disable Transmit store and forward */
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67 u32 ETH_TransmitThresholdControl; /* Selects the Transmit Threshold Control */
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68 u32 ETH_ForwardErrorFrames; /* Enable/disable forward to DMA of all frames except runt error frames */
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69 u32 ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */
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70 u32 ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO */
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71 u32 ETH_SecondFrameOperate; /* Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */
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72 u32 ETH_AddressAlignedBeats; /* Enable/disable Address Aligned Beats */
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73 u32 ETH_FixedBurst; /* Enable/disable the AHB Master interface fixed burst transfers */
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74 u32 ETH_RxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */
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75 u32 ETH_TxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */
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76 u32 ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
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77 u32 ETH_DMAArbitration; /* Selects DMA Tx/Rx arbitration */
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80 /*----------------------------------------------------------------------------*/
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81 /* DMA descriptors types */
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82 /*----------------------------------------------------------------------------*/
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83 /* ETHERNET DMA Desciptors data structure definition */
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85 volatile u32 Status; /* Status */
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86 volatile u32 ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
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87 volatile u32 Buffer1Addr; /* Buffer1 address pointer */
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88 volatile u32 Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
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89 } ETH_DMADESCTypeDef;
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91 /* Exported constants --------------------------------------------------------*/
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93 /*----------------------------------------------------------------------------*/
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94 /* ETHERNET Frames defines */
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95 /*----------------------------------------------------------------------------*/
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96 /* ENET Buffers setting */
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97 #define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
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98 #define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
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99 #define ETH_CRC 4 /* Ethernet CRC */
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100 #define ETH_EXTRA 2 /* Extra bytes in some cases */
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101 #define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
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102 #define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */
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103 #define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */
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104 #define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
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106 /*--------------------------------------------------------*/
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107 /* Ethernet DMA descriptors registers bits definition */
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108 /*--------------------------------------------------------*/
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109 /* DMA Tx Desciptor ---------------------------------------------------------*/
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110 /*-----------------------------------------------------------------------------------------------
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111 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | |
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112 -----------------------------------------------------------------------------------------------
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113 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
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114 -----------------------------------------------------------------------------------------------
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115 TDES2 | Buffer1 Address [31:0] |
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116 -----------------------------------------------------------------------------------------------
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117 TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
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118 ----------------------------------------------------------------------------------------------*/
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120 /* Bit definition of TDES0 register: DMA Tx descriptor status register */
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121 #define ETH_DMATxDesc_OWN (0x80000000UL) /* OWN bit: descriptor is owned by DMA engine */
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122 #define ETH_DMATxDesc_IC ((u32)0x40000000) /* Interrupt on Completion */
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123 #define ETH_DMATxDesc_LS ((u32)0x20000000) /* Last Segment */
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124 #define ETH_DMATxDesc_FS ((u32)0x10000000) /* First Segment */
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125 #define ETH_DMATxDesc_DC ((u32)0x08000000) /* Disable CRC */
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126 #define ETH_DMATxDesc_DP ((u32)0x04000000) /* Disable Padding */
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127 #define ETH_DMATxDesc_TTSE ((u32)0x02000000) /* Transmit Time Stamp Enable */
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128 #define ETH_DMATxDesc_CIC ((u32)0x00C00000) /* Checksum Insertion Control: 4 cases */
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129 #define ETH_DMATxDesc_CIC_ByPass ((u32)0x00000000) /* Do Nothing: Checksum Engine is bypassed */
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130 #define ETH_DMATxDesc_CIC_IPV4Header ((u32)0x00400000) /* IPV4 header Checksum Insertion */
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131 #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((u32)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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132 #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((u32)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */
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133 #define ETH_DMATxDesc_TER ((u32)0x00200000) /* Transmit End of Ring */
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134 #define ETH_DMATxDesc_TCH ((u32)0x00100000) /* Second Address Chained */
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135 #define ETH_DMATxDesc_TTSS ((u32)0x00020000) /* Tx Time Stamp Status */
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136 #define ETH_DMATxDesc_IHE ((u32)0x00010000) /* IP Header Error */
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137 #define ETH_DMATxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
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138 #define ETH_DMATxDesc_JT ((u32)0x00004000) /* Jabber Timeout */
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139 #define ETH_DMATxDesc_FF ((u32)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
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140 #define ETH_DMATxDesc_PCE ((u32)0x00001000) /* Payload Checksum Error */
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141 #define ETH_DMATxDesc_LCA ((u32)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */
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142 #define ETH_DMATxDesc_NC ((u32)0x00000400) /* No Carrier: no carrier signal from the tranceiver */
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143 #define ETH_DMATxDesc_LCO ((u32)0x00000200) /* Late Collision: transmission aborted due to collision */
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144 #define ETH_DMATxDesc_EC ((u32)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */
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145 #define ETH_DMATxDesc_VF ((u32)0x00000080) /* VLAN Frame */
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146 #define ETH_DMATxDesc_CC ((u32)0x00000078) /* Collision Count */
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147 #define ETH_DMATxDesc_ED ((u32)0x00000004) /* Excessive Deferral */
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148 #define ETH_DMATxDesc_UF ((u32)0x00000002) /* Underflow Error: late data arrival from the memory */
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149 #define ETH_DMATxDesc_DB ((u32)0x00000001) /* Deferred Bit */
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151 /* Bit definition of TDES1 register */
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152 #define ETH_DMATxDesc_TBS2 ((u32)0x1FFF0000) /* Transmit Buffer2 Size */
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153 #define ETH_DMATxDesc_TBS1 ((u32)0x00001FFF) /* Transmit Buffer1 Size */
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155 /* Bit definition of TDES2 register */
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156 #define ETH_DMATxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */
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158 /* Bit definition of TDES3 register */
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159 #define ETH_DMATxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */
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161 /* DMA Rx descriptor ---------------------------------------------------------*/
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162 /*---------------------------------------------------------------------------------------------------------------------
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163 RDES0 | OWN(31) | Status [30:0] |
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164 ---------------------------------------------------------------------------------------------------------------------
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165 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
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166 ---------------------------------------------------------------------------------------------------------------------
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167 RDES2 | Buffer1 Address [31:0] |
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168 ---------------------------------------------------------------------------------------------------------------------
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169 RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
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170 --------------------------------------------------------------------------------------------------------------------*/
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172 /* Bit definition of RDES0 register: DMA Rx descriptor status register */
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173 #define ETH_DMARxDesc_OWN ((u32)0x80000000) /* OWN bit: descriptor is owned by DMA engine */
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174 #define ETH_DMARxDesc_AFM ((u32)0x40000000) /* DA Filter Fail for the rx frame */
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175 #define ETH_DMARxDesc_FL ((u32)0x3FFF0000) /* Receive descriptor frame length */
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176 #define ETH_DMARxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
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177 #define ETH_DMARxDesc_DE ((u32)0x00004000) /* Desciptor error: no more descriptors for receive frame */
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178 #define ETH_DMARxDesc_SAF ((u32)0x00002000) /* SA Filter Fail for the received frame */
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179 #define ETH_DMARxDesc_LE ((u32)0x00001000) /* Frame size not matching with length field */
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180 #define ETH_DMARxDesc_OE ((u32)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */
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181 #define ETH_DMARxDesc_VLAN ((u32)0x00000400) /* VLAN Tag: received frame is a VLAN frame */
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182 #define ETH_DMARxDesc_FS ((u32)0x00000200) /* First descriptor of the frame */
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183 #define ETH_DMARxDesc_LS ((u32)0x00000100) /* Last descriptor of the frame */
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184 #define ETH_DMARxDesc_IPV4HCE ((u32)0x00000080) /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */
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185 #define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080) /* (Giant Frame)Rx - frame is longer than 1518/1522 */
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186 #define ETH_DMARxDesc_LC ((u32)0x00000040) /* Late collision occurred during reception */
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187 #define ETH_DMARxDesc_FT ((u32)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */
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188 #define ETH_DMARxDesc_RWT ((u32)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */
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189 #define ETH_DMARxDesc_RE ((u32)0x00000008) /* Receive error: error reported by MII interface */
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190 #define ETH_DMARxDesc_DBE ((u32)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */
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191 #define ETH_DMARxDesc_CE ((u32)0x00000002) /* CRC error */
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192 #define ETH_DMARxDesc_MAMPCE ((u32)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
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194 /* Bit definition of RDES1 register */
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195 #define ETH_DMARxDesc_DIC ((u32)0x80000000) /* Disable Interrupt on Completion */
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196 #define ETH_DMARxDesc_RBS2 ((u32)0x1FFF0000) /* Receive Buffer2 Size */
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197 #define ETH_DMARxDesc_RER ((u32)0x00008000) /* Receive End of Ring */
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198 #define ETH_DMARxDesc_RCH ((u32)0x00004000) /* Second Address Chained */
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199 #define ETH_DMARxDesc_RBS1 ((u32)0x00001FFF) /* Receive Buffer1 Size */
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201 /* Bit definition of RDES2 register */
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202 #define ETH_DMARxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */
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204 /* Bit definition of RDES3 register */
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205 #define ETH_DMARxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */
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207 /*----------------------------------------------------------------------------*/
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208 /* Desciption of common PHY registers */
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209 /*----------------------------------------------------------------------------*/
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210 /* PHY Read/write Timeouts */
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211 #define PHY_READ_TO ((u32)0x0004FFFF)
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212 #define PHY_WRITE_TO ((u32)0x0004FFFF)
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214 /* PHY Reset Delay */
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215 #define PHY_ResetDelay ((u32)0x000FFFFF)
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217 /* PHY Config Delay */
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218 #define PHY_ConfigDelay ((u32)0x00FFFFFF)
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220 /* PHY Register address */
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221 #define PHY_BCR 0 /* Tranceiver Basic Control Register */
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222 #define PHY_BSR 1 /* Tranceiver Basic Status Register */
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224 /* PHY basic Control register */
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225 #define PHY_Reset ((u16)0x8000) /* PHY Reset */
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226 #define PHY_Loopback ((u16)0x4000) /* Select loop-back mode */
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227 #define PHY_FULLDUPLEX_100M ((u16)0x2100) /* Set the full-duplex mode at 100 Mb/s */
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228 #define PHY_HALFDUPLEX_100M ((u16)0x2000) /* Set the half-duplex mode at 100 Mb/s */
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229 #define PHY_FULLDUPLEX_10M ((u16)0x0100) /* Set the full-duplex mode at 10 Mb/s */
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230 #define PHY_HALFDUPLEX_10M ((u16)0x0000) /* Set the half-duplex mode at 10 Mb/s */
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231 #define PHY_AutoNegotiation ((u16)0x1000) /* Enable auto-negotiation function */
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232 #define PHY_Restart_AutoNegotiation ((u16)0x0200) /* Restart auto-negotiation function */
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233 #define PHY_Powerdown ((u16)0x0800) /* Select the power down mode */
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234 #define PHY_Isolate ((u16)0x0400) /* Isolate PHY from MII */
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236 /* PHY basic status register */
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237 #define PHY_AutoNego_Complete ((u16)0x0020) /* Auto-Negotioation process completed */
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238 #define PHY_Linked_Status ((u16)0x0004) /* Valid link established */
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239 #define PHY_Jabber_detection ((u16)0x0002) /* Jabber condition detected */
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241 /* The PHY status register value change from a PHY to another so the user have to update
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242 this value depending on the used external PHY */
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244 //#define PHY_SR 31 /* Tranceiver Status Register */
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246 #define PHY_SR 16 /* Tranceiver Status Register */
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248 /* PHY status register */
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249 /* The Speed and Duplex mask values change from a PHY to another so the user have to update
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250 this value depending on the used external PHY */
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252 //#define PHY_Speed_Status ((u16)0x0004) /* Configured information of Speed: 10Mbps */
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253 //#define PHY_Duplex_Status ((u16)0x0010) /* Configured information of Duplex: Full-duplex */
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255 #define PHY_Speed_Status ((u16)0x0002) /* Configured information of Speed: 10Mbps */
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256 #define PHY_Duplex_Status ((u16)0x0004) /* Configured information of Duplex: Full-duplex */
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258 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
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259 #define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
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260 ((REG) == PHY_BSR) || \
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263 /*----------------------------------------------------------------------------*/
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265 /*----------------------------------------------------------------------------*/
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266 /* ETHERNET AutoNegotiation --------------------------------------------------*/
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267 #define ETH_AutoNegotiation_Enable ((u32)0x00000001)
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268 #define ETH_AutoNegotiation_Disable ((u32)0x00000000)
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270 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
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271 ((CMD) == ETH_AutoNegotiation_Disable))
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273 /* ETHERNET watchdog ---------------------------------------------------------*/
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274 #define ETH_Watchdog_Enable ((u32)0x00000000)
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275 #define ETH_Watchdog_Disable ((u32)0x00800000)
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277 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
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278 ((CMD) == ETH_Watchdog_Disable))
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280 /* ETHERNET Jabber -----------------------------------------------------------*/
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281 #define ETH_Jabber_Enable ((u32)0x00000000)
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282 #define ETH_Jabber_Disable ((u32)0x00400000)
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284 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
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285 ((CMD) == ETH_Jabber_Disable))
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287 /* ETHERNET Jumbo Frame ------------------------------------------------------*/
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288 #define ETH_JumboFrame_Enable ((u32)0x00100000)
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289 #define ETH_JumboFrame_Disable ((u32)0x00000000)
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291 #define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \
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292 ((CMD) == ETH_JumboFrame_Disable))
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294 /* ETHERNET Inter Frame Gap --------------------------------------------------*/
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295 #define ETH_InterFrameGap_96Bit ((u32)0x00000000) /* minimum IFG between frames during transmission is 96Bit */
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296 #define ETH_InterFrameGap_88Bit ((u32)0x00020000) /* minimum IFG between frames during transmission is 88Bit */
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297 #define ETH_InterFrameGap_80Bit ((u32)0x00040000) /* minimum IFG between frames during transmission is 80Bit */
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298 #define ETH_InterFrameGap_72Bit ((u32)0x00060000) /* minimum IFG between frames during transmission is 72Bit */
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299 #define ETH_InterFrameGap_64Bit ((u32)0x00080000) /* minimum IFG between frames during transmission is 64Bit */
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300 #define ETH_InterFrameGap_56Bit ((u32)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */
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301 #define ETH_InterFrameGap_48Bit ((u32)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */
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302 #define ETH_InterFrameGap_40Bit ((u32)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */
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304 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
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305 ((GAP) == ETH_InterFrameGap_88Bit) || \
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306 ((GAP) == ETH_InterFrameGap_80Bit) || \
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307 ((GAP) == ETH_InterFrameGap_72Bit) || \
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308 ((GAP) == ETH_InterFrameGap_64Bit) || \
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309 ((GAP) == ETH_InterFrameGap_56Bit) || \
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310 ((GAP) == ETH_InterFrameGap_48Bit) || \
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311 ((GAP) == ETH_InterFrameGap_40Bit))
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313 /* ETHERNET Carrier Sense ----------------------------------------------------*/
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314 #define ETH_CarrierSense_Enable ((u32)0x00000000)
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315 #define ETH_CarrierSense_Disable ((u32)0x00010000)
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317 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
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318 ((CMD) == ETH_CarrierSense_Disable))
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320 /* ETHERNET Speed ------------------------------------------------------------*/
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321 #define ETH_Speed_10M ((u32)0x00000000)
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322 #define ETH_Speed_100M ((u32)0x00004000)
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324 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
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325 ((SPEED) == ETH_Speed_100M))
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327 /* ETHERNET Receive Own ------------------------------------------------------*/
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328 #define ETH_ReceiveOwn_Enable ((u32)0x00000000)
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329 #define ETH_ReceiveOwn_Disable ((u32)0x00002000)
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331 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
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332 ((CMD) == ETH_ReceiveOwn_Disable))
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334 /* ETHERNET Loop back Mode ---------------------------------------------------*/
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335 #define ETH_LoopbackMode_Enable ((u32)0x00001000)
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336 #define ETH_LoopbackMode_Disable ((u32)0x00000000)
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338 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
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339 ((CMD) == ETH_LoopbackMode_Disable))
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341 /* ETHERNET Duplex mode ------------------------------------------------------*/
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342 #define ETH_Mode_FullDuplex ((u32)0x00000800)
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343 #define ETH_Mode_HalfDuplex ((u32)0x00000000)
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345 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
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346 ((MODE) == ETH_Mode_HalfDuplex))
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348 /* ETHERNET Checksum Offload -------------------------------------------------*/
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349 #define ETH_ChecksumOffload_Enable ((u32)0x00000400)
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350 #define ETH_ChecksumOffload_Disable ((u32)0x00000000)
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352 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
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353 ((CMD) == ETH_ChecksumOffload_Disable))
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355 /* ETHERNET Retry Transmission -----------------------------------------------*/
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356 #define ETH_RetryTransmission_Enable ((u32)0x00000000)
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357 #define ETH_RetryTransmission_Disable ((u32)0x00000200)
\r
359 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
\r
360 ((CMD) == ETH_RetryTransmission_Disable))
\r
362 /* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/
\r
363 #define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080)
\r
364 #define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000)
\r
366 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
\r
367 ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
\r
369 /* ETHERNET Back-Off limit ---------------------------------------------------*/
\r
370 #define ETH_BackOffLimit_10 ((u32)0x00000000)
\r
371 #define ETH_BackOffLimit_8 ((u32)0x00000020)
\r
372 #define ETH_BackOffLimit_4 ((u32)0x00000040)
\r
373 #define ETH_BackOffLimit_1 ((u32)0x00000060)
\r
375 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
\r
376 ((LIMIT) == ETH_BackOffLimit_8) || \
\r
377 ((LIMIT) == ETH_BackOffLimit_4) || \
\r
378 ((LIMIT) == ETH_BackOffLimit_1))
\r
380 /* ETHERNET Deferral Check ---------------------------------------------------*/
\r
381 #define ETH_DeferralCheck_Enable ((u32)0x00000010)
\r
382 #define ETH_DeferralCheck_Disable ((u32)0x00000000)
\r
384 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
\r
385 ((CMD) == ETH_DeferralCheck_Disable))
\r
387 /* ETHERNET Receive All ------------------------------------------------------*/
\r
388 #define ETH_ReceiveAll_Enable ((u32)0x80000000)
\r
389 #define ETH_ReceiveAll_Disable ((u32)0x00000000)
\r
391 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
\r
392 ((CMD) == ETH_ReceiveAll_Disable))
\r
394 /* ETHERNET Source Addr Filter ------------------------------------------------*/
\r
395 #define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200)
\r
396 #define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
\r
397 #define ETH_SourceAddrFilter_Disable ((u32)0x00000000)
\r
399 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
\r
400 ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
\r
401 ((CMD) == ETH_SourceAddrFilter_Disable))
\r
403 /* ETHERNET Pass Control Frames ----------------------------------------------*/
\r
404 #define ETH_PassControlFrames_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */
\r
405 #define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
\r
406 #define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
\r
408 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
\r
409 ((PASS) == ETH_PassControlFrames_ForwardAll) || \
\r
410 ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
\r
412 /* ETHERNET Broadcast Frames Reception ---------------------------------------*/
\r
413 #define ETH_BroadcastFramesReception_Enable ((u32)0x00000000)
\r
414 #define ETH_BroadcastFramesReception_Disable ((u32)0x00000020)
\r
416 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
\r
417 ((CMD) == ETH_BroadcastFramesReception_Disable))
\r
419 /* ETHERNET Destination Addr Filter ------------------------------------------*/
\r
420 #define ETH_DestinationAddrFilter_Normal ((u32)0x00000000)
\r
421 #define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008)
\r
423 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
\r
424 ((FILTER) == ETH_DestinationAddrFilter_Inverse))
\r
426 /* ETHERNET Promiscuous Mode -------------------------------------------------*/
\r
427 #define ETH_PromiscuousMode_Enable ((u32)0x00000001)
\r
428 #define ETH_PromiscuousMode_Disable ((u32)0x00000000)
\r
430 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
\r
431 ((CMD) == ETH_PromiscuousMode_Disable))
\r
433 /* ETHERNET multicast frames filter --------------------------------------------*/
\r
434 #define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404)
\r
435 #define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004)
\r
436 #define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000)
\r
437 #define ETH_MulticastFramesFilter_None ((u32)0x00000010)
\r
439 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
\r
440 ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
\r
441 ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
\r
442 ((FILTER) == ETH_MulticastFramesFilter_None))
\r
444 /* ETHERNET unicast frames filter --------------------------------------------*/
\r
445 #define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402)
\r
446 #define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002)
\r
447 #define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000)
\r
449 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
\r
450 ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
\r
451 ((FILTER) == ETH_UnicastFramesFilter_Perfect))
\r
453 /* ETHERNET Pause Time ------------------------------------------------*/
\r
454 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
\r
456 /* ETHERNET Zero Quanta Pause ------------------------------------------------*/
\r
457 #define ETH_ZeroQuantaPause_Enable ((u32)0x00000000)
\r
458 #define ETH_ZeroQuantaPause_Disable ((u32)0x00000080)
\r
460 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
\r
461 ((CMD) == ETH_ZeroQuantaPause_Disable))
\r
463 /* ETHERNET Pause Low Threshold ----------------------------------------------*/
\r
464 #define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */
\r
465 #define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */
\r
466 #define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */
\r
467 #define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */
\r
469 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
\r
470 ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
\r
471 ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
\r
472 ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
\r
474 /* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/
\r
475 #define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008)
\r
476 #define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000)
\r
478 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
\r
479 ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
\r
481 /* ETHERNET Receive Flow Control ---------------------------------------------*/
\r
482 #define ETH_ReceiveFlowControl_Enable ((u32)0x00000004)
\r
483 #define ETH_ReceiveFlowControl_Disable ((u32)0x00000000)
\r
485 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
\r
486 ((CMD) == ETH_ReceiveFlowControl_Disable))
\r
488 /* ETHERNET Transmit Flow Control --------------------------------------------*/
\r
489 #define ETH_TransmitFlowControl_Enable ((u32)0x00000002)
\r
490 #define ETH_TransmitFlowControl_Disable ((u32)0x00000000)
\r
492 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
\r
493 ((CMD) == ETH_TransmitFlowControl_Disable))
\r
495 /* ETHERNET VLAN Tag Comparison ----------------------------------------------*/
\r
496 #define ETH_VLANTagComparison_12Bit ((u32)0x00010000)
\r
497 #define ETH_VLANTagComparison_16Bit ((u32)0x00000000)
\r
499 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
\r
500 ((COMPARISON) == ETH_VLANTagComparison_16Bit))
\r
502 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
\r
504 /* ETHERNET MAC Flags ---------------------------------------------------*/
\r
505 #define ETH_MAC_FLAG_TST ((u32)0x00000200) /* Time stamp trigger flag (on MAC) */
\r
506 #define ETH_MAC_FLAG_MMCT ((u32)0x00000040) /* MMC transmit flag */
\r
507 #define ETH_MAC_FLAG_MMCR ((u32)0x00000020) /* MMC receive flag */
\r
508 #define ETH_MAC_FLAG_MMC ((u32)0x00000010) /* MMC flag (on MAC) */
\r
509 #define ETH_MAC_FLAG_PMT ((u32)0x00000008) /* PMT flag (on MAC) */
\r
511 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
\r
512 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
\r
513 ((FLAG) == ETH_MAC_FLAG_PMT))
\r
515 /* ETHERNET MAC Interrupts ---------------------------------------------------*/
\r
516 #define ETH_MAC_IT_TST ((u32)0x00000200) /* Time stamp trigger interrupt (on MAC) */
\r
517 #define ETH_MAC_IT_MMCT ((u32)0x00000040) /* MMC transmit interrupt */
\r
518 #define ETH_MAC_IT_MMCR ((u32)0x00000020) /* MMC receive interrupt */
\r
519 #define ETH_MAC_IT_MMC ((u32)0x00000010) /* MMC interrupt (on MAC) */
\r
520 #define ETH_MAC_IT_PMT ((u32)0x00000008) /* PMT interrupt (on MAC) */
\r
522 #define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
\r
523 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
\r
524 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
\r
525 ((IT) == ETH_MAC_IT_PMT))
\r
527 /* ETHERNET MAC addresses ----------------------------------------------------*/
\r
528 #define ETH_MAC_Address0 ((u32)0x00000000)
\r
529 #define ETH_MAC_Address1 ((u32)0x00000008)
\r
530 #define ETH_MAC_Address2 ((u32)0x00000010)
\r
531 #define ETH_MAC_Address3 ((u32)0x00000018)
\r
533 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
\r
534 ((ADDRESS) == ETH_MAC_Address1) || \
\r
535 ((ADDRESS) == ETH_MAC_Address2) || \
\r
536 ((ADDRESS) == ETH_MAC_Address3))
\r
538 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
\r
539 ((ADDRESS) == ETH_MAC_Address2) || \
\r
540 ((ADDRESS) == ETH_MAC_Address3))
\r
542 /* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/
\r
543 #define ETH_MAC_AddressFilter_SA ((u32)0x00000000)
\r
544 #define ETH_MAC_AddressFilter_DA ((u32)0x00000008)
\r
546 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
\r
547 ((FILTER) == ETH_MAC_AddressFilter_DA))
\r
549 /* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/
\r
550 #define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
\r
551 #define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
\r
552 #define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
\r
553 #define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
\r
554 #define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
\r
555 #define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
\r
557 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
\r
558 ((MASK) == ETH_MAC_AddressMask_Byte5) || \
\r
559 ((MASK) == ETH_MAC_AddressMask_Byte4) || \
\r
560 ((MASK) == ETH_MAC_AddressMask_Byte3) || \
\r
561 ((MASK) == ETH_MAC_AddressMask_Byte2) || \
\r
562 ((MASK) == ETH_MAC_AddressMask_Byte1))
\r
564 /*----------------------------------------------------------------------------*/
\r
565 /* Ethernet DMA Desciptors defines */
\r
566 /*----------------------------------------------------------------------------*/
\r
567 /* ETHERNET DMA Tx descriptor flags --------------------------------------------------------*/
\r
568 #define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
\r
569 ((FLAG) == ETH_DMATxDesc_IC) || \
\r
570 ((FLAG) == ETH_DMATxDesc_LS) || \
\r
571 ((FLAG) == ETH_DMATxDesc_FS) || \
\r
572 ((FLAG) == ETH_DMATxDesc_DC) || \
\r
573 ((FLAG) == ETH_DMATxDesc_DP) || \
\r
574 ((FLAG) == ETH_DMATxDesc_TTSE) || \
\r
575 ((FLAG) == ETH_DMATxDesc_TER) || \
\r
576 ((FLAG) == ETH_DMATxDesc_TCH) || \
\r
577 ((FLAG) == ETH_DMATxDesc_TTSS) || \
\r
578 ((FLAG) == ETH_DMATxDesc_IHE) || \
\r
579 ((FLAG) == ETH_DMATxDesc_ES) || \
\r
580 ((FLAG) == ETH_DMATxDesc_JT) || \
\r
581 ((FLAG) == ETH_DMATxDesc_FF) || \
\r
582 ((FLAG) == ETH_DMATxDesc_PCE) || \
\r
583 ((FLAG) == ETH_DMATxDesc_LCA) || \
\r
584 ((FLAG) == ETH_DMATxDesc_NC) || \
\r
585 ((FLAG) == ETH_DMATxDesc_LCO) || \
\r
586 ((FLAG) == ETH_DMATxDesc_EC) || \
\r
587 ((FLAG) == ETH_DMATxDesc_VF) || \
\r
588 ((FLAG) == ETH_DMATxDesc_CC) || \
\r
589 ((FLAG) == ETH_DMATxDesc_ED) || \
\r
590 ((FLAG) == ETH_DMATxDesc_UF) || \
\r
591 ((FLAG) == ETH_DMATxDesc_DB))
\r
593 /* ETHERNET DMA Tx descriptor segment ----------------------------------------*/
\r
594 #define ETH_DMATxDesc_LastSegment ((u32)0x40000000) /* Last Segment */
\r
595 #define ETH_DMATxDesc_FirstSegment ((u32)0x20000000) /* First Segment */
\r
597 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
\r
598 ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
\r
600 /* ETHERNET DMA Tx descriptor Checksum Insertion Control --------------------*/
\r
601 #define ETH_DMATxDesc_ChecksumByPass ((u32)0x00000000) /* Checksum engine bypass */
\r
602 #define ETH_DMATxDesc_ChecksumIPV4Header ((u32)0x00400000) /* IPv4 header checksum insertion */
\r
603 #define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((u32)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
\r
604 #define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((u32)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
\r
606 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
\r
607 ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
\r
608 ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
\r
609 ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
\r
611 /* ETHERNET DMA Tx Desciptor buffer size */
\r
612 #define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
\r
614 /* ETHERNET DMA Rx descriptor flags --------------------------------------------------------*/
\r
615 #define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
\r
616 ((FLAG) == ETH_DMARxDesc_AFM) || \
\r
617 ((FLAG) == ETH_DMARxDesc_ES) || \
\r
618 ((FLAG) == ETH_DMARxDesc_DE) || \
\r
619 ((FLAG) == ETH_DMARxDesc_SAF) || \
\r
620 ((FLAG) == ETH_DMARxDesc_LE) || \
\r
621 ((FLAG) == ETH_DMARxDesc_OE) || \
\r
622 ((FLAG) == ETH_DMARxDesc_VLAN) || \
\r
623 ((FLAG) == ETH_DMARxDesc_FS) || \
\r
624 ((FLAG) == ETH_DMARxDesc_LS) || \
\r
625 ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
\r
626 ((FLAG) == ETH_DMARxDesc_RxLongFrame) || \
\r
627 ((FLAG) == ETH_DMARxDesc_LC) || \
\r
628 ((FLAG) == ETH_DMARxDesc_FT) || \
\r
629 ((FLAG) == ETH_DMARxDesc_RWT) || \
\r
630 ((FLAG) == ETH_DMARxDesc_RE) || \
\r
631 ((FLAG) == ETH_DMARxDesc_DBE) || \
\r
632 ((FLAG) == ETH_DMARxDesc_CE) || \
\r
633 ((FLAG) == ETH_DMARxDesc_MAMPCE))
\r
635 /* ETHERNET DMA Rx descriptor buffers ---------------------------------------*/
\r
636 #define ETH_DMARxDesc_Buffer1 ((u32)0x00000000) /* DMA Rx Desc Buffer1 */
\r
637 #define ETH_DMARxDesc_Buffer2 ((u32)0x00000001) /* DMA Rx Desc Buffer2 */
\r
639 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
\r
640 ((BUFFER) == ETH_DMARxDesc_Buffer2))
\r
642 /*----------------------------------------------------------------------------*/
\r
643 /* Ethernet DMA defines */
\r
644 /*----------------------------------------------------------------------------*/
\r
645 /* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/
\r
646 #define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000)
\r
647 #define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000)
\r
649 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
\r
650 ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
\r
652 /* ETHERNET Receive Store Forward --------------------------------------------*/
\r
653 #define ETH_ReceiveStoreForward_Enable ((u32)0x02000000)
\r
654 #define ETH_ReceiveStoreForward_Disable ((u32)0x00000000)
\r
656 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
\r
657 ((CMD) == ETH_ReceiveStoreForward_Disable))
\r
659 /* ETHERNET Flush Received Frame ---------------------------------------------*/
\r
660 #define ETH_FlushReceivedFrame_Enable ((u32)0x00000000)
\r
661 #define ETH_FlushReceivedFrame_Disable ((u32)0x01000000)
\r
663 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
\r
664 ((CMD) == ETH_FlushReceivedFrame_Disable))
\r
666 /* ETHERNET Transmit Store Forward -------------------------------------------*/
\r
667 #define ETH_TransmitStoreForward_Enable ((u32)0x00200000)
\r
668 #define ETH_TransmitStoreForward_Disable ((u32)0x00000000)
\r
670 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
\r
671 ((CMD) == ETH_TransmitStoreForward_Disable))
\r
673 /* ETHERNET Transmit Threshold Control ---------------------------------------*/
\r
674 #define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
\r
675 #define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
\r
676 #define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
\r
677 #define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
\r
678 #define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
\r
679 #define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
\r
680 #define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
\r
681 #define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
\r
683 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
\r
684 ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
\r
685 ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
\r
686 ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
\r
687 ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
\r
688 ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
\r
689 ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
\r
690 ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
\r
692 /* ETHERNET Forward Error Frames ---------------------------------------------*/
\r
693 #define ETH_ForwardErrorFrames_Enable ((u32)0x00000080)
\r
694 #define ETH_ForwardErrorFrames_Disable ((u32)0x00000000)
\r
696 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
\r
697 ((CMD) == ETH_ForwardErrorFrames_Disable))
\r
699 /* ETHERNET Forward Undersized Good Frames -----------------------------------*/
\r
700 #define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040)
\r
701 #define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000)
\r
703 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
\r
704 ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
\r
706 /* ETHERNET Receive Threshold Control ----------------------------------------*/
\r
707 #define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
\r
708 #define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
\r
709 #define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
\r
710 #define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
\r
712 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
\r
713 ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
\r
714 ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
\r
715 ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
\r
717 /* ETHERNET Second Frame Operate ---------------------------------------------*/
\r
718 #define ETH_SecondFrameOperate_Enable ((u32)0x00000004)
\r
719 #define ETH_SecondFrameOperate_Disable ((u32)0x00000000)
\r
721 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
\r
722 ((CMD) == ETH_SecondFrameOperate_Disable))
\r
724 /* ETHERNET Address Aligned Beats --------------------------------------------*/
\r
725 #define ETH_AddressAlignedBeats_Enable ((u32)0x02000000)
\r
726 #define ETH_AddressAlignedBeats_Disable ((u32)0x00000000)
\r
728 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
\r
729 ((CMD) == ETH_AddressAlignedBeats_Disable))
\r
731 /* ETHERNET Fixed Burst ------------------------------------------------------*/
\r
732 #define ETH_FixedBurst_Enable ((u32)0x00010000)
\r
733 #define ETH_FixedBurst_Disable ((u32)0x00000000)
\r
735 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
\r
736 ((CMD) == ETH_FixedBurst_Disable))
\r
738 /* ETHERNET Rx DMA Burst Length ----------------------------------------------*/
\r
739 #define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
\r
740 #define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
\r
741 #define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
742 #define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
743 #define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
744 #define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
746 #define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
\r
747 #define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
\r
748 #define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
\r
749 #define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
\r
750 #define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
\r
751 #define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
\r
753 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
\r
754 ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
\r
755 ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
\r
756 ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
\r
757 ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
\r
758 ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
\r
759 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
\r
760 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
\r
761 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
\r
762 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
\r
763 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
\r
764 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
\r
766 /* ETHERNET Tx DMA Burst Length ----------------------------------------------*/
\r
767 #define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
\r
768 #define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
\r
769 #define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
770 #define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
771 #define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
772 #define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
774 #define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
775 #define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
776 #define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
777 #define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
778 #define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
\r
779 #define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
\r
781 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
\r
782 ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
\r
783 ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
\r
784 ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
\r
785 ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
\r
786 ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
\r
787 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
\r
788 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
\r
789 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
\r
790 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
\r
791 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
\r
792 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
\r
794 /* ETHERNET DMA Desciptor SkipLength */
\r
795 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
\r
797 /* ETHERNET DMA Arbitration --------------------------------------------------*/
\r
798 #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000)
\r
799 #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000)
\r
800 #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000)
\r
801 #define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000)
\r
802 #define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002)
\r
804 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
\r
805 ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
\r
806 ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
\r
807 ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
\r
808 ((RATIO) == ETH_DMAArbitration_RxPriorTx))
\r
810 /* ETHERNET DMA Flags ---------------------------------------------------*/
\r
811 #define ETH_DMA_FLAG_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */
\r
812 #define ETH_DMA_FLAG_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */
\r
813 #define ETH_DMA_FLAG_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */
\r
815 #define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
\r
816 #define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
\r
817 #define ETH_DMA_FLAG_AccessError ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
\r
818 #define ETH_DMA_FLAG_NIS ((u32)0x00010000) /* Normal interrupt summary flag */
\r
819 #define ETH_DMA_FLAG_AIS ((u32)0x00008000) /* Abnormal interrupt summary flag */
\r
820 #define ETH_DMA_FLAG_ER ((u32)0x00004000) /* Early receive flag */
\r
821 #define ETH_DMA_FLAG_FBE ((u32)0x00002000) /* Fatal bus error flag */
\r
822 #define ETH_DMA_FLAG_ET ((u32)0x00000400) /* Early transmit flag */
\r
823 #define ETH_DMA_FLAG_RWT ((u32)0x00000200) /* Receive watchdog timeout flag */
\r
824 #define ETH_DMA_FLAG_RPS ((u32)0x00000100) /* Receive process stopped flag */
\r
825 #define ETH_DMA_FLAG_RBU ((u32)0x00000080) /* Receive buffer unavailable flag */
\r
826 #define ETH_DMA_FLAG_R ((u32)0x00000040) /* Receive flag */
\r
827 #define ETH_DMA_FLAG_TU ((u32)0x00000020) /* Underflow flag */
\r
828 #define ETH_DMA_FLAG_RO ((u32)0x00000010) /* Overflow flag */
\r
829 #define ETH_DMA_FLAG_TJT ((u32)0x00000008) /* Transmit jabber timeout flag */
\r
830 #define ETH_DMA_FLAG_TBU ((u32)0x00000004) /* Transmit buffer unavailable flag */
\r
831 #define ETH_DMA_FLAG_TPS ((u32)0x00000002) /* Transmit process stopped flag */
\r
832 #define ETH_DMA_FLAG_T ((u32)0x00000001) /* Transmit flag */
\r
834 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
\r
835 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
\r
836 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
\r
837 ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
\r
838 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
\r
839 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
\r
840 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
\r
841 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
\r
842 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
\r
843 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
\r
844 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
\r
845 ((FLAG) == ETH_DMA_FLAG_T))
\r
847 /* ETHERNET DMA Interrupts ---------------------------------------------------*/
\r
848 #define ETH_DMA_IT_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */
\r
849 #define ETH_DMA_IT_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */
\r
850 #define ETH_DMA_IT_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */
\r
852 #define ETH_DMA_IT_NIS ((u32)0x00010000) /* Normal interrupt summary */
\r
853 #define ETH_DMA_IT_AIS ((u32)0x00008000) /* Abnormal interrupt summary */
\r
854 #define ETH_DMA_IT_ER ((u32)0x00004000) /* Early receive interrupt */
\r
855 #define ETH_DMA_IT_FBE ((u32)0x00002000) /* Fatal bus error interrupt */
\r
856 #define ETH_DMA_IT_ET ((u32)0x00000400) /* Early transmit interrupt */
\r
857 #define ETH_DMA_IT_RWT ((u32)0x00000200) /* Receive watchdog timeout interrupt */
\r
858 #define ETH_DMA_IT_RPS ((u32)0x00000100) /* Receive process stopped interrupt */
\r
859 #define ETH_DMA_IT_RBU ((u32)0x00000080) /* Receive buffer unavailable interrupt */
\r
860 #define ETH_DMA_IT_R ((u32)0x00000040) /* Receive interrupt */
\r
861 #define ETH_DMA_IT_TU ((u32)0x00000020) /* Underflow interrupt */
\r
862 #define ETH_DMA_IT_RO ((u32)0x00000010) /* Overflow interrupt */
\r
863 #define ETH_DMA_IT_TJT ((u32)0x00000008) /* Transmit jabber timeout interrupt */
\r
864 #define ETH_DMA_IT_TBU ((u32)0x00000004) /* Transmit buffer unavailable interrupt */
\r
865 #define ETH_DMA_IT_TPS ((u32)0x00000002) /* Transmit process stopped interrupt */
\r
866 #define ETH_DMA_IT_T ((u32)0x00000001) /* Transmit interrupt */
\r
868 #define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00))
\r
869 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
\r
870 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
\r
871 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
\r
872 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
\r
873 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
\r
874 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
\r
875 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
\r
876 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
\r
877 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
\r
879 /* ETHERNET DMA transmit process state --------------------------------------------------------*/
\r
880 #define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
\r
881 #define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */
\r
882 #define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) /* Running - waiting for status */
\r
883 #define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) /* Running - reading the data from host memory */
\r
884 #define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) /* Suspended - Tx Desciptor unavailabe */
\r
885 #define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */
\r
887 /* ETHERNET DMA receive process state --------------------------------------------------------*/
\r
888 #define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
\r
889 #define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */
\r
890 #define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) /* Running - waiting for packet */
\r
891 #define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) /* Suspended - Rx Desciptor unavailable */
\r
892 #define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) /* Running - closing descriptor */
\r
893 #define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */
\r
895 /* ETHERNET DMA overflow --------------------------------------------------------*/
\r
896 #define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */
\r
897 #define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) /* Overflow bit for missed frame counter */
\r
899 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
\r
900 ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
\r
902 /*----------------------------------------------------------------------------*/
\r
903 /* Ethernet PMT defines */
\r
904 /*----------------------------------------------------------------------------*/
\r
905 /* ETHERNET PMT Flags --------------------------------------------------------*/
\r
906 #define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */
\r
907 #define ETH_PMT_FLAG_WUFR ((u32)0x00000040) /* Wake-Up Frame Received */
\r
908 #define ETH_PMT_FLAG_MPR ((u32)0x00000020) /* Magic Packet Received */
\r
910 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
\r
911 ((FLAG) == ETH_PMT_FLAG_MPR))
\r
913 /*----------------------------------------------------------------------------*/
\r
914 /* Ethernet MMC defines */
\r
915 /*----------------------------------------------------------------------------*/
\r
916 /* ETHERNET MMC Tx Interrupts */
\r
917 #define ETH_MMC_IT_TGF ((u32)0x00200000) /* When Tx good frame counter reaches half the maximum value */
\r
918 #define ETH_MMC_IT_TGFMSC ((u32)0x00008000) /* When Tx good multi col counter reaches half the maximum value */
\r
919 #define ETH_MMC_IT_TGFSC ((u32)0x00004000) /* When Tx good single col counter reaches half the maximum value */
\r
921 /* ETHERNET MMC Rx Interrupts */
\r
922 #define ETH_MMC_IT_RGUF ((u32)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */
\r
923 #define ETH_MMC_IT_RFAE ((u32)0x10000040) /* When Rx alignment error counter reaches half the maximum value */
\r
924 #define ETH_MMC_IT_RFCE ((u32)0x10000020) /* When Rx crc error counter reaches half the maximum value */
\r
926 #define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \
\r
928 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
\r
929 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
\r
930 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
\r
932 /* ETHERNET MMC Registers */
\r
933 #define ETH_MMCCR ((u32)0x00000100) /* MMC CR register */
\r
934 #define ETH_MMCRIR ((u32)0x00000104) /* MMC RIR register */
\r
935 #define ETH_MMCTIR ((u32)0x00000108) /* MMC TIR register */
\r
936 #define ETH_MMCRIMR ((u32)0x0000010C) /* MMC RIMR register */
\r
937 #define ETH_MMCTIMR ((u32)0x00000110) /* MMC TIMR register */
\r
938 #define ETH_MMCTGFSCCR ((u32)0x0000014C) /* MMC TGFSCCR register */
\r
939 #define ETH_MMCTGFMSCCR ((u32)0x00000150) /* MMC TGFMSCCR register */
\r
940 #define ETH_MMCTGFCR ((u32)0x00000168) /* MMC TGFCR register */
\r
941 #define ETH_MMCRFCECR ((u32)0x00000194) /* MMC RFCECR register */
\r
942 #define ETH_MMCRFAECR ((u32)0x00000198) /* MMC RFAECR register */
\r
943 #define ETH_MMCRGUFCR ((u32)0x000001C4) /* MMC RGUFCR register */
\r
945 /* ETHERNET MMC registers */
\r
946 #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
\r
947 ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
\r
948 ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
\r
949 ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
\r
950 ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
\r
951 ((REG) == ETH_MMCRGUFCR))
\r
953 /*----------------------------------------------------------------------------*/
\r
954 /* Ethernet PTP defines */
\r
955 /*----------------------------------------------------------------------------*/
\r
956 /* ETHERNET PTP time update method -------------------------------------------*/
\r
957 #define ETH_PTP_FineUpdate ((u32)0x00000001) /* Fine Update method */
\r
958 #define ETH_PTP_CoarseUpdate ((u32)0x00000000) /* Coarse Update method */
\r
960 #define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
\r
961 ((UPDATE) == ETH_PTP_CoarseUpdate))
\r
963 /* ETHERNET PTP Flags --------------------------------------------------------*/
\r
964 #define ETH_PTP_FLAG_TSARU ((u32)0x00000020) /* Addend Register Update */
\r
965 #define ETH_PTP_FLAG_TSITE ((u32)0x00000010) /* Time Stamp Interrupt Trigger */
\r
966 #define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) /* Time Stamp Update */
\r
967 #define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) /* Time Stamp Initialize */
\r
969 #define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
\r
970 ((FLAG) == ETH_PTP_FLAG_TSITE) || \
\r
971 ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
\r
972 ((FLAG) == ETH_PTP_FLAG_TSSTI))
\r
974 /* ETHERNET PTP subsecond increment */
\r
975 #define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
\r
977 /* ETHERNET PTP time sign ----------------------------------------------------*/
\r
978 #define ETH_PTP_PositiveTime ((u32)0x00000000) /* Positive time value */
\r
979 #define ETH_PTP_NegativeTime ((u32)0x80000000) /* Negative time value */
\r
981 #define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
\r
982 ((SIGN) == ETH_PTP_NegativeTime))
\r
984 /* ETHERNET PTP time stamp low update */
\r
985 #define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
\r
987 /* ETHERNET PTP registers */
\r
988 #define ETH_PTPTSCR ((u32)0x00000700) /* PTP TSCR register */
\r
989 #define ETH_PTPSSIR ((u32)0x00000704) /* PTP SSIR register */
\r
990 #define ETH_PTPTSHR ((u32)0x00000708) /* PTP TSHR register */
\r
991 #define ETH_PTPTSLR ((u32)0x0000070C) /* PTP TSLR register */
\r
992 #define ETH_PTPTSHUR ((u32)0x00000710) /* PTP TSHUR register */
\r
993 #define ETH_PTPTSLUR ((u32)0x00000714) /* PTP TSLUR register */
\r
994 #define ETH_PTPTSAR ((u32)0x00000718) /* PTP TSAR register */
\r
995 #define ETH_PTPTTHR ((u32)0x0000071C) /* PTP TTHR register */
\r
996 #define ETH_PTPTTLR ((u32)0x00000720) /* PTP TTLR register */
\r
998 #define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
\r
999 ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
\r
1000 ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
\r
1001 ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
\r
1002 ((REG) == ETH_PTPTTLR))
\r
1004 /* Exported macro ------------------------------------------------------------*/
\r
1005 /* Exported functions ------------------------------------------------------- */
\r
1006 void ETH_DeInit(void);
\r
1007 u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
\r
1008 void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
\r
1009 void ETH_SoftwareReset(void);
\r
1010 FlagStatus ETH_GetSoftwareResetStatus(void);
\r
1011 void ETH_Start(void);
\r
1012 u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength);
\r
1013 u32 ETH_HandleRxPkt(u32 addr);
\r
1016 u32 ETH_GetRxPktSize(void);
\r
1017 void ETH_DropRxPkt(void);
\r
1019 /*--------------------------------- PHY ------------------------------------*/
\r
1020 u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
\r
1021 u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
\r
1022 u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
\r
1023 /*--------------------------------- MAC ------------------------------------*/
\r
1024 void ETH_MACTransmissionCmd(FunctionalState NewState);
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1025 void ETH_MACReceptionCmd(FunctionalState NewState);
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1026 FlagStatus ETH_GetFlowControlBusyStatus(void);
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1027 void ETH_InitiatePauseControlFrame(void);
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1028 void ETH_BackPressureActivationCmd(FunctionalState NewState);
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1029 FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG);
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1030 ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT);
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1031 void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState);
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1032 void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr);
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1033 void ETH_GetMACAddress(u32 MacAddr, u8 *Addr);
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1034 void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState);
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1035 void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter);
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1036 void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte);
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1037 /*----------------------- DMA Tx/Rx descriptors ----------------------------*/
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1038 void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount);
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1039 void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount);
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1040 FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag);
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1041 u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
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1042 void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
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1043 void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
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1044 void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment);
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1045 void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum);
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1046 void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
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1047 void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
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1048 void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
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1049 void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
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1050 void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
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1051 void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2);
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1052 void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount);
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1053 void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount);
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1054 FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag);
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1055 void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
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1056 u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
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1057 void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
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1058 void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
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1059 void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
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1060 u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer);
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1061 /*--------------------------------- DMA ------------------------------------*/
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1062 FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG);
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1063 void ETH_DMAClearFlag(u32 ETH_DMA_FLAG);
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1064 ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT);
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1065 void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT);
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1066 u32 ETH_GetTransmitProcessState(void);
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1067 u32 ETH_GetReceiveProcessState(void);
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1068 void ETH_FlushTransmitFIFO(void);
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1069 FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
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1070 void ETH_DMATransmissionCmd(FunctionalState NewState);
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1071 void ETH_DMAReceptionCmd(FunctionalState NewState);
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1072 void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState);
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1073 FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow);
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1074 u32 ETH_GetRxOverflowMissedFrameCounter(void);
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1075 u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
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1076 u32 ETH_GetCurrentTxDescStartAddress(void);
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1077 u32 ETH_GetCurrentRxDescStartAddress(void);
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1078 u32 ETH_GetCurrentTxBufferAddress(void);
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1079 u32 ETH_GetCurrentRxBufferAddress(void);
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1080 void ETH_ResumeDMATransmission(void);
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1081 void ETH_ResumeDMAReception(void);
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1082 /*--------------------------------- PMT ------------------------------------*/
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1083 void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
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1084 void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer);
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1085 void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
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1086 FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG);
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1087 void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
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1088 void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
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1089 void ETH_PowerDownCmd(FunctionalState NewState);
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1090 /*--------------------------------- MMC ------------------------------------*/
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1091 void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
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1092 void ETH_MMCResetOnReadCmd(FunctionalState NewState);
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1093 void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
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1094 void ETH_MMCCountersReset(void);
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1095 void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState);
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1096 ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT);
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1097 u32 ETH_GetMMCRegister(u32 ETH_MMCReg);
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1098 /*--------------------------------- PTP ------------------------------------*/
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1099 u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab);
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1100 u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab);
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1101 void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount);
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1102 void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount);
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1103 void ETH_EnablePTPTimeStampAddend(void);
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1104 void ETH_EnablePTPTimeStampInterruptTrigger(void);
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1105 void ETH_EnablePTPTimeStampUpdate(void);
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1106 void ETH_InitializePTPTimeStamp(void);
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1107 void ETH_PTPUpdateMethodConfig(u32 UpdateMethod);
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1108 void ETH_PTPTimeStampCmd(FunctionalState NewState);
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1109 FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG);
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1110 void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue);
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1111 void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue);
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1112 void ETH_SetPTPTimeStampAddend(u32 Value);
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1113 void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue);
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1114 u32 ETH_GetPTPRegister(u32 ETH_PTPReg);
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1116 #endif /* __STM32FXXX_ETH_H */
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1118 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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projects / freertos / blob