1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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2 * File Name : stm32fxxx_eth_map.h
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3 * Author : MCD Application Team
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6 * Description : This file contains all ETHERNET peripheral register's
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7 * definitions and memory mapping.
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8 ********************************************************************************
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9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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15 *******************************************************************************/
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17 /* Define to prevent recursive inclusion -------------------------------------*/
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18 #ifndef __STM32FXXX_ETH_MAP_H
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19 #define __STM32FXXX_ETH_MAP_H
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25 /* Includes ------------------------------------------------------------------*/
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27 #include "stm32fxxx_eth_conf.h"
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28 #include "stm32f10x_type.h"
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30 /* Exported types ------------------------------------------------------------*/
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31 /******************************************************************************/
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32 /* Ethernet Peripheral registers structures */
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33 /******************************************************************************/
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111 /******************************************************************************/
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112 /* Ethernet MAC Registers bits definitions */
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113 /******************************************************************************/
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114 //#define IPNAME_REGNAME_BITNAME /* BIT MASK */
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116 /* Bit definition for Ethernet MAC Control Register register */
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117 #define ETH_MACCR_WD ((u32)0x00800000) /* Watchdog disable */
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118 #define ETH_MACCR_JD ((u32)0x00400000) /* Jabber disable */
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119 #define ETH_MACCR_JFE ((u32)0x00100000) /* Jumbo frame enable */
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120 #define ETH_MACCR_IFG ((u32)0x000E0000) /* Inter-frame gap */
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121 #define ETH_MACCR_IFG_96Bit ((u32)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
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122 #define ETH_MACCR_IFG_88Bit ((u32)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
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123 #define ETH_MACCR_IFG_80Bit ((u32)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
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124 #define ETH_MACCR_IFG_72Bit ((u32)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
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125 #define ETH_MACCR_IFG_64Bit ((u32)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
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126 #define ETH_MACCR_IFG_56Bit ((u32)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
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127 #define ETH_MACCR_IFG_48Bit ((u32)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
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128 #define ETH_MACCR_IFG_40Bit ((u32)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
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129 #define ETH_MACCR_CSD ((u32)0x00010000) /* Carrier sense disable (during transmission) */
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130 #define ETH_MACCR_FES ((u32)0x00004000) /* Fast ethernet speed */
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131 #define ETH_MACCR_ROD ((u32)0x00002000) /* Receive own disable */
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132 #define ETH_MACCR_LM ((u32)0x00001000) /* loopback mode */
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133 #define ETH_MACCR_DM ((u32)0x00000800) /* Duplex mode */
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134 #define ETH_MACCR_IPCO ((u32)0x00000400) /* IP Checksum offload */
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135 #define ETH_MACCR_RD ((u32)0x00000200) /* Retry disable */
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136 #define ETH_MACCR_APCS ((u32)0x00000080) /* Automatic Pad/CRC stripping */
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137 #define ETH_MACCR_BL ((u32)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
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138 a transmission attempt during retries after a collision: 0 =< r <2^k */
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139 #define ETH_MACCR_BL_10 ((u32)0x00000000) /* k = min (n, 10) */
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140 #define ETH_MACCR_BL_8 ((u32)0x00000020) /* k = min (n, 8) */
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141 #define ETH_MACCR_BL_4 ((u32)0x00000040) /* k = min (n, 4) */
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142 #define ETH_MACCR_BL_1 ((u32)0x00000060) /* k = min (n, 1) */
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143 #define ETH_MACCR_DC ((u32)0x00000010) /* Defferal check */
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144 #define ETH_MACCR_TE ((u32)0x00000008) /* Transmitter enable */
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145 #define ETH_MACCR_RE ((u32)0x00000004) /* Receiver enable */
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147 /* Bit definition for Ethernet MAC Frame Filter Register */
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148 #define ETH_MACFFR_RA ((u32)0x80000000) /* Receive all */
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149 #define ETH_MACFFR_HPF ((u32)0x00000400) /* Hash or perfect filter */
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150 #define ETH_MACFFR_SAF ((u32)0x00000200) /* Source address filter enable */
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151 #define ETH_MACFFR_SAIF ((u32)0x00000100) /* SA inverse filtering */
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152 #define ETH_MACFFR_PCF ((u32)0x000000C0) /* Pass control frames: 3 cases */
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153 #define ETH_MACFFR_PCF_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */
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154 #define ETH_MACFFR_PCF_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
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155 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
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156 #define ETH_MACFFR_BFD ((u32)0x00000020) /* Broadcast frame disable */
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157 #define ETH_MACFFR_PAM ((u32)0x00000010) /* Pass all mutlicast */
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158 #define ETH_MACFFR_DAIF ((u32)0x00000008) /* DA Inverse filtering */
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159 #define ETH_MACFFR_HM ((u32)0x00000004) /* Hash multicast */
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160 #define ETH_MACFFR_HU ((u32)0x00000002) /* Hash unicast */
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161 #define ETH_MACFFR_PM ((u32)0x00000001) /* Promiscuous mode */
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163 /* Bit definition for Ethernet MAC Hash Table High Register */
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164 #define ETH_MACHTHR_HTH ((u32)0xFFFFFFFF) /* Hash table high */
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166 /* Bit definition for Ethernet MAC Hash Table Low Register */
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167 #define ETH_MACHTLR_HTL ((u32)0xFFFFFFFF) /* Hash table low */
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169 /* Bit definition for Ethernet MAC MII Address Register */
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170 #define ETH_MACMIIAR_PA ((u32)0x0000F800) /* Physical layer address */
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171 #define ETH_MACMIIAR_MR ((u32)0x000007C0) /* MII register in the selected PHY */
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172 #define ETH_MACMIIAR_CR ((u32)0x0000001C) /* CR clock range: 6 cases */
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173 #define ETH_MACMIIAR_CR_Div42 ((u32)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
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174 #define ETH_MACMIIAR_CR_Div16 ((u32)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
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175 #define ETH_MACMIIAR_CR_Div26 ((u32)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
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176 #define ETH_MACMIIAR_MW ((u32)0x00000002) /* MII write */
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177 #define ETH_MACMIIAR_MB ((u32)0x00000001) /* MII busy */
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179 /* Bit definition for Ethernet MAC MII Data Register */
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180 #define ETH_MACMIIDR_MD ((u32)0x0000FFFF) /* MII data: read/write data from/to PHY */
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182 /* Bit definition for Ethernet MAC Flow Control Register */
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183 #define ETH_MACFCR_PT ((u32)0xFFFF0000) /* Pause time */
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184 #define ETH_MACFCR_ZQPD ((u32)0x00000080) /* Zero-quanta pause disable */
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185 #define ETH_MACFCR_PLT ((u32)0x00000030) /* Pause low threshold: 4 cases */
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186 #define ETH_MACFCR_PLT_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */
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187 #define ETH_MACFCR_PLT_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */
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188 #define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */
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189 #define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */
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190 #define ETH_MACFCR_UPFD ((u32)0x00000008) /* Unicast pause frame detect */
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191 #define ETH_MACFCR_RFCE ((u32)0x00000004) /* Receive flow control enable */
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192 #define ETH_MACFCR_TFCE ((u32)0x00000002) /* Transmit flow control enable */
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193 #define ETH_MACFCR_FCBBPA ((u32)0x00000001) /* Flow control busy/backpressure activate */
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195 /* Bit definition for Ethernet MAC VLAN Tag Register */
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196 #define ETH_MACVLANTR_VLANTC ((u32)0x00010000) /* 12-bit VLAN tag comparison */
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197 #define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
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199 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
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200 #define ETH_MACRWUFFR_D ((u32)0xFFFFFFFF) /* Wake-up frame filter register data */
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201 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
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202 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
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203 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
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204 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
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205 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
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206 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
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207 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
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208 RSVD - Filter1 Command - RSVD - Filter0 Command
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209 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
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210 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
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211 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
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213 /* Bit definition for Ethernet MAC PMT Control and Status Register */
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214 #define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
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215 #define ETH_MACPMTCSR_GU ((u32)0x00000200) /* Global Unicast */
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216 #define ETH_MACPMTCSR_WFR ((u32)0x00000040) /* Wake-Up Frame Received */
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217 #define ETH_MACPMTCSR_MPR ((u32)0x00000020) /* Magic Packet Received */
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218 #define ETH_MACPMTCSR_WFE ((u32)0x00000004) /* Wake-Up Frame Enable */
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219 #define ETH_MACPMTCSR_MPE ((u32)0x00000002) /* Magic Packet Enable */
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220 #define ETH_MACPMTCSR_PD ((u32)0x00000001) /* Power Down */
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222 /* Bit definition for Ethernet MAC Status Register */
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223 #define ETH_MACSR_TSTS ((u32)0x00000200) /* Time stamp trigger status */
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224 #define ETH_MACSR_MMCTS ((u32)0x00000040) /* MMC transmit status */
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225 #define ETH_MACSR_MMMCRS ((u32)0x00000020) /* MMC receive status */
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226 #define ETH_MACSR_MMCS ((u32)0x00000010) /* MMC status */
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227 #define ETH_MACSR_PMTS ((u32)0x00000008) /* PMT status */
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229 /* Bit definition for Ethernet MAC Interrupt Mask Register */
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230 #define ETH_MACIMR_TSTIM ((u32)0x00000200) /* Time stamp trigger interrupt mask */
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231 #define ETH_MACIMR_PMTIM ((u32)0x00000008) /* PMT interrupt mask */
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233 /* Bit definition for Ethernet MAC Address0 High Register */
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234 #define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) /* MAC address0 high */
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236 /* Bit definition for Ethernet MAC Address0 Low Register */
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237 #define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) /* MAC address0 low */
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239 /* Bit definition for Ethernet MAC Address1 High Register */
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240 #define ETH_MACA1HR_AE ((u32)0x80000000) /* Address enable */
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241 #define ETH_MACA1HR_SA ((u32)0x40000000) /* Source address */
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242 #define ETH_MACA1HR_MBC ((u32)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
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243 #define ETH_MACA1HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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244 #define ETH_MACA1HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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245 #define ETH_MACA1HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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246 #define ETH_MACA1HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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247 #define ETH_MACA1HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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248 #define ETH_MACA1HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [7:0] */
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249 #define ETH_MACA1HR_MACA1H ((u32)0x0000FFFF) /* MAC address1 high */
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251 /* Bit definition for Ethernet MAC Address1 Low Register */
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252 #define ETH_MACA1LR_MACA1L ((u32)0xFFFFFFFF) /* MAC address1 low */
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254 /* Bit definition for Ethernet MAC Address2 High Register */
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255 #define ETH_MACA2HR_AE ((u32)0x80000000) /* Address enable */
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256 #define ETH_MACA2HR_SA ((u32)0x40000000) /* Source address */
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257 #define ETH_MACA2HR_MBC ((u32)0x3F000000) /* Mask byte control */
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258 #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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259 #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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260 #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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261 #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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262 #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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263 #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
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264 #define ETH_MACA2HR_MACA2H ((u32)0x0000FFFF) /* MAC address1 high */
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266 /* Bit definition for Ethernet MAC Address2 Low Register */
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267 #define ETH_MACA2LR_MACA2L ((u32)0xFFFFFFFF) /* MAC address2 low */
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269 /* Bit definition for Ethernet MAC Address3 High Register */
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270 #define ETH_MACA3HR_AE ((u32)0x80000000) /* Address enable */
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271 #define ETH_MACA3HR_SA ((u32)0x40000000) /* Source address */
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272 #define ETH_MACA3HR_MBC ((u32)0x3F000000) /* Mask byte control */
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273 #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */
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274 #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */
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275 #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */
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276 #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */
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277 #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */
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278 #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */
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279 #define ETH_MACA3HR_MACA3H ((u32)0x0000FFFF) /* MAC address3 high */
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281 /* Bit definition for Ethernet MAC Address3 Low Register */
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282 #define ETH_MACA3LR_MACA3L ((u32)0xFFFFFFFF) /* MAC address3 low */
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284 /******************************************************************************/
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285 /* Ethernet MMC Registers bits definition */
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286 /******************************************************************************/
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288 /* Bit definition for Ethernet MMC Contol Register */
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289 #define ETH_MMCCR_MCF ((u32)0x00000008) /* MMC Counter Freeze */
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290 #define ETH_MMCCR_ROR ((u32)0x00000004) /* Reset on Read */
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291 #define ETH_MMCCR_CSR ((u32)0x00000002) /* Counter Stop Rollover */
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292 #define ETH_MMCCR_CR ((u32)0x00000001) /* Counters Reset */
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294 /* Bit definition for Ethernet MMC Receive Interrupt Register */
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295 #define ETH_MMCRIR_RGUFS ((u32)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
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296 #define ETH_MMCRIR_RFAES ((u32)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
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297 #define ETH_MMCRIR_RFCES ((u32)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
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299 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
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300 #define ETH_MMCTIR_TGFS ((u32)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
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301 #define ETH_MMCTIR_TGFMSCS ((u32)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
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302 #define ETH_MMCTIR_TGFSCS ((u32)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
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304 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
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305 #define ETH_MMCRIMR_RGUFM ((u32)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
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306 #define ETH_MMCRIMR_RFAEM ((u32)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
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307 #define ETH_MMCRIMR_RFCEM ((u32)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
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309 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
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310 #define ETH_MMCTIMR_TGFM ((u32)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
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311 #define ETH_MMCTIMR_TGFMSCM ((u32)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
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312 #define ETH_MMCTIMR_TGFSCM ((u32)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
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314 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
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315 #define ETH_MMCTGFSCCR_TGFSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
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317 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
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318 #define ETH_MMCTGFMSCCR_TGFMSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
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320 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
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321 #define ETH_MMCTGFCR_TGFC ((u32)0xFFFFFFFF) /* Number of good frames transmitted. */
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323 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
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324 #define ETH_MMCRFCECR_RFCEC ((u32)0xFFFFFFFF) /* Number of frames received with CRC error. */
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326 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
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327 #define ETH_MMCRFAECR_RFAEC ((u32)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
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329 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
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330 #define ETH_MMCRGUFCR_RGUFC ((u32)0xFFFFFFFF) /* Number of good unicast frames received. */
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332 /******************************************************************************/
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333 /* Ethernet PTP Registers bits definition */
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334 /******************************************************************************/
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336 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
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337 #define ETH_PTPTSCR_TSARU ((u32)0x00000020) /* Addend register update */
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338 #define ETH_PTPTSCR_TSITE ((u32)0x00000010) /* Time stamp interrupt trigger enable */
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339 #define ETH_PTPTSCR_TSSTU ((u32)0x00000008) /* Time stamp update */
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340 #define ETH_PTPTSCR_TSSTI ((u32)0x00000004) /* Time stamp initialize */
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341 #define ETH_PTPTSCR_TSFCU ((u32)0x00000002) /* Time stamp fine or coarse update */
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342 #define ETH_PTPTSCR_TSE ((u32)0x00000001) /* Time stamp enable */
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344 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
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345 #define ETH_PTPSSIR_STSSI ((u32)0x000000FF) /* System time Sub-second increment value */
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347 /* Bit definition for Ethernet PTP Time Stamp High Register */
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348 #define ETH_PTPTSHR_STS ((u32)0xFFFFFFFF) /* System Time second */
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350 /* Bit definition for Ethernet PTP Time Stamp Low Register */
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351 #define ETH_PTPTSLR_STPNS ((u32)0x80000000) /* System Time Positive or negative time */
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352 #define ETH_PTPTSLR_STSS ((u32)0x7FFFFFFF) /* System Time sub-seconds */
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354 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
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355 #define ETH_PTPTSHUR_TSUS ((u32)0xFFFFFFFF) /* Time stamp update seconds */
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357 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
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358 #define ETH_PTPTSLUR_TSUPNS ((u32)0x80000000) /* Time stamp update Positive or negative time */
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359 #define ETH_PTPTSLUR_TSUSS ((u32)0x7FFFFFFF) /* Time stamp update sub-seconds */
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361 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
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362 #define ETH_PTPTSAR_TSA ((u32)0xFFFFFFFF) /* Time stamp addend */
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364 /* Bit definition for Ethernet PTP Target Time High Register */
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365 #define ETH_PTPTTHR_TTSH ((u32)0xFFFFFFFF) /* Target time stamp high */
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367 /* Bit definition for Ethernet PTP Target Time Low Register */
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368 #define ETH_PTPTTLR_TTSL ((u32)0xFFFFFFFF) /* Target time stamp low */
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370 /******************************************************************************/
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371 /* Ethernet DMA Registers bits definition */
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372 /******************************************************************************/
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374 /* Bit definition for Ethernet DMA Bus Mode Register */
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375 #define ETH_DMABMR_AAB ((u32)0x02000000) /* Address-Aligned beats */
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376 #define ETH_DMABMR_FPM ((u32)0x01000000) /* 4xPBL mode */
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377 #define ETH_DMABMR_USP ((u32)0x00800000) /* Use separate PBL */
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378 #define ETH_DMABMR_RDP ((u32)0x007E0000) /* RxDMA PBL */
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379 /* Values to be confirmed: maybe they are inversed */
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380 #define ETH_DMABMR_RDP_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
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381 #define ETH_DMABMR_RDP_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
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382 #define ETH_DMABMR_RDP_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
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383 #define ETH_DMABMR_RDP_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
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384 #define ETH_DMABMR_RDP_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
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385 #define ETH_DMABMR_RDP_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
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386 #define ETH_DMABMR_RDP_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
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387 #define ETH_DMABMR_RDP_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
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388 #define ETH_DMABMR_RDP_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
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389 #define ETH_DMABMR_RDP_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
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390 #define ETH_DMABMR_RDP_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
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391 #define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
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392 #define ETH_DMABMR_FB ((u32)0x00010000) /* Fixed Burst */
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393 #define ETH_DMABMR_RTPR ((u32)0x0000C000) /* Rx Tx priority ratio */
\r
394 #define ETH_DMABMR_RTPR_1_1 ((u32)0x00000000) /* Rx Tx priority ratio */
\r
395 #define ETH_DMABMR_RTPR_2_1 ((u32)0x00004000) /* Rx Tx priority ratio */
\r
396 #define ETH_DMABMR_RTPR_3_1 ((u32)0x00008000) /* Rx Tx priority ratio */
\r
397 #define ETH_DMABMR_RTPR_4_1 ((u32)0x0000C000) /* Rx Tx priority ratio */
\r
398 #define ETH_DMABMR_PBL ((u32)0x00003F00) /* Programmable burst length */
\r
399 /* Values to be confirmed: maybe they are inversed */
\r
400 #define ETH_DMABMR_PBL_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
\r
401 #define ETH_DMABMR_PBL_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
\r
402 #define ETH_DMABMR_PBL_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
403 #define ETH_DMABMR_PBL_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
404 #define ETH_DMABMR_PBL_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
405 #define ETH_DMABMR_PBL_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
406 #define ETH_DMABMR_PBL_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
\r
407 #define ETH_DMABMR_PBL_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
\r
408 #define ETH_DMABMR_PBL_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
\r
409 #define ETH_DMABMR_PBL_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
\r
410 #define ETH_DMABMR_PBL_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
\r
411 #define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
\r
412 #define ETH_DMABMR_DSL ((u32)0x0000007C) /* Descriptor Skip Length */
\r
413 #define ETH_DMABMR_DA ((u32)0x00000002) /* DMA arbitration scheme */
\r
414 #define ETH_DMABMR_SR ((u32)0x00000001) /* Software reset */
\r
416 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
\r
417 #define ETH_DMATPDR_TPD ((u32)0xFFFFFFFF) /* Transmit poll demand */
\r
419 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
\r
420 #define ETH_DMARPDR_RPD ((u32)0xFFFFFFFF) /* Receive poll demand */
\r
422 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
\r
423 #define ETH_DMARDLAR_SRL ((u32)0xFFFFFFFF) /* Start of receive list */
\r
425 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
\r
426 #define ETH_DMATDLAR_STL ((u32)0xFFFFFFFF) /* Start of transmit list */
\r
428 /* Bit definition for Ethernet DMA Status Register */
\r
429 #define ETH_DMASR_TSTS ((u32)0x20000000) /* Time-stamp trigger status */
\r
430 #define ETH_DMASR_PMTS ((u32)0x10000000) /* PMT status */
\r
431 #define ETH_DMASR_MMCS ((u32)0x08000000) /* MMC status */
\r
432 #define ETH_DMASR_EBS ((u32)0x03800000) /* Error bits status */
\r
433 /* combination with EBS[2:0] for GetFlagStatus function */
\r
434 #define ETH_DMASR_EBS_DescAccess ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
\r
435 #define ETH_DMASR_EBS_ReadTransf ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
\r
436 #define ETH_DMASR_EBS_DataTransfTx ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
\r
437 #define ETH_DMASR_TPS ((u32)0x00700000) /* Transmit process state */
\r
438 #define ETH_DMASR_TPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
\r
439 #define ETH_DMASR_TPS_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */
\r
440 #define ETH_DMASR_TPS_Waiting ((u32)0x00200000) /* Running - waiting for status */
\r
441 #define ETH_DMASR_TPS_Reading ((u32)0x00300000) /* Running - reading the data from host memory */
\r
442 #define ETH_DMASR_TPS_Suspended ((u32)0x00600000) /* Suspended - Tx Descriptor unavailabe */
\r
443 #define ETH_DMASR_TPS_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */
\r
444 #define ETH_DMASR_RPS ((u32)0x000E0000) /* Receive process state */
\r
445 #define ETH_DMASR_RPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
\r
446 #define ETH_DMASR_RPS_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */
\r
447 #define ETH_DMASR_RPS_Waiting ((u32)0x00060000) /* Running - waiting for packet */
\r
448 #define ETH_DMASR_RPS_Suspended ((u32)0x00080000) /* Suspended - Rx Descriptor unavailable */
\r
449 #define ETH_DMASR_RPS_Closing ((u32)0x000A0000) /* Running - closing descriptor */
\r
450 #define ETH_DMASR_RPS_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */
\r
451 #define ETH_DMASR_NIS ((u32)0x00010000) /* Normal interrupt summary */
\r
452 #define ETH_DMASR_AIS ((u32)0x00008000) /* Abnormal interrupt summary */
\r
453 #define ETH_DMASR_ERS ((u32)0x00004000) /* Early receive status */
\r
454 #define ETH_DMASR_FBES ((u32)0x00002000) /* Fatal bus error status */
\r
455 #define ETH_DMASR_ETS ((u32)0x00000400) /* Early transmit status */
\r
456 #define ETH_DMASR_RWTS ((u32)0x00000200) /* Receive watchdog timeout status */
\r
457 #define ETH_DMASR_RPSS ((u32)0x00000100) /* Receive process stopped status */
\r
458 #define ETH_DMASR_RBUS ((u32)0x00000080) /* Receive buffer unavailable status */
\r
459 #define ETH_DMASR_RS ((u32)0x00000040) /* Receive status */
\r
460 #define ETH_DMASR_TUS ((u32)0x00000020) /* Transmit underflow status */
\r
461 #define ETH_DMASR_ROS ((u32)0x00000010) /* Receive overflow status */
\r
462 #define ETH_DMASR_TJTS ((u32)0x00000008) /* Transmit jabber timeout status */
\r
463 #define ETH_DMASR_TBUS ((u32)0x00000004) /* Transmit buffer unavailable status */
\r
464 #define ETH_DMASR_TPSS ((u32)0x00000002) /* Transmit process stopped status */
\r
465 #define ETH_DMASR_TS ((u32)0x00000001) /* Transmit status */
\r
467 /* Bit definition for Ethernet DMA Operation Mode Register */
\r
468 #define ETH_DMAOMR_DTCEFD ((u32)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
\r
469 #define ETH_DMAOMR_RSF ((u32)0x02000000) /* Receive store and forward */
\r
470 #define ETH_DMAOMR_DFRF ((u32)0x01000000) /* Disable flushing of received frames */
\r
471 #define ETH_DMAOMR_TSF ((u32)0x00200000) /* Transmit store and forward */
\r
472 #define ETH_DMAOMR_FTF ((u32)0x00100000) /* Flush transmit FIFO */
\r
473 #define ETH_DMAOMR_TTC ((u32)0x0001C000) /* Transmit threshold control */
\r
474 #define ETH_DMAOMR_TTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
\r
475 #define ETH_DMAOMR_TTC_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
\r
476 #define ETH_DMAOMR_TTC_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
\r
477 #define ETH_DMAOMR_TTC_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
\r
478 #define ETH_DMAOMR_TTC_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
\r
479 #define ETH_DMAOMR_TTC_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
\r
480 #define ETH_DMAOMR_TTC_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
\r
481 #define ETH_DMAOMR_TTC_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
\r
482 #define ETH_DMAOMR_ST ((u32)0x00002000) /* Start/stop transmission command */
\r
483 #define ETH_DMAOMR_FEF ((u32)0x00000080) /* Forward error frames */
\r
484 #define ETH_DMAOMR_FUGF ((u32)0x00000040) /* Forward undersized good frames */
\r
485 #define ETH_DMAOMR_RTC ((u32)0x00000018) /* receive threshold control */
\r
486 #define ETH_DMAOMR_RTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
\r
487 #define ETH_DMAOMR_RTC_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
\r
488 #define ETH_DMAOMR_RTC_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
\r
489 #define ETH_DMAOMR_RTC_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
\r
490 #define ETH_DMAOMR_OSF ((u32)0x00000004) /* operate on second frame */
\r
491 #define ETH_DMAOMR_SR ((u32)0x00000002) /* Start/stop receive */
\r
493 /* Bit definition for Ethernet DMA Interrupt Enable Register */
\r
494 #define ETH_DMAIER_NISE ((u32)0x00010000) /* Normal interrupt summary enable */
\r
495 #define ETH_DMAIER_AISE ((u32)0x00008000) /* Abnormal interrupt summary enable */
\r
496 #define ETH_DMAIER_ERIE ((u32)0x00004000) /* Early receive interrupt enable */
\r
497 #define ETH_DMAIER_FBEIE ((u32)0x00002000) /* Fatal bus error interrupt enable */
\r
498 #define ETH_DMAIER_ETIE ((u32)0x00000400) /* Early transmit interrupt enable */
\r
499 #define ETH_DMAIER_RWTIE ((u32)0x00000200) /* Receive watchdog timeout interrupt enable */
\r
500 #define ETH_DMAIER_RPSIE ((u32)0x00000100) /* Receive process stopped interrupt enable */
\r
501 #define ETH_DMAIER_RBUIE ((u32)0x00000080) /* Receive buffer unavailable interrupt enable */
\r
502 #define ETH_DMAIER_RIE ((u32)0x00000040) /* Receive interrupt enable */
\r
503 #define ETH_DMAIER_TUIE ((u32)0x00000020) /* Transmit Underflow interrupt enable */
\r
504 #define ETH_DMAIER_ROIE ((u32)0x00000010) /* Receive Overflow interrupt enable */
\r
505 #define ETH_DMAIER_TJTIE ((u32)0x00000008) /* Transmit jabber timeout interrupt enable */
\r
506 #define ETH_DMAIER_TBUIE ((u32)0x00000004) /* Transmit buffer unavailable interrupt enable */
\r
507 #define ETH_DMAIER_TPSIE ((u32)0x00000002) /* Transmit process stopped interrupt enable */
\r
508 #define ETH_DMAIER_TIE ((u32)0x00000001) /* Transmit interrupt enable */
\r
510 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
\r
511 #define ETH_DMAMFBOCR_OFOC ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */
\r
512 #define ETH_DMAMFBOCR_MFA ((u32)0x0FFE0000) /* Number of frames missed by the application */
\r
513 #define ETH_DMAMFBOCR_OMFC ((u32)0x00010000) /* Overflow bit for missed frame counter */
\r
514 #define ETH_DMAMFBOCR_MFC ((u32)0x0000FFFF) /* Number of frames missed by the controller */
\r
516 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
\r
517 #define ETH_DMACHTDR_HTDAP ((u32)0xFFFFFFFF) /* Host transmit descriptor address pointer */
\r
519 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
\r
520 #define ETH_DMACHRDR_HRDAP ((u32)0xFFFFFFFF) /* Host receive descriptor address pointer */
\r
522 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
\r
523 #define ETH_DMACHTBAR_HTBAP ((u32)0xFFFFFFFF) /* Host transmit buffer address pointer */
\r
525 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
\r
526 #define ETH_DMACHRBAR_HRBAP ((u32)0xFFFFFFFF) /* Host receive buffer address pointer */
\r
528 /******************************************************************************/
\r
530 /******************************************************************************/
\r
531 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
\r
532 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
\r
533 #define READ_BIT(REG, BIT) ((REG) & (BIT))
\r
535 /******************************************************************************/
\r
536 /* Peripheral memory map */
\r
537 /******************************************************************************/
\r
538 /* ETHERNET registers base address */
\r
539 #define ETH_BASE ((u32)0x40028000)
\r
540 #define ETH_MAC_BASE (ETH_BASE)
\r
541 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
\r
542 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
\r
543 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
\r
545 /******************************************************************************/
\r
546 /* Peripheral declaration */
\r
547 /******************************************************************************/
\r
549 /*------------------------ Non Debug Mode ------------------------------------*/
\r
552 #define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE)
\r
553 #endif /*_ETH_MAC */
\r
556 #define ETH_MMC ((ETH_MMC_TypeDef *) ETH_MMC_BASE)
\r
557 #endif /*_ETH_MMC */
\r
560 #define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE)
\r
561 #endif /*_ETH_PTP */
\r
564 #define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE)
\r
565 #endif /*_ETH_DMA */
\r
567 /*------------------------ Debug Mode ----------------------------------------*/
\r
568 #else /* ETH_DEBUG */
\r
570 EXT ETH_MAC_TypeDef *ETH_MAC;
\r
571 #endif /*_ETH_MAC */
\r
574 EXT ETH_MMC_TypeDef *ETH_MMC;
\r
575 #endif /*_ETH_MMC */
\r
578 EXT ETH_PTP_TypeDef *ETH_PTP;
\r
579 #endif /*_ETH_PTP */
\r
582 EXT ETH_DMA_TypeDef *ETH_DMA;
\r
583 #endif /*_ETH_DMA */
\r
585 #endif /* ETH_DEBUG */
\r
587 /* Exported constants --------------------------------------------------------*/
\r
588 /* Exported macro ------------------------------------------------------------*/
\r
589 /* Exported functions ------------------------------------------------------- */
\r
591 #endif /* __STM32FXXX_ETH_MAP_H */
\r
593 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
\r
projects / freertos / blob