1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_dma.c
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file provides all the DMA firmware functions.
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6 ********************************************************************************
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11 ********************************************************************************
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12 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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14 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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15 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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16 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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17 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *******************************************************************************/
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20 /* Includes ------------------------------------------------------------------*/
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21 #include "stm32f10x_dma.h"
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22 #include "stm32f10x_rcc.h"
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24 /* Private typedef -----------------------------------------------------------*/
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25 /* Private define ------------------------------------------------------------*/
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26 /* DMA ENABLE mask */
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27 #define CCR_ENABLE_Set ((u32)0x00000001)
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28 #define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
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30 /* DMA Channelx interrupt pending bit masks */
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31 #define DMA_Channel1_IT_Mask ((u32)0x0000000F)
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32 #define DMA_Channel2_IT_Mask ((u32)0x000000F0)
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33 #define DMA_Channel3_IT_Mask ((u32)0x00000F00)
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34 #define DMA_Channel4_IT_Mask ((u32)0x0000F000)
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35 #define DMA_Channel5_IT_Mask ((u32)0x000F0000)
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36 #define DMA_Channel6_IT_Mask ((u32)0x00F00000)
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37 #define DMA_Channel7_IT_Mask ((u32)0x0F000000)
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39 /* DMA registers Masks */
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40 #define CCR_CLEAR_Mask ((u32)0xFFFF800F)
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42 /* Private macro -------------------------------------------------------------*/
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43 /* Private variables ---------------------------------------------------------*/
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44 /* Private function prototypes -----------------------------------------------*/
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45 /* Private functions ---------------------------------------------------------*/
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47 /*******************************************************************************
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48 * Function Name : DMA_DeInit
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49 * Description : Deinitializes the DMA Channelx registers to their default reset
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51 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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55 *******************************************************************************/
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56 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
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58 /* DMA Channelx disable */
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59 DMA_Cmd(DMA_Channelx, DISABLE);
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61 /* Reset Channelx control register */
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62 DMA_Channelx->CCR = 0;
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64 /* Reset Channelx remaining bytes register */
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65 DMA_Channelx->CNDTR = 0;
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67 /* Reset Channelx peripheral address register */
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68 DMA_Channelx->CPAR = 0;
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70 /* Reset Channelx memory address register */
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71 DMA_Channelx->CMAR = 0;
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73 switch (*(u32*)&DMA_Channelx)
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75 case DMA_Channel1_BASE:
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76 /* Reset interrupt pending bits for Channel1 */
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77 DMA->IFCR |= DMA_Channel1_IT_Mask;
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80 case DMA_Channel2_BASE:
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81 /* Reset interrupt pending bits for Channel2 */
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82 DMA->IFCR |= DMA_Channel2_IT_Mask;
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85 case DMA_Channel3_BASE:
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86 /* Reset interrupt pending bits for Channel3 */
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87 DMA->IFCR |= DMA_Channel3_IT_Mask;
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90 case DMA_Channel4_BASE:
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91 /* Reset interrupt pending bits for Channel4 */
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92 DMA->IFCR |= DMA_Channel4_IT_Mask;
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95 case DMA_Channel5_BASE:
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96 /* Reset interrupt pending bits for Channel5 */
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97 DMA->IFCR |= DMA_Channel5_IT_Mask;
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100 case DMA_Channel6_BASE:
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101 /* Reset interrupt pending bits for Channel6 */
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102 DMA->IFCR |= DMA_Channel6_IT_Mask;
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105 case DMA_Channel7_BASE:
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106 /* Reset interrupt pending bits for Channel7 */
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107 DMA->IFCR |= DMA_Channel7_IT_Mask;
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115 /*******************************************************************************
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116 * Function Name : DMA_Init
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117 * Description : Initializes the DMA Channelx according to the specified
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118 * parameters in the DMA_InitStruct.
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119 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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121 * - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
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122 * contains the configuration information for the specified
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126 ******************************************************************************/
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127 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
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131 /* Check the parameters */
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132 assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
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133 assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
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134 assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
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135 assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
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136 assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
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137 assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
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138 assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
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139 assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
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140 assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
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142 /*--------------------------- DMA Channelx CCR Configuration -----------------*/
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143 /* Get the DMA_Channelx CCR value */
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144 tmpreg = DMA_Channelx->CCR;
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145 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
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146 tmpreg &= CCR_CLEAR_Mask;
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147 /* Configure DMA Channelx: data transfer, data size, priority level and mode */
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148 /* Set DIR bit according to DMA_DIR value */
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149 /* Set CIRCULAR bit according to DMA_Mode value */
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150 /* Set PINC bit according to DMA_PeripheralInc value */
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151 /* Set MINC bit according to DMA_MemoryInc value */
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152 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
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153 /* Set MSIZE bits according to DMA_MemoryDataSize value */
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154 /* Set PL bits according to DMA_Priority value */
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155 /* Set the MEM2MEM bit according to DMA_M2M value */
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156 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
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157 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
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158 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
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159 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
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160 /* Write to DMA Channelx CCR */
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161 DMA_Channelx->CCR = tmpreg;
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163 /*--------------------------- DMA Channelx CNBTR Configuration ---------------*/
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164 /* Write to DMA Channelx CNBTR */
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165 DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
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167 /*--------------------------- DMA Channelx CPAR Configuration ----------------*/
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168 /* Write to DMA Channelx CPAR */
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169 DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
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171 /*--------------------------- DMA Channelx CMAR Configuration ----------------*/
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172 /* Write to DMA Channelx CMAR */
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173 DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
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176 /*******************************************************************************
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177 * Function Name : DMA_StructInit
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178 * Description : Fills each DMA_InitStruct member with its default value.
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179 * Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
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180 * which will be initialized.
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183 *******************************************************************************/
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184 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
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186 /*-------------- Reset DMA init structure parameters values ------------------*/
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187 /* Initialize the DMA_PeripheralBaseAddr member */
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188 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
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190 /* Initialize the DMA_MemoryBaseAddr member */
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191 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
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193 /* Initialize the DMA_DIR member */
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194 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
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196 /* Initialize the DMA_BufferSize member */
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197 DMA_InitStruct->DMA_BufferSize = 0;
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199 /* Initialize the DMA_PeripheralInc member */
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200 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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202 /* Initialize the DMA_MemoryInc member */
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203 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
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205 /* Initialize the DMA_PeripheralDataSize member */
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206 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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208 /* Initialize the DMA_MemoryDataSize member */
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209 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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211 /* Initialize the DMA_Mode member */
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212 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
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214 /* Initialize the DMA_Priority member */
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215 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
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217 /* Initialize the DMA_M2M member */
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218 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
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221 /*******************************************************************************
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222 * Function Name : DMA_Cmd
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223 * Description : Enables or disables the specified DMA Channel.
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224 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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226 * - NewState: new state of the DMAx Channel.
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227 * This parameter can be: ENABLE or DISABLE.
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230 *******************************************************************************/
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231 void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)
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233 /* Check the parameters */
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234 assert(IS_FUNCTIONAL_STATE(NewState));
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236 if (NewState != DISABLE)
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238 /* Enable the selected DMA Channelx */
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239 DMA_Channelx->CCR |= CCR_ENABLE_Set;
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243 /* Disable the selected DMA Channelx */
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244 DMA_Channelx->CCR &= CCR_ENABLE_Reset;
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248 /*******************************************************************************
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249 * Function Name : DMA_ITConfig
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250 * Description : Enables or disables the specified DMA interrupts.
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251 * Input : - DMA_IT: specifies the DMA interrupts sources to be enabled
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253 * This parameter can be any combination of the following values:
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254 * - DMA_IT_TC: Transfer complete interrupt mask
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255 * - DMA_IT_HT: Half transfer interrupt mask
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256 * - DMA_IT_TE: Transfer error interrupt mask
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257 * - NewState: new state of the specified DMA interrupts.
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258 * This parameter can be: ENABLE or DISABLE.
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261 *******************************************************************************/
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262 void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState)
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264 /* Check the parameters */
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265 assert(IS_DMA_CONFIG_IT(DMA_IT));
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266 assert(IS_FUNCTIONAL_STATE(NewState));
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268 if (NewState != DISABLE)
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270 /* Enable the selected DMA interrupts */
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271 DMA_Channelx->CCR |= DMA_IT;
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275 /* Disable the selected DMA interrupts */
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276 DMA_Channelx->CCR &= ~DMA_IT;
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280 /*******************************************************************************
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281 * Function Name : DMA_GetCurrDataCounter
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282 * Description : Returns the number of remaining data units in the current
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283 * DMA Channel transfer.
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284 * Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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287 * Return : The number of remaining data units in the current DMA Channel
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289 *******************************************************************************/
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290 u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)
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292 /* Return the current memory address value for Channelx */
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293 return ((u16)(DMA_Channelx->CNDTR));
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296 /*******************************************************************************
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297 * Function Name : DMA_GetFlagStatus
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298 * Description : Checks whether the specified DMA flag is set or not.
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299 * Input : - DMA_FLAG: specifies the flag to check.
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300 * This parameter can be one of the following values:
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301 * - DMA_FLAG_GL1: Channel1 global flag.
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302 * - DMA_FLAG_TC1: Channel1 transfer complete flag.
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303 * - DMA_FLAG_HT1: Channel1 half transfer flag.
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304 * - DMA_FLAG_TE1: Channel1 transfer error flag.
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305 * - DMA_FLAG_GL2: Channel2 global flag.
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306 * - DMA_FLAG_TC2: Channel2 transfer complete flag.
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307 * - DMA_FLAG_HT2: Channel2 half transfer flag.
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308 * - DMA_FLAG_TE2: Channel2 transfer error flag.
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309 * - DMA_FLAG_GL3: Channel3 global flag.
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310 * - DMA_FLAG_TC3: Channel3 transfer complete flag.
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311 * - DMA_FLAG_HT3: Channel3 half transfer flag.
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312 * - DMA_FLAG_TE3: Channel3 transfer error flag.
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313 * - DMA_FLAG_GL4: Channel4 global flag.
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314 * - DMA_FLAG_TC4: Channel4 transfer complete flag.
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315 * - DMA_FLAG_HT4: Channel4 half transfer flag.
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316 * - DMA_FLAG_TE4: Channel4 transfer error flag.
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317 * - DMA_FLAG_GL5: Channel5 global flag.
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318 * - DMA_FLAG_TC5: Channel5 transfer complete flag.
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319 * - DMA_FLAG_HT5: Channel5 half transfer flag.
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320 * - DMA_FLAG_TE5: Channel5 transfer error flag.
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321 * - DMA_FLAG_GL6: Channel6 global flag.
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322 * - DMA_FLAG_TC6: Channel6 transfer complete flag.
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323 * - DMA_FLAG_HT6: Channel6 half transfer flag.
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324 * - DMA_FLAG_TE6: Channel6 transfer error flag.
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325 * - DMA_FLAG_GL7: Channel7 global flag.
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326 * - DMA_FLAG_TC7: Channel7 transfer complete flag.
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327 * - DMA_FLAG_HT7: Channel7 half transfer flag.
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328 * - DMA_FLAG_TE7: Channel7 transfer error flag.
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330 * Return : The new state of DMA_FLAG (SET or RESET).
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331 *******************************************************************************/
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332 FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
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334 FlagStatus bitstatus = RESET;
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336 /* Check the parameters */
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337 assert(IS_DMA_GET_FLAG(DMA_FLAG));
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339 /* Check the status of the specified DMA flag */
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340 if ((DMA->ISR & DMA_FLAG) != (u32)RESET)
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342 /* DMA_FLAG is set */
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347 /* DMA_FLAG is reset */
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350 /* Return the DMA_FLAG status */
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354 /*******************************************************************************
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355 * Function Name : DMA_ClearFlag
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356 * Description : Clears the DMA's pending flags.
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357 * Input : - DMA_FLAG: specifies the flag to clear.
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358 * This parameter can be any combination of the following values:
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359 * - DMA_FLAG_GL1: Channel1 global flag.
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360 * - DMA_FLAG_TC1: Channel1 transfer complete flag.
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361 * - DMA_FLAG_HT1: Channel1 half transfer flag.
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362 * - DMA_FLAG_TE1: Channel1 transfer error flag.
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363 * - DMA_FLAG_GL2: Channel2 global flag.
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364 * - DMA_FLAG_TC2: Channel2 transfer complete flag.
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365 * - DMA_FLAG_HT2: Channel2 half transfer flag.
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366 * - DMA_FLAG_TE2: Channel2 transfer error flag.
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367 * - DMA_FLAG_GL3: Channel3 global flag.
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368 * - DMA_FLAG_TC3: Channel3 transfer complete flag.
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369 * - DMA_FLAG_HT3: Channel3 half transfer flag.
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370 * - DMA_FLAG_TE3: Channel3 transfer error flag.
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371 * - DMA_FLAG_GL4: Channel4 global flag.
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372 * - DMA_FLAG_TC4: Channel4 transfer complete flag.
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373 * - DMA_FLAG_HT4: Channel4 half transfer flag.
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374 * - DMA_FLAG_TE4: Channel4 transfer error flag.
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375 * - DMA_FLAG_GL5: Channel5 global flag.
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376 * - DMA_FLAG_TC5: Channel5 transfer complete flag.
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377 * - DMA_FLAG_HT5: Channel5 half transfer flag.
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378 * - DMA_FLAG_TE5: Channel5 transfer error flag.
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379 * - DMA_FLAG_GL6: Channel6 global flag.
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380 * - DMA_FLAG_TC6: Channel6 transfer complete flag.
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381 * - DMA_FLAG_HT6: Channel6 half transfer flag.
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382 * - DMA_FLAG_TE6: Channel6 transfer error flag.
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383 * - DMA_FLAG_GL7: Channel7 global flag.
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384 * - DMA_FLAG_TC7: Channel7 transfer complete flag.
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385 * - DMA_FLAG_HT7: Channel7 half transfer flag.
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386 * - DMA_FLAG_TE7: Channel7 transfer error flag.
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389 *******************************************************************************/
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390 void DMA_ClearFlag(u32 DMA_FLAG)
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392 /* Check the parameters */
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393 assert(IS_DMA_CLEAR_FLAG(DMA_FLAG));
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395 /* Clear the selected DMA flags */
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396 DMA->IFCR = DMA_FLAG;
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399 /*******************************************************************************
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400 * Function Name : DMA_GetITStatus
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401 * Description : Checks whether the specified DMA interrupt has occurred or not.
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402 * Input : - DMA_IT: specifies the DMA interrupt source to check.
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403 * This parameter can be one of the following values:
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404 * - DMA_IT_GL1: Channel1 global interrupt.
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405 * - DMA_IT_TC1: Channel1 transfer complete interrupt.
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406 * - DMA_IT_HT1: Channel1 half transfer interrupt.
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407 * - DMA_IT_TE1: Channel1 transfer error interrupt.
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408 * - DMA_IT_GL2: Channel2 global interrupt.
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409 * - DMA_IT_TC2: Channel2 transfer complete interrupt.
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410 * - DMA_IT_HT2: Channel2 half transfer interrupt.
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411 * - DMA_IT_TE2: Channel2 transfer error interrupt.
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412 * - DMA_IT_GL3: Channel3 global interrupt.
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413 * - DMA_IT_TC3: Channel3 transfer complete interrupt.
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414 * - DMA_IT_HT3: Channel3 half transfer interrupt.
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415 * - DMA_IT_TE3: Channel3 transfer error interrupt.
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416 * - DMA_IT_GL4: Channel4 global interrupt.
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417 * - DMA_IT_TC4: Channel4 transfer complete interrupt.
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418 * - DMA_IT_HT4: Channel4 half transfer interrupt.
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419 * - DMA_IT_TE4: Channel4 transfer error interrupt.
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420 * - DMA_IT_GL5: Channel5 global interrupt.
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421 * - DMA_IT_TC5: Channel5 transfer complete interrupt.
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422 * - DMA_IT_HT5: Channel5 half transfer interrupt.
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423 * - DMA_IT_TE5: Channel5 transfer error interrupt.
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424 * - DMA_IT_GL6: Channel6 global interrupt.
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425 * - DMA_IT_TC6: Channel6 transfer complete interrupt.
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426 * - DMA_IT_HT6: Channel6 half transfer interrupt.
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427 * - DMA_IT_TE6: Channel6 transfer error interrupt.
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428 * - DMA_IT_GL7: Channel7 global interrupt.
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429 * - DMA_IT_TC7: Channel7 transfer complete interrupt.
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430 * - DMA_IT_HT7: Channel7 half transfer interrupt.
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431 * - DMA_IT_TE7: Channel7 transfer error interrupt.
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433 * Return : The new state of DMA_IT (SET or RESET).
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434 *******************************************************************************/
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435 ITStatus DMA_GetITStatus(u32 DMA_IT)
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437 ITStatus bitstatus = RESET;
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439 /* Check the parameters */
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440 assert(IS_DMA_GET_IT(DMA_IT));
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442 /* Check the status of the specified DMA interrupt */
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443 if ((DMA->ISR & DMA_IT) != (u32)RESET)
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445 /* DMA_IT is set */
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450 /* DMA_IT is reset */
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453 /* Return the DMA_IT status */
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457 /*******************************************************************************
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458 * Function Name : DMA_ClearITPendingBit
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459 * Description : Clears the DMA
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460 * Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
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461 * This parameter can be any combination of the following values:
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462 * - DMA_IT_GL1: Channel1 global interrupt.
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463 * - DMA_IT_TC1: Channel1 transfer complete interrupt.
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464 * - DMA_IT_HT1: Channel1 half transfer interrupt.
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465 * - DMA_IT_TE1: Channel1 transfer error interrupt.
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466 * - DMA_IT_GL2: Channel2 global interrupt.
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467 * - DMA_IT_TC2: Channel2 transfer complete interrupt.
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468 * - DMA_IT_HT2: Channel2 half transfer interrupt.
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469 * - DMA_IT_TE2: Channel2 transfer error interrupt.
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470 * - DMA_IT_GL3: Channel3 global interrupt.
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471 * - DMA_IT_TC3: Channel3 transfer complete interrupt.
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472 * - DMA_IT_HT3: Channel3 half transfer interrupt.
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473 * - DMA_IT_TE3: Channel3 transfer error interrupt.
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474 * - DMA_IT_GL4: Channel4 global interrupt.
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475 * - DMA_IT_TC4: Channel4 transfer complete interrupt.
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476 * - DMA_IT_HT4: Channel4 half transfer interrupt.
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477 * - DMA_IT_TE4: Channel4 transfer error interrupt.
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478 * - DMA_IT_GL5: Channel5 global interrupt.
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479 * - DMA_IT_TC5: Channel5 transfer complete interrupt.
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480 * - DMA_IT_HT5: Channel5 half transfer interrupt.
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481 * - DMA_IT_TE5: Channel5 transfer error interrupt.
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482 * - DMA_IT_GL6: Channel6 global interrupt.
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483 * - DMA_IT_TC6: Channel6 transfer complete interrupt.
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484 * - DMA_IT_HT6: Channel6 half transfer interrupt.
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485 * - DMA_IT_TE6: Channel6 transfer error interrupt.
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486 * - DMA_IT_GL7: Channel7 global interrupt.
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487 * - DMA_IT_TC7: Channel7 transfer complete interrupt.
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488 * - DMA_IT_HT7: Channel7 half transfer interrupt.
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489 * - DMA_IT_TE7: Channel7 transfer error interrupt.
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492 *******************************************************************************/
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493 void DMA_ClearITPendingBit(u32 DMA_IT)
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495 /* Check the parameters */
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496 assert(IS_DMA_CLEAR_IT(DMA_IT));
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498 /* Clear the selected DMA interrupt pending bits */
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499 DMA->IFCR = DMA_IT;
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502 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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