git.sur5r.net Git - freertos/blob - Demo/Common/drivers/ST/STM32F10xFWLib/src/stm32f10x_fsmc.c

   1 /**\r
   2   ******************************************************************************\r
   3   * @file  stm32f10x_fsmc.c\r
   4   * @author  MCD Application Team\r
   5   * @version  V3.0.0\r
   6   * @date  04/06/2009\r
   7   * @brief  This file provides all the FSMC firmware functions.\r
   8   ******************************************************************************\r
   9   * @copy\r
  10   *\r
  11   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  12   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
  13   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
  14   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
  15   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
  16   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  17   *\r
  18   * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>\r
  19   */ \r
  20 \r
  21 /* Includes ------------------------------------------------------------------*/\r
  22 #include "stm32f10x_fsmc.h"\r
  23 #include "stm32f10x_rcc.h"\r
  24 \r
  25 /** @addtogroup StdPeriph_Driver\r
  26   * @{\r
  27   */\r
  28 \r
  29 /** @defgroup FSMC \r
  30   * @brief FSMC driver modules\r
  31   * @{\r
  32   */ \r
  33 \r
  34 /** @defgroup FSMC_Private_TypesDefinitions\r
  35   * @{\r
  36   */ \r
  37 /**\r
  38   * @}\r
  39   */\r
  40 \r
  41 /** @defgroup FSMC_Private_Defines\r
  42   * @{\r
  43   */\r
  44 \r
  45 /* --------------------- FSMC registers bit mask ---------------------------- */\r
  46 \r
  47 /* FSMC BCRx Mask */\r
  48 #define BCR_MBKEN_Set                       ((uint32_t)0x00000001)\r
  49 #define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)\r
  50 #define BCR_FACCEN_Set                      ((uint32_t)0x00000040)\r
  51 \r
  52 /* FSMC PCRx Mask */\r
  53 #define PCR_PBKEN_Set                       ((uint32_t)0x00000004)\r
  54 #define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)\r
  55 #define PCR_ECCEN_Set                       ((uint32_t)0x00000040)\r
  56 #define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)\r
  57 #define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)\r
  58 /**\r
  59   * @}\r
  60   */\r
  61 \r
  62 /** @defgroup FSMC_Private_Macros\r
  63   * @{\r
  64   */\r
  65 \r
  66 /**\r
  67   * @}\r
  68   */\r
  69 \r
  70 /** @defgroup FSMC_Private_Variables\r
  71   * @{\r
  72   */\r
  73 \r
  74 /**\r
  75   * @}\r
  76   */\r
  77 \r
  78 /** @defgroup FSMC_Private_FunctionPrototypes\r
  79   * @{\r
  80   */\r
  81 \r
  82 /**\r
  83   * @}\r
  84   */\r
  85 \r
  86 /** @defgroup FSMC_Private_Functions\r
  87   * @{\r
  88   */\r
  89 \r
  90 /**\r
  91   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
  92   *   reset values.\r
  93   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
  94   *   This parameter can be one of the following values:\r
  95   * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
  96   * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
  97   * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
  98   * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
  99   * @retval : None\r
 100   */\r
 101 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
 102 {\r
 103   /* Check the parameter */\r
 104   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 105   \r
 106   /* FSMC_Bank1_NORSRAM1 */\r
 107   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
 108   {\r
 109     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    \r
 110   }\r
 111   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
 112   else\r
 113   {   \r
 114     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
 115   }\r
 116   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
 117   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  \r
 118 }\r
 119 \r
 120 /**\r
 121   * @brief  Deinitializes the FSMC NAND Banks registers to their default \r
 122   *   reset values.\r
 123   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 124   *   This parameter can be one of the following values:\r
 125   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 126   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
 127   * @retval : None\r
 128   */\r
 129 void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
 130 {\r
 131   /* Check the parameter */\r
 132   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 133   \r
 134   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 135   {\r
 136     /* Set the FSMC_Bank2 registers to their reset values */\r
 137     FSMC_Bank2->PCR2 = 0x00000018;\r
 138     FSMC_Bank2->SR2 = 0x00000040;\r
 139     FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
 140     FSMC_Bank2->PATT2 = 0xFCFCFCFC;  \r
 141   }\r
 142   /* FSMC_Bank3_NAND */  \r
 143   else\r
 144   {\r
 145     /* Set the FSMC_Bank3 registers to their reset values */\r
 146     FSMC_Bank3->PCR3 = 0x00000018;\r
 147     FSMC_Bank3->SR3 = 0x00000040;\r
 148     FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
 149     FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
 150   }  \r
 151 }\r
 152 \r
 153 /**\r
 154   * @brief  Deinitializes the FSMC PCCARD Bank registers to their default \r
 155   *   reset values.\r
 156   * @param  None                       \r
 157   * @retval : None\r
 158   */\r
 159 void FSMC_PCCARDDeInit(void)\r
 160 {\r
 161   /* Set the FSMC_Bank4 registers to their reset values */\r
 162   FSMC_Bank4->PCR4 = 0x00000018; \r
 163   FSMC_Bank4->SR4 = 0x00000000; \r
 164   FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
 165   FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
 166   FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
 167 }\r
 168 \r
 169 /**\r
 170   * @brief  Initializes the FSMC NOR/SRAM Banks according to the \r
 171   *   specified parameters in the FSMC_NORSRAMInitStruct.\r
 172   * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
 173   *   structure that contains the configuration information for \r
 174   *   the FSMC NOR/SRAM specified Banks.                       \r
 175   * @retval : None\r
 176   */\r
 177 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 178 { \r
 179   /* Check the parameters */\r
 180   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
 181   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
 182   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
 183   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
 184   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
 185   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
 186   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
 187   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
 188   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
 189   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
 190   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
 191   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  \r
 192   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
 193   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
 194   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
 195   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
 196   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
 197   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
 198   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
 199   \r
 200   /* Bank1 NOR/SRAM control register configuration */ \r
 201   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 202             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
 203             FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
 204             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
 205             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
 206             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
 207             FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
 208             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
 209             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
 210             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
 211             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
 212             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
 213   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
 214   {\r
 215     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
 216   }\r
 217   /* Bank1 NOR/SRAM timing register configuration */\r
 218   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
 219             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
 220             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
 221             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 222             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
 223             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
 224             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
 225              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
 226             \r
 227     \r
 228   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
 229   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
 230   {\r
 231     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
 232     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
 233     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
 234     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
 235     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
 236     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
 237     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 238               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
 239               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
 240               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 241               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
 242               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
 243                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
 244   }\r
 245   else\r
 246   {\r
 247     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
 248   }\r
 249 }\r
 250 \r
 251 /**\r
 252   * @brief  Initializes the FSMC NAND Banks according to the specified \r
 253   *   parameters in the FSMC_NANDInitStruct.\r
 254   * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
 255   *   structure that contains the configuration information for \r
 256   *   the FSMC NAND specified Banks.                       \r
 257   * @retval : None\r
 258   */\r
 259 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
 260 {\r
 261   uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
 262     \r
 263   /* Check the parameters */\r
 264   assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
 265   assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
 266   assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
 267   assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
 268   assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
 269   assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
 270   assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
 271   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
 272   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
 273   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
 274   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
 275   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
 276   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
 277   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
 278   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
 279   \r
 280   /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
 281   tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
 282             PCR_MemoryType_NAND |\r
 283             FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
 284             FSMC_NANDInitStruct->FSMC_ECC |\r
 285             FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
 286             (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
 287             (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
 288             \r
 289   /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
 290   tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
 291             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 292             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 293             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
 294             \r
 295   /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
 296   tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
 297             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 298             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 299             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
 300   \r
 301   if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
 302   {\r
 303     /* FSMC_Bank2_NAND registers configuration */\r
 304     FSMC_Bank2->PCR2 = tmppcr;\r
 305     FSMC_Bank2->PMEM2 = tmppmem;\r
 306     FSMC_Bank2->PATT2 = tmppatt;\r
 307   }\r
 308   else\r
 309   {\r
 310     /* FSMC_Bank3_NAND registers configuration */\r
 311     FSMC_Bank3->PCR3 = tmppcr;\r
 312     FSMC_Bank3->PMEM3 = tmppmem;\r
 313     FSMC_Bank3->PATT3 = tmppatt;\r
 314   }\r
 315 }\r
 316 \r
 317 /**\r
 318   * @brief  Initializes the FSMC PCCARD Bank according to the specified \r
 319   *   parameters in the FSMC_PCCARDInitStruct.\r
 320   * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
 321   *   structure that contains the configuration information for \r
 322   *   the FSMC PCCARD Bank.                       \r
 323   * @retval : None\r
 324   */\r
 325 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
 326 {\r
 327   /* Check the parameters */\r
 328   assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
 329   assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
 330   assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
 331  \r
 332   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
 333   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
 334   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
 335   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
 336   \r
 337   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
 338   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
 339   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
 340   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
 341   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
 342   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
 343   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
 344   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
 345   \r
 346   /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
 347   FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
 348                      FSMC_MemoryDataWidth_16b |  \r
 349                      (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
 350                      (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
 351             \r
 352   /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
 353   FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
 354                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 355                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 356                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
 357             \r
 358   /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
 359   FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
 360                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 361                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 362                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);        \r
 363             \r
 364   /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
 365   FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
 366                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 367                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 368                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             \r
 369 }\r
 370 \r
 371 /**\r
 372   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.\r
 373   * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
 374   *   structure which will be initialized.\r
 375   * @retval : None\r
 376   */\r
 377 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 378 {  \r
 379   /* Reset NOR/SRAM Init structure parameters values */\r
 380   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
 381   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
 382   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
 383   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 384   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
 385   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
 386   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
 387   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
 388   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
 389   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
 390   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
 391   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
 392   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 393   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 394   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 395   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 396   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 397   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
 398   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
 399   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 400   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 401   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 402   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 403   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 404   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
 405   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
 406 }\r
 407 \r
 408 /**\r
 409   * @brief  Fills each FSMC_NANDInitStruct member with its default value.\r
 410   * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
 411   *   structure which will be initialized.\r
 412   * @retval : None\r
 413   */\r
 414 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
 415 { \r
 416   /* Reset NAND Init structure parameters values */\r
 417   FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
 418   FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
 419   FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 420   FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
 421   FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
 422   FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
 423   FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
 424   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 425   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 426   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 427   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 428   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 429   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 430   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 431   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;         \r
 432 }\r
 433 \r
 434 /**\r
 435   * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.\r
 436   * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
 437   *   structure which will be initialized.\r
 438   * @retval : None\r
 439   */\r
 440 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
 441 {\r
 442   /* Reset PCCARD Init structure parameters values */\r
 443   FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
 444   FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
 445   FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
 446   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 447   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 448   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 449   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 450   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 451   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 452   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 453   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;     \r
 454   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 455   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 456   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 457   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 458 }\r
 459 \r
 460 /**\r
 461   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.\r
 462   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 463   *   This parameter can be one of the following values:\r
 464   * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
 465   * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
 466   * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
 467   * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
 468   * @param NewState: new state of the FSMC_Bank.\r
 469   *   This parameter can be: ENABLE or DISABLE.\r
 470   * @retval : None\r
 471   */\r
 472 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 473 {\r
 474   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 475   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 476   \r
 477   if (NewState != DISABLE)\r
 478   {\r
 479     /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
 480     FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
 481   }\r
 482   else\r
 483   {\r
 484     /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
 485     FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
 486   }\r
 487 }\r
 488 \r
 489 /**\r
 490   * @brief  Enables or disables the specified NAND Memory Bank.\r
 491   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 492   *   This parameter can be one of the following values:\r
 493   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 494   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 495   * @param NewState: new state of the FSMC_Bank.\r
 496   *   This parameter can be: ENABLE or DISABLE.\r
 497   * @retval : None\r
 498   */\r
 499 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 500 {\r
 501   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 502   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 503   \r
 504   if (NewState != DISABLE)\r
 505   {\r
 506     /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
 507     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 508     {\r
 509       FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
 510     }\r
 511     else\r
 512     {\r
 513       FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
 514     }\r
 515   }\r
 516   else\r
 517   {\r
 518     /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
 519     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 520     {\r
 521       FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
 522     }\r
 523     else\r
 524     {\r
 525       FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
 526     }\r
 527   }\r
 528 }\r
 529 \r
 530 /**\r
 531   * @brief  Enables or disables the PCCARD Memory Bank.\r
 532   * @param NewState: new state of the PCCARD Memory Bank.  \r
 533   *   This parameter can be: ENABLE or DISABLE.\r
 534   * @retval : None\r
 535   */\r
 536 void FSMC_PCCARDCmd(FunctionalState NewState)\r
 537 {\r
 538   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 539   \r
 540   if (NewState != DISABLE)\r
 541   {\r
 542     /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
 543     FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
 544   }\r
 545   else\r
 546   {\r
 547     /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
 548     FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
 549   }\r
 550 }\r
 551 \r
 552 /**\r
 553   * @brief  Enables or disables the FSMC NAND ECC feature.\r
 554   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 555   *   This parameter can be one of the following values:\r
 556   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 557   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 558   * @param NewState: new state of the FSMC NAND ECC feature.  \r
 559   *   This parameter can be: ENABLE or DISABLE.\r
 560   * @retval : None\r
 561   */\r
 562 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 563 {\r
 564   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 565   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 566   \r
 567   if (NewState != DISABLE)\r
 568   {\r
 569     /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
 570     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 571     {\r
 572       FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
 573     }\r
 574     else\r
 575     {\r
 576       FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
 577     }\r
 578   }\r
 579   else\r
 580   {\r
 581     /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
 582     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 583     {\r
 584       FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
 585     }\r
 586     else\r
 587     {\r
 588       FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
 589     }\r
 590   }\r
 591 }\r
 592 \r
 593 /**\r
 594   * @brief  Returns the error correction code register value.\r
 595   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 596   *   This parameter can be one of the following values:\r
 597   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 598   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 599   * @retval : The Error Correction Code (ECC) value.\r
 600   */\r
 601 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
 602 {\r
 603   uint32_t eccval = 0x00000000;\r
 604   \r
 605   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 606   {\r
 607     /* Get the ECCR2 register value */\r
 608     eccval = FSMC_Bank2->ECCR2;\r
 609   }\r
 610   else\r
 611   {\r
 612     /* Get the ECCR3 register value */\r
 613     eccval = FSMC_Bank3->ECCR3;\r
 614   }\r
 615   /* Return the error correction code value */\r
 616   return(eccval);\r
 617 }\r
 618 \r
 619 /**\r
 620   * @brief  Enables or disables the specified FSMC interrupts.\r
 621   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 622   *   This parameter can be one of the following values:\r
 623   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 624   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 625   * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 626   * @param FSMC_IT: specifies the FSMC interrupt sources to be\r
 627   *   enabled or disabled.\r
 628   *   This parameter can be any combination of the following values:\r
 629   * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 630   * @arg FSMC_IT_Level: Level edge detection interrupt.\r
 631   * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
 632   * @param NewState: new state of the specified FSMC interrupts.\r
 633   *   This parameter can be: ENABLE or DISABLE.\r
 634   * @retval : None\r
 635   */\r
 636 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
 637 {\r
 638   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 639   assert_param(IS_FSMC_IT(FSMC_IT));    \r
 640   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 641   \r
 642   if (NewState != DISABLE)\r
 643   {\r
 644     /* Enable the selected FSMC_Bank2 interrupts */\r
 645     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 646     {\r
 647       FSMC_Bank2->SR2 |= FSMC_IT;\r
 648     }\r
 649     /* Enable the selected FSMC_Bank3 interrupts */\r
 650     else if (FSMC_Bank == FSMC_Bank3_NAND)\r
 651     {\r
 652       FSMC_Bank3->SR3 |= FSMC_IT;\r
 653     }\r
 654     /* Enable the selected FSMC_Bank4 interrupts */\r
 655     else\r
 656     {\r
 657       FSMC_Bank4->SR4 |= FSMC_IT;    \r
 658     }\r
 659   }\r
 660   else\r
 661   {\r
 662     /* Disable the selected FSMC_Bank2 interrupts */\r
 663     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 664     {\r
 665       \r
 666       FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
 667     }\r
 668     /* Disable the selected FSMC_Bank3 interrupts */\r
 669     else if (FSMC_Bank == FSMC_Bank3_NAND)\r
 670     {\r
 671       FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
 672     }\r
 673     /* Disable the selected FSMC_Bank4 interrupts */\r
 674     else\r
 675     {\r
 676       FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    \r
 677     }\r
 678   }\r
 679 }\r
 680 \r
 681 /**\r
 682   * @brief  Checks whether the specified FSMC flag is set or not.\r
 683   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 684   *   This parameter can be one of the following values:\r
 685   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 686   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 687   * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 688   * @param FSMC_FLAG: specifies the flag to check.\r
 689   *   This parameter can be one of the following values:\r
 690   * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
 691   * @arg FSMC_FLAG_Level: Level detection Flag.\r
 692   * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
 693   * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
 694   * @retval : The new state of FSMC_FLAG (SET or RESET).\r
 695   */\r
 696 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
 697 {\r
 698   FlagStatus bitstatus = RESET;\r
 699   uint32_t tmpsr = 0x00000000;\r
 700   \r
 701   /* Check the parameters */\r
 702   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
 703   assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
 704   \r
 705   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 706   {\r
 707     tmpsr = FSMC_Bank2->SR2;\r
 708   }  \r
 709   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 710   {\r
 711     tmpsr = FSMC_Bank3->SR3;\r
 712   }\r
 713   /* FSMC_Bank4_PCCARD*/\r
 714   else\r
 715   {\r
 716     tmpsr = FSMC_Bank4->SR4;\r
 717   } \r
 718   \r
 719   /* Get the flag status */\r
 720   if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
 721   {\r
 722     bitstatus = SET;\r
 723   }\r
 724   else\r
 725   {\r
 726     bitstatus = RESET;\r
 727   }\r
 728   /* Return the flag status */\r
 729   return bitstatus;\r
 730 }\r
 731 \r
 732 /**\r
 733   * @brief  Clears the FSMC\92s pending flags.\r
 734   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 735   *   This parameter can be one of the following values:\r
 736   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 737   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 738   * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 739   * @param FSMC_FLAG: specifies the flag to clear.\r
 740   *   This parameter can be any combination of the following values:\r
 741   * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
 742   * @arg FSMC_FLAG_Level: Level detection Flag.\r
 743   * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
 744   * @retval : None\r
 745   */\r
 746 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
 747 {\r
 748  /* Check the parameters */\r
 749   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
 750   assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
 751     \r
 752   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 753   {\r
 754     FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
 755   }  \r
 756   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 757   {\r
 758     FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
 759   }\r
 760   /* FSMC_Bank4_PCCARD*/\r
 761   else\r
 762   {\r
 763     FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
 764   }\r
 765 }\r
 766 \r
 767 /**\r
 768   * @brief  Checks whether the specified FSMC interrupt has occurred or not.\r
 769   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 770   *   This parameter can be one of the following values:\r
 771   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 772   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 773   * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 774   * @param FSMC_IT: specifies the FSMC interrupt source to check.\r
 775   *   This parameter can be one of the following values:\r
 776   * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 777   * @arg FSMC_IT_Level: Level edge detection interrupt.\r
 778   * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
 779   * @retval : The new state of FSMC_IT (SET or RESET).\r
 780   */\r
 781 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
 782 {\r
 783   ITStatus bitstatus = RESET;\r
 784   uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
 785   \r
 786   /* Check the parameters */\r
 787   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 788   assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
 789   \r
 790   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 791   {\r
 792     tmpsr = FSMC_Bank2->SR2;\r
 793   }  \r
 794   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 795   {\r
 796     tmpsr = FSMC_Bank3->SR3;\r
 797   }\r
 798   /* FSMC_Bank4_PCCARD*/\r
 799   else\r
 800   {\r
 801     tmpsr = FSMC_Bank4->SR4;\r
 802   } \r
 803   \r
 804   itstatus = tmpsr & FSMC_IT;\r
 805   \r
 806   itenable = tmpsr & (FSMC_IT >> 3);\r
 807   if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))\r
 808   {\r
 809     bitstatus = SET;\r
 810   }\r
 811   else\r
 812   {\r
 813     bitstatus = RESET;\r
 814   }\r
 815   return bitstatus; \r
 816 }\r
 817 \r
 818 /**\r
 819   * @brief  Clears the FSMC\92s interrupt pending bits.\r
 820   * @param FSMC_Bank: specifies the FSMC Bank to be used\r
 821   *   This parameter can be one of the following values:\r
 822   * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 823   * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 824   * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 825   * @param FSMC_IT: specifies the interrupt pending bit to clear.\r
 826   *   This parameter can be any combination of the following values:\r
 827   * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 828   * @arg FSMC_IT_Level: Level edge detection interrupt.\r
 829   * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
 830   * @retval : None\r
 831   */\r
 832 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
 833 {\r
 834   /* Check the parameters */\r
 835   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 836   assert_param(IS_FSMC_IT(FSMC_IT));\r
 837     \r
 838   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 839   {\r
 840     FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
 841   }  \r
 842   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 843   {\r
 844     FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
 845   }\r
 846   /* FSMC_Bank4_PCCARD*/\r
 847   else\r
 848   {\r
 849     FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
 850   }\r
 851 }\r
 852 \r
 853 /**\r
 854   * @}\r
 855   */ \r
 856 \r
 857 /**\r
 858   * @}\r
 859   */\r
 860 \r
 861 /**\r
 862   * @}\r
 863   */\r
 864 \r
 865 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r