1 /******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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2 * File Name : stm32f10x_rcc.c
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3 * Author : MCD Application Team
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4 * Date First Issued : 09/29/2006
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5 * Description : This file provides all the RCC firmware functions.
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6 ********************************************************************************
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11 ********************************************************************************
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12 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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14 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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15 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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16 * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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17 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 *******************************************************************************/
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20 /* Includes ------------------------------------------------------------------*/
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21 #include "stm32f10x_rcc.h"
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23 /* Private typedef -----------------------------------------------------------*/
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24 /* Private define ------------------------------------------------------------*/
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25 /* ------------ RCC registers bit address in the alias region ----------- */
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26 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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28 /* --- CR Register ---*/
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29 /* Alias word address of HSION bit */
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30 #define CR_OFFSET (RCC_OFFSET + 0x00)
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31 #define HSION_BitNumber 0x00
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32 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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34 /* Alias word address of PLLON bit */
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35 #define PLLON_BitNumber 0x18
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36 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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38 /* Alias word address of CSSON bit */
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39 #define CSSON_BitNumber 0x13
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40 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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42 /* --- CFGR Register ---*/
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43 /* Alias word address of USBPRE bit */
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44 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
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45 #define USBPRE_BitNumber 0x16
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46 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
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48 /* --- BDCR Register ---*/
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49 /* Alias word address of RTCEN bit */
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50 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
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51 #define RTCEN_BitNumber 0x0F
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52 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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54 /* Alias word address of BDRST bit */
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55 #define BDRST_BitNumber 0x10
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56 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
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58 /* --- CSR Register ---*/
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59 /* Alias word address of LSION bit */
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60 #define CSR_OFFSET (RCC_OFFSET + 0x24)
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61 #define LSION_BitNumber 0x00
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62 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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64 /* ---------------------- RCC registers bit mask ------------------------ */
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65 /* CR register bit mask */
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66 #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
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67 #define CR_HSEBYP_Set ((u32)0x00040000)
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68 #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
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69 #define CR_HSEON_Set ((u32)0x00010000)
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70 #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
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72 /* CFGR register bit mask */
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73 #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
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74 #define CFGR_PLLMull_Mask ((u32)0x003C0000)
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75 #define CFGR_PLLSRC_Mask ((u32)0x00010000)
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76 #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
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77 #define CFGR_SWS_Mask ((u32)0x0000000C)
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78 #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
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79 #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
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80 #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
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81 #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
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82 #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
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83 #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
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84 #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
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85 #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
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86 #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
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88 /* CSR register bit mask */
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89 #define CSR_RVMF_Set ((u32)0x01000000)
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92 #define FLAG_Mask ((u8)0x1F)
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94 /* Typical Value of the HSI in Hz */
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95 #define HSI_Value ((u32)8000000)
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97 /* BDCR register base address */
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98 #define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET)
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100 /* Private macro -------------------------------------------------------------*/
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101 /* Private variables ---------------------------------------------------------*/
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102 static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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103 static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
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105 /* Private function prototypes -----------------------------------------------*/
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106 /* Private functions ---------------------------------------------------------*/
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108 /*******************************************************************************
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109 * Function Name : RCC_DeInit
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110 * Description : Deinitializes the RCC peripheral registers to their default
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112 * - The HSITRIM[4:0] bits in RCC_CR register are not modified
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113 * by this function.
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114 * - The RCC_BDCR and RCC_CSR registers are not reset by this
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119 *******************************************************************************/
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120 void RCC_DeInit(void)
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122 /* Disable APB2 Peripheral Reset */
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123 RCC->APB2RSTR = 0x00000000;
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125 /* Disable APB1 Peripheral Reset */
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126 RCC->APB1RSTR = 0x00000000;
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128 /* FLITF and SRAM Clock ON */
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129 RCC->AHBENR = 0x00000014;
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131 /* Disable APB2 Peripheral Clock */
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132 RCC->APB2ENR = 0x00000000;
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134 /* Disable APB1 Peripheral Clock */
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135 RCC->APB1ENR = 0x00000000;
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137 /* Set HSION bit */
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138 RCC->CR |= (u32)0x00000001;
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140 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
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141 RCC->CFGR &= 0xF8FF0000;
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143 /* Reset HSEON, CSSON and PLLON bits */
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144 RCC->CR &= 0xFEF6FFFF;
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146 /* Reset HSEBYP bit */
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147 RCC->CR &= 0xFFFBFFFF;
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149 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
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150 RCC->CFGR &= 0xFF80FFFF;
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152 /* Disable all interrupts */
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153 RCC->CIR = 0x00000000;
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156 /*******************************************************************************
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157 * Function Name : RCC_HSEConfig
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158 * Description : Configures the External High Speed oscillator (HSE).
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159 * Input : - RCC_HSE: specifies the new state of the HSE.
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160 * This parameter can be one of the following values:
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161 * - RCC_HSE_OFF: HSE oscillator OFF
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162 * - RCC_HSE_ON: HSE oscillator ON
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163 * - RCC_HSE_Bypass: HSE oscillator bypassed with external
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167 *******************************************************************************/
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168 void RCC_HSEConfig(u32 RCC_HSE)
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170 /* Check the parameters */
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171 assert(IS_RCC_HSE(RCC_HSE));
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173 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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174 /* Reset HSEON bit */
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175 RCC->CR &= CR_HSEON_Reset;
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177 /* Reset HSEBYP bit */
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178 RCC->CR &= CR_HSEBYP_Reset;
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180 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
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184 /* Set HSEON bit */
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185 RCC->CR |= CR_HSEON_Set;
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188 case RCC_HSE_Bypass:
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189 /* Set HSEBYP and HSEON bits */
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190 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
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198 /*******************************************************************************
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199 * Function Name : RCC_AdjustHSICalibrationValue
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200 * Description : Adjusts the Internal High Speed oscillator (HSI) calibration
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202 * Input : - HSICalibrationValue: specifies the calibration trimming value.
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203 * This parameter must be a number between 0 and 0x1F.
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206 *******************************************************************************/
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207 void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
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211 /* Check the parameters */
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212 assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
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216 /* Clear HSITRIM[7:3] bits */
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217 tmpreg &= CR_HSITRIM_Mask;
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219 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
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220 tmpreg |= (u32)HSICalibrationValue << 3;
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222 /* Store the new value */
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226 /*******************************************************************************
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227 * Function Name : RCC_HSICmd
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228 * Description : Enables or disables the Internal High Speed oscillator (HSI).
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229 * HSI can not be stopped if it is used directly or through the
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230 * PLL as system clock, or if a Flash programmation is on going.
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231 * Input : - NewState: new state of the HSI.
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232 * This parameter can be: ENABLE or DISABLE.
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235 *******************************************************************************/
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236 void RCC_HSICmd(FunctionalState NewState)
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238 /* Check the parameters */
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239 assert(IS_FUNCTIONAL_STATE(NewState));
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241 *(vu32 *) CR_HSION_BB = (u32)NewState;
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244 /*******************************************************************************
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245 * Function Name : RCC_PLLConfig
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246 * Description : Configures the PLL clock source and multiplication factor.
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247 * This function must be used only when the PLL is disabled.
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248 * Input : - RCC_PLLSource: specifies the PLL entry clock source.
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249 * This parameter can be one of the following values:
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250 * - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
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251 * by 2 selected as PLL clock entry
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252 * - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
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253 * as PLL clock entry
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254 * - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
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255 * by 2 selected as PLL clock entry
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256 * - RCC_PLLMul: specifies the PLL multiplication factor.
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257 * This parameter can be RCC_PLLMul_x where x:[2,16]
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260 *******************************************************************************/
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261 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
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265 /* Check the parameters */
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266 assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));
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267 assert(IS_RCC_PLL_MUL(RCC_PLLMul));
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269 tmpreg = RCC->CFGR;
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271 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
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272 tmpreg &= CFGR_PLL_Mask;
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274 /* Set the PLL configuration bits */
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275 tmpreg |= RCC_PLLSource | RCC_PLLMul;
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277 /* Store the new value */
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278 RCC->CFGR = tmpreg;
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281 /*******************************************************************************
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282 * Function Name : RCC_PLLCmd
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283 * Description : Enables or disables the PLL.
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284 * The PLL can not be disabled if it is used as system clock.
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285 * Input : - NewState: new state of the PLL.
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286 * This parameter can be: ENABLE or DISABLE.
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289 *******************************************************************************/
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290 void RCC_PLLCmd(FunctionalState NewState)
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292 /* Check the parameters */
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293 assert(IS_FUNCTIONAL_STATE(NewState));
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295 *(vu32 *) CR_PLLON_BB = (u32)NewState;
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298 /*******************************************************************************
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299 * Function Name : RCC_SYSCLKConfig
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300 * Description : Configures the system clock (SYSCLK).
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301 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
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302 * clock. This parameter can be one of the following values:
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303 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
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304 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
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305 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
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308 *******************************************************************************/
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309 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
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313 /* Check the parameters */
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314 assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
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316 tmpreg = RCC->CFGR;
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318 /* Clear SW[1:0] bits */
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319 tmpreg &= CFGR_SW_Mask;
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321 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
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322 tmpreg |= RCC_SYSCLKSource;
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324 /* Store the new value */
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325 RCC->CFGR = tmpreg;
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328 /*******************************************************************************
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329 * Function Name : RCC_GetSYSCLKSource
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330 * Description : Returns the clock source used as system clock.
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333 * Return : The clock source used as system clock. The returned value can
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334 * be one of the following:
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335 * - 0x00: HSI used as system clock
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336 * - 0x04: HSE used as system clock
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337 * - 0x08: PLL used as system clock
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338 *******************************************************************************/
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339 u8 RCC_GetSYSCLKSource(void)
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341 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
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344 /*******************************************************************************
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345 * Function Name : RCC_HCLKConfig
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346 * Description : Configures the AHB clock (HCLK).
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347 * Input : - RCC_HCLK: defines the AHB clock. This clock is derived
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348 * from the system clock (SYSCLK).
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349 * This parameter can be one of the following values:
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350 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
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351 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
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352 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
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353 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
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354 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
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355 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
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356 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
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357 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
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358 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
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361 *******************************************************************************/
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362 void RCC_HCLKConfig(u32 RCC_HCLK)
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366 /* Check the parameters */
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367 assert(IS_RCC_HCLK(RCC_HCLK));
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369 tmpreg = RCC->CFGR;
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371 /* Clear HPRE[7:4] bits */
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372 tmpreg &= CFGR_HPRE_Reset_Mask;
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374 /* Set HPRE[7:4] bits according to RCC_HCLK value */
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375 tmpreg |= RCC_HCLK;
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377 /* Store the new value */
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378 RCC->CFGR = tmpreg;
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381 /*******************************************************************************
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382 * Function Name : RCC_PCLK1Config
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383 * Description : Configures the Low Speed APB clock (PCLK1).
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384 * Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived
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385 * from the AHB clock (HCLK).
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386 * This parameter can be one of the following values:
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387 * - RCC_HCLK_Div1: APB1 clock = HCLK
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388 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
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389 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
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390 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
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391 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
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394 *******************************************************************************/
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395 void RCC_PCLK1Config(u32 RCC_PCLK1)
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399 /* Check the parameters */
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400 assert(IS_RCC_PCLK(RCC_PCLK1));
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402 tmpreg = RCC->CFGR;
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404 /* Clear PPRE1[10:8] bits */
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405 tmpreg &= CFGR_PPRE1_Reset_Mask;
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407 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
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408 tmpreg |= RCC_PCLK1;
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410 /* Store the new value */
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411 RCC->CFGR = tmpreg;
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414 /*******************************************************************************
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415 * Function Name : RCC_PCLK2Config
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416 * Description : Configures the High Speed APB clock (PCLK2).
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417 * Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived
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418 * from the AHB clock (HCLK).
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419 * This parameter can be one of the following values:
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420 * - RCC_HCLK_Div1: APB2 clock = HCLK
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421 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
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422 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
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423 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
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424 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
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427 *******************************************************************************/
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428 void RCC_PCLK2Config(u32 RCC_PCLK2)
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432 /* Check the parameters */
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433 assert(IS_RCC_PCLK(RCC_PCLK2));
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435 tmpreg = RCC->CFGR;
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437 /* Clear PPRE2[13:11] bits */
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438 tmpreg &= CFGR_PPRE2_Reset_Mask;
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440 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
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441 tmpreg |= RCC_PCLK2 << 3;
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443 /* Store the new value */
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444 RCC->CFGR = tmpreg;
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447 /*******************************************************************************
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448 * Function Name : RCC_ITConfig
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449 * Description : Enables or disables the specified RCC interrupts.
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450 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
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452 * This parameter can be any combination of the following values:
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453 * - RCC_IT_LSIRDY: LSI ready interrupt
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454 * - RCC_IT_LSERDY: LSE ready interrupt
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455 * - RCC_IT_HSIRDY: HSI ready interrupt
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456 * - RCC_IT_HSERDY: HSE ready interrupt
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457 * - RCC_IT_PLLRDY: PLL ready interrupt
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458 * - NewState: new state of the specified RCC interrupts.
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459 * This parameter can be: ENABLE or DISABLE.
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462 *******************************************************************************/
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463 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
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465 /* Check the parameters */
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466 assert(IS_RCC_IT(RCC_IT));
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467 assert(IS_FUNCTIONAL_STATE(NewState));
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469 if (NewState != DISABLE)
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471 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
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472 *(vu8 *) 0x40021009 |= RCC_IT;
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476 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
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477 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
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481 /*******************************************************************************
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482 * Function Name : RCC_USBCLKConfig
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483 * Description : Configures the USB clock (USBCLK).
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484 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
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485 * is derived from the PLL output.
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486 * This parameter can be one of the following values:
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487 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
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488 * selected as USB clock source
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489 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
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493 *******************************************************************************/
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494 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
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496 /* Check the parameters */
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497 assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
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499 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
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502 /*******************************************************************************
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503 * Function Name : RCC_ADCCLKConfig
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504 * Description : Configures the ADC clock (ADCCLK).
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505 * Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived
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506 * from the APB2 clock (PCLK2).
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507 * This parameter can be one of the following values:
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508 * - RCC_PCLK2_Div2: ADC clock = PCLK2/2
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509 * - RCC_PCLK2_Div4: ADC clock = PCLK2/4
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510 * - RCC_PCLK2_Div6: ADC clock = PCLK2/6
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511 * - RCC_PCLK2_Div8: ADC clock = PCLK2/8
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514 *******************************************************************************/
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515 void RCC_ADCCLKConfig(u32 RCC_ADCCLK)
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519 /* Check the parameters */
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520 assert(IS_RCC_ADCCLK(RCC_ADCCLK));
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522 tmpreg = RCC->CFGR;
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524 /* Clear ADCPRE[15:14] bits */
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525 tmpreg &= CFGR_ADCPRE_Reset_Mask;
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527 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
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528 tmpreg |= RCC_ADCCLK;
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530 /* Store the new value */
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531 RCC->CFGR = tmpreg;
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534 /*******************************************************************************
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535 * Function Name : RCC_LSEConfig
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536 * Description : Configures the External Low Speed oscillator (LSE).
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537 * Input : - RCC_LSE: specifies the new state of the LSE.
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538 * This parameter can be one of the following values:
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539 * - RCC_LSE_OFF: LSE oscillator OFF
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540 * - RCC_LSE_ON: LSE oscillator ON
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541 * - RCC_LSE_Bypass: LSE oscillator bypassed with external
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545 *******************************************************************************/
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546 void RCC_LSEConfig(u32 RCC_LSE)
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548 /* Check the parameters */
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549 assert(IS_RCC_LSE(RCC_LSE));
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551 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
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552 /* Reset LSEON bit */
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553 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
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555 /* Reset LSEBYP bit */
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556 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
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558 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
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562 /* Set LSEON bit */
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563 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
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566 case RCC_LSE_Bypass:
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567 /* Set LSEBYP and LSEON bits */
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568 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
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576 /*******************************************************************************
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577 * Function Name : RCC_LSICmd
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578 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
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579 * LSI can not be disabled if the IWDG is running.
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580 * Input : - NewState: new state of the LSI.
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581 * This parameter can be: ENABLE or DISABLE.
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584 *******************************************************************************/
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585 void RCC_LSICmd(FunctionalState NewState)
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587 /* Check the parameters */
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588 assert(IS_FUNCTIONAL_STATE(NewState));
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590 *(vu32 *) CSR_LSION_BB = (u32)NewState;
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593 /*******************************************************************************
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594 * Function Name : RCC_RTCCLKConfig
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595 * Description : Configures the RTC clock (RTCCLK).
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596 * Once the RTC clock is selected it can
\92t be changed unless the
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597 * Backup domain is reset.
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598 * Input : - RCC_RTCCLKSource: specifies the RTC clock source.
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599 * This parameter can be one of the following values:
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600 * - RCC_RTCCLKSource_LSE: LSE oscillator clock used as RTC
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602 * - RCC_RTCCLKSource_LSI: LSI oscillator clock used as RTC
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604 * - RCC_RTCCLKSource_HSE_Div128: HSE oscillator clock divided
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605 * by 128 used as RTC clock
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608 *******************************************************************************/
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609 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
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611 /* Check the parameters */
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612 assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
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614 /* Select the RTC clock source */
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615 RCC->BDCR |= RCC_RTCCLKSource;
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618 /*******************************************************************************
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619 * Function Name : RCC_RTCCLKCmd
\r
620 * Description : Enables or disables the RTC clock.
\r
621 * This function must be used only after the RTC clock was
\r
622 * selected using the RCC_RTCCLKConfig function.
\r
623 * Input : - NewState: new state of the RTC clock.
\r
624 * This parameter can be: ENABLE or DISABLE.
\r
627 *******************************************************************************/
\r
628 void RCC_RTCCLKCmd(FunctionalState NewState)
\r
630 /* Check the parameters */
\r
631 assert(IS_FUNCTIONAL_STATE(NewState));
\r
633 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
\r
636 /*******************************************************************************
\r
637 * Function Name : RCC_GetClocksFreq
\r
638 * Description : Returns the frequencies of different on chip clocks.
\r
639 * Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
\r
640 * will hold the clocks frequencies.
\r
643 *******************************************************************************/
\r
644 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
\r
646 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
\r
648 /* Get SYSCLK source -------------------------------------------------------*/
\r
649 tmp = RCC->CFGR & CFGR_SWS_Mask;
\r
653 case 0x00: /* HSI used as system clock */
\r
654 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\r
657 case 0x04: /* HSE used as system clock */
\r
658 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
\r
661 case 0x08: /* PLL used as system clock */
\r
662 /* Get PLL clock source and multiplication factor ----------------------*/
\r
663 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
\r
664 pllmull = ( pllmull >> 18) + 2;
\r
666 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
\r
668 if (pllsource == 0x00)
\r
669 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
\r
670 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
\r
673 {/* HSE selected as PLL clock entry */
\r
675 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
\r
676 {/* HSE oscillator clock divided by 2 */
\r
678 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
\r
682 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
\r
688 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\r
692 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
\r
693 /* Get HCLK prescaler */
\r
694 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
\r
696 presc = APBAHBPrescTable[tmp];
\r
698 /* HCLK clock frequency */
\r
699 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
\r
701 /* Get PCLK1 prescaler */
\r
702 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
\r
704 presc = APBAHBPrescTable[tmp];
\r
706 /* PCLK1 clock frequency */
\r
707 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
709 /* Get PCLK2 prescaler */
\r
710 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
\r
712 presc = APBAHBPrescTable[tmp];
\r
714 /* PCLK2 clock frequency */
\r
715 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
717 /* Get ADCCLK prescaler */
\r
718 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
\r
720 presc = ADCPrescTable[tmp];
\r
722 /* ADCCLK clock frequency */
\r
723 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
\r
726 /*******************************************************************************
\r
727 * Function Name : RCC_AHBPeriphClockCmd
\r
728 * Description : Enables or disables the AHB peripheral clock.
\r
729 * Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
\r
730 * This parameter can be any combination of the following values:
\r
731 * - RCC_AHBPeriph_DMA
\r
732 * - RCC_AHBPeriph_SRAM
\r
733 * - RCC_AHBPeriph_FLITF
\r
734 * SRAM and FLITF clock can be disabled only during sleep mode.
\r
735 * - NewState: new state of the specified peripheral clock.
\r
736 * This parameter can be: ENABLE or DISABLE.
\r
739 *******************************************************************************/
\r
740 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
\r
742 /* Check the parameters */
\r
743 assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
\r
744 assert(IS_FUNCTIONAL_STATE(NewState));
\r
746 if (NewState != DISABLE)
\r
748 RCC->AHBENR |= RCC_AHBPeriph;
\r
752 RCC->AHBENR &= ~RCC_AHBPeriph;
\r
756 /*******************************************************************************
\r
757 * Function Name : RCC_APB2PeriphClockCmd
\r
758 * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
\r
759 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
\r
761 * This parameter can be any combination of the following values:
\r
762 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
\r
763 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
\r
764 * RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
\r
765 * RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
\r
766 * - NewState: new state of the specified peripheral clock.
\r
767 * This parameter can be: ENABLE or DISABLE.
\r
770 *******************************************************************************/
\r
771 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
\r
773 /* Check the parameters */
\r
774 assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
775 assert(IS_FUNCTIONAL_STATE(NewState));
\r
777 if (NewState != DISABLE)
\r
779 RCC->APB2ENR |= RCC_APB2Periph;
\r
783 RCC->APB2ENR &= ~RCC_APB2Periph;
\r
787 /*******************************************************************************
\r
788 * Function Name : RCC_APB1PeriphClockCmd
\r
789 * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
\r
790 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
\r
792 * This parameter can be any combination of the following values:
\r
793 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
\r
794 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
\r
795 * RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
\r
796 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
\r
797 * RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
\r
798 * - NewState: new state of the specified peripheral clock.
\r
799 * This parameter can be: ENABLE or DISABLE.
\r
802 *******************************************************************************/
\r
803 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
\r
805 /* Check the parameters */
\r
806 assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
807 assert(IS_FUNCTIONAL_STATE(NewState));
\r
809 if (NewState != DISABLE)
\r
811 RCC->APB1ENR |= RCC_APB1Periph;
\r
815 RCC->APB1ENR &= ~RCC_APB1Periph;
\r
819 /*******************************************************************************
\r
820 * Function Name : RCC_APB2PeriphResetCmd
\r
821 * Description : Forces or releases High Speed APB (APB2) peripheral reset.
\r
822 * Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
\r
823 * This parameter can be any combination of the following values:
\r
824 * - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB
\r
825 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE
\r
826 * RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1
\r
827 * RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL
\r
828 * - NewState: new state of the specified peripheral reset.
\r
829 * This parameter can be: ENABLE or DISABLE.
\r
832 *******************************************************************************/
\r
833 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
\r
835 /* Check the parameters */
\r
836 assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
837 assert(IS_FUNCTIONAL_STATE(NewState));
\r
839 if (NewState != DISABLE)
\r
841 RCC->APB2RSTR |= RCC_APB2Periph;
\r
845 RCC->APB2RSTR &= ~RCC_APB2Periph;
\r
849 /*******************************************************************************
\r
850 * Function Name : RCC_APB1PeriphResetCmd
\r
851 * Description : Forces or releases Low Speed APB (APB1) peripheral reset.
\r
852 * Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
\r
853 * This parameter can be any combination of the following values:
\r
854 * - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4
\r
855 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2
\r
856 * RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2
\r
857 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP
\r
858 * RCC_APB1Periph_PWR, RCC_APB1Periph_ALL
\r
859 * - NewState: new state of the specified peripheral clock.
\r
860 * This parameter can be: ENABLE or DISABLE.
\r
863 *******************************************************************************/
\r
864 void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
\r
866 /* Check the parameters */
\r
867 assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
868 assert(IS_FUNCTIONAL_STATE(NewState));
\r
870 if (NewState != DISABLE)
\r
872 RCC->APB1RSTR |= RCC_APB1Periph;
\r
876 RCC->APB1RSTR &= ~RCC_APB1Periph;
\r
880 /*******************************************************************************
\r
881 * Function Name : RCC_BackupResetCmd
\r
882 * Description : Forces or releases the Backup domain reset.
\r
883 * Input : - NewState: new state of the Backup domain reset.
\r
884 * This parameter can be: ENABLE or DISABLE.
\r
887 *******************************************************************************/
\r
888 void RCC_BackupResetCmd(FunctionalState NewState)
\r
890 /* Check the parameters */
\r
891 assert(IS_FUNCTIONAL_STATE(NewState));
\r
893 *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
\r
896 /*******************************************************************************
\r
897 * Function Name : RCC_ClockSecuritySystemCmd
\r
898 * Description : Enables or disables the Clock Security System.
\r
899 * Input : - NewState: new state of the Clock Security System..
\r
900 * This parameter can be: ENABLE or DISABLE.
\r
903 *******************************************************************************/
\r
904 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
\r
906 /* Check the parameters */
\r
907 assert(IS_FUNCTIONAL_STATE(NewState));
\r
909 *(vu32 *) CR_CSSON_BB = (u32)NewState;
\r
912 /*******************************************************************************
\r
913 * Function Name : RCC_MCOConfig
\r
914 * Description : Selects the clock source to output on MCO pin.
\r
915 * Input : - RCC_MCO: specifies the clock source to output.
\r
916 * This parameter can be one of the following values:
\r
917 * - RCC_MCO_NoClock: No clock selected
\r
918 * - RCC_MCO_SYSCLK: System clock selected
\r
919 * - RCC_MCO_HSI: HSI oscillator clock selected
\r
920 * - RCC_MCO_HSE: HSE oscillator clock selected
\r
921 * - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
\r
924 *******************************************************************************/
\r
925 void RCC_MCOConfig(u8 RCC_MCO)
\r
927 /* Check the parameters */
\r
928 assert(IS_RCC_MCO(RCC_MCO));
\r
930 /* Perform Byte access to MCO[26:24] bits to select the MCO source */
\r
931 *(vu8 *) 0x40021007 = RCC_MCO;
\r
934 /*******************************************************************************
\r
935 * Function Name : RCC_GetFlagStatus
\r
936 * Description : Checks whether the specified RCC flag is set or not.
\r
937 * Input : - RCC_FLAG: specifies the flag to check.
\r
938 * This parameter can be one of the following values:
\r
939 * - RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
940 * - RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
941 * - RCC_FLAG_PLLRDY: PLL clock ready
\r
942 * - RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
943 * - RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
944 * - RCC_FLAG_PINRST: Pin reset
\r
945 * - RCC_FLAG_PORRST: POR/PDR reset
\r
946 * - RCC_FLAG_SFTRST: Software reset
\r
947 * - RCC_FLAG_IWDGRST: Independent Watchdog reset
\r
948 * - RCC_FLAG_WWDGRST: Window Watchdog reset
\r
949 * - RCC_FLAG_LPWRRST: Low Power reset
\r
951 * Return : The new state of RCC_FLAG (SET or RESET).
\r
952 *******************************************************************************/
\r
953 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
\r
957 FlagStatus bitstatus = RESET;
\r
959 /* Check the parameters */
\r
960 assert(IS_RCC_FLAG(RCC_FLAG));
\r
962 /* Get the RCC register index */
\r
963 tmp = RCC_FLAG >> 5;
\r
965 if (tmp == 1) /* The flag to check is in CR register */
\r
967 statusreg = RCC->CR;
\r
969 else if (tmp == 2) /* The flag to check is in BDCR register */
\r
971 statusreg = RCC->BDCR;
\r
973 else /* The flag to check is in CSR register */
\r
975 statusreg = RCC->CSR;
\r
978 /* Get the flag position */
\r
979 tmp = RCC_FLAG & FLAG_Mask;
\r
981 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
\r
990 /* Return the flag status */
\r
994 /*******************************************************************************
\r
995 * Function Name : RCC_ClearFlag
\r
996 * Description : Clears the RCC reset flags.
\r
997 * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
\r
998 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
\r
1003 *******************************************************************************/
\r
1004 void RCC_ClearFlag(void)
\r
1006 /* Set RVMF bit to clear the reset flags */
\r
1007 RCC->CSR |= CSR_RVMF_Set;
\r
1010 /*******************************************************************************
\r
1011 * Function Name : RCC_GetITStatus
\r
1012 * Description : Checks whether the specified RCC interrupt has occurred or not.
\r
1013 * Input : - RCC_IT: specifies the RCC interrupt source to check.
\r
1014 * This parameter can be one of the following values:
\r
1015 * - RCC_IT_LSIRDY: LSI ready interrupt
\r
1016 * - RCC_IT_LSERDY: LSE ready interrupt
\r
1017 * - RCC_IT_HSIRDY: HSI ready interrupt
\r
1018 * - RCC_IT_HSERDY: HSE ready interrupt
\r
1019 * - RCC_IT_PLLRDY: PLL ready interrupt
\r
1020 * - RCC_IT_CSS: Clock Security System interrupt
\r
1022 * Return : The new state of RCC_IT (SET or RESET).
\r
1023 *******************************************************************************/
\r
1024 ITStatus RCC_GetITStatus(u8 RCC_IT)
\r
1026 ITStatus bitstatus = RESET;
\r
1028 /* Check the parameters */
\r
1029 assert(IS_RCC_GET_IT(RCC_IT));
\r
1031 /* Check the status of the specified RCC interrupt */
\r
1032 if ((RCC->CIR & RCC_IT) != (u32)RESET)
\r
1038 bitstatus = RESET;
\r
1041 /* Return the RCC_IT status */
\r
1045 /*******************************************************************************
\r
1046 * Function Name : RCC_ClearITPendingBit
\r
1047 * Description : Clears the RCC
\92s interrupt pending bits.
\r
1048 * Input : - RCC_IT: specifies the interrupt pending bit to clear.
\r
1049 * This parameter can be any combination of the following values:
\r
1050 * - RCC_IT_LSIRDY: LSI ready interrupt
\r
1051 * - RCC_IT_LSERDY: LSE ready interrupt
\r
1052 * - RCC_IT_HSIRDY: HSI ready interrupt
\r
1053 * - RCC_IT_HSERDY: HSE ready interrupt
\r
1054 * - RCC_IT_PLLRDY: PLL ready interrupt
\r
1055 * - RCC_IT_CSS: Clock Security System interrupt
\r
1058 *******************************************************************************/
\r
1059 void RCC_ClearITPendingBit(u8 RCC_IT)
\r
1061 /* Check the parameters */
\r
1062 assert(IS_RCC_CLEAR_IT(RCC_IT));
\r
1064 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
\r
1066 *(vu8 *) 0x4002100A = RCC_IT;
\r
1069 /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
\r