2 ******************************************************************************
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3 * @file stm32f10x_sdio.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the SDIO firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_sdio.h"
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23 #include "stm32f10x_rcc.h"
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25 /** @addtogroup StdPeriph_Driver
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30 * @brief SDIO driver modules
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34 /** @defgroup SDIO_Private_TypesDefinitions
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38 /* ------------ SDIO registers bit address in the alias region ----------- */
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39 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
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41 /* --- CLKCR Register ---*/
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43 /* Alias word address of CLKEN bit */
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44 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
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45 #define CLKEN_BitNumber 0x08
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46 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
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48 /* --- CMD Register ---*/
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50 /* Alias word address of SDIOSUSPEND bit */
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51 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
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52 #define SDIOSUSPEND_BitNumber 0x0B
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53 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
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55 /* Alias word address of ENCMDCOMPL bit */
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56 #define ENCMDCOMPL_BitNumber 0x0C
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57 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
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59 /* Alias word address of NIEN bit */
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60 #define NIEN_BitNumber 0x0D
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61 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
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63 /* Alias word address of ATACMD bit */
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64 #define ATACMD_BitNumber 0x0E
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65 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
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67 /* --- DCTRL Register ---*/
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69 /* Alias word address of DMAEN bit */
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70 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
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71 #define DMAEN_BitNumber 0x03
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72 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
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74 /* Alias word address of RWSTART bit */
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75 #define RWSTART_BitNumber 0x08
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76 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
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78 /* Alias word address of RWSTOP bit */
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79 #define RWSTOP_BitNumber 0x09
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80 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
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82 /* Alias word address of RWMOD bit */
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83 #define RWMOD_BitNumber 0x0A
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84 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
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86 /* Alias word address of SDIOEN bit */
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87 #define SDIOEN_BitNumber 0x0B
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88 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
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90 /* ---------------------- SDIO registers bit mask ------------------------ */
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92 /* --- CLKCR Register ---*/
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94 /* CLKCR register clear mask */
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95 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
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97 /* --- PWRCTRL Register ---*/
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99 /* SDIO PWRCTRL Mask */
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100 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
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102 /* --- DCTRL Register ---*/
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104 /* SDIO DCTRL Clear Mask */
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105 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
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107 /* --- CMD Register ---*/
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109 /* CMD Register clear mask */
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110 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
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112 /* SDIO RESP Registers Address */
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113 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
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119 /** @defgroup SDIO_Private_Defines
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127 /** @defgroup SDIO_Private_Macros
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135 /** @defgroup SDIO_Private_Variables
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143 /** @defgroup SDIO_Private_FunctionPrototypes
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151 /** @defgroup SDIO_Private_Functions
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156 * @brief Deinitializes the SDIO peripheral registers to their default
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161 void SDIO_DeInit(void)
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163 SDIO->POWER = 0x00000000;
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164 SDIO->CLKCR = 0x00000000;
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165 SDIO->ARG = 0x00000000;
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166 SDIO->CMD = 0x00000000;
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167 SDIO->DTIMER = 0x00000000;
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168 SDIO->DLEN = 0x00000000;
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169 SDIO->DCTRL = 0x00000000;
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170 SDIO->ICR = 0x00C007FF;
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171 SDIO->MASK = 0x00000000;
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175 * @brief Initializes the SDIO peripheral according to the specified
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176 * parameters in the SDIO_InitStruct.
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177 * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
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178 * that contains the configuration information for the SDIO
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182 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
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184 uint32_t tmpreg = 0;
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186 /* Check the parameters */
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187 assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
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188 assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
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189 assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
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190 assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
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191 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
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193 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
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194 /* Get the SDIO CLKCR value */
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195 tmpreg = SDIO->CLKCR;
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197 /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
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198 tmpreg &= CLKCR_CLEAR_MASK;
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200 /* Set CLKDIV bits according to SDIO_ClockDiv value */
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201 /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
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202 /* Set BYPASS bit according to SDIO_ClockBypass value */
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203 /* Set WIDBUS bits according to SDIO_BusWide value */
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204 /* Set NEGEDGE bits according to SDIO_ClockEdge value */
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205 /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
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206 tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
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207 SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
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208 SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
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210 /* Write to SDIO CLKCR */
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211 SDIO->CLKCR = tmpreg;
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215 * @brief Fills each SDIO_InitStruct member with its default value.
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216 * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
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217 * will be initialized.
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220 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
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222 /* SDIO_InitStruct members default value */
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223 SDIO_InitStruct->SDIO_ClockDiv = 0x00;
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224 SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
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225 SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
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226 SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
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227 SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
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228 SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
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232 * @brief Enables or disables the SDIO Clock.
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233 * @param NewState: new state of the SDIO Clock.
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234 * This parameter can be: ENABLE or DISABLE.
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237 void SDIO_ClockCmd(FunctionalState NewState)
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239 /* Check the parameters */
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240 assert_param(IS_FUNCTIONAL_STATE(NewState));
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242 *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
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246 * @brief Sets the power status of the controller.
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247 * @param SDIO_PowerState: new state of the Power state.
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248 * This parameter can be one of the following values:
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249 * @arg SDIO_PowerState_OFF
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250 * @arg SDIO_PowerState_ON
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253 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
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255 /* Check the parameters */
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256 assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
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258 SDIO->POWER &= PWR_PWRCTRL_MASK;
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259 SDIO->POWER |= SDIO_PowerState;
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263 * @brief Gets the power status of the controller.
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265 * @retval : Power status of the controller. The returned value can
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266 * be one of the following:
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267 * - 0x00: Power OFF
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269 * - 0x03: Power ON
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271 uint32_t SDIO_GetPowerState(void)
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273 return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
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277 * @brief Enables or disables the SDIO interrupts.
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278 * @param SDIO_IT: specifies the SDIO interrupt sources to be
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279 * enabled or disabled.
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280 * This parameter can be one or a combination of the following values:
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281 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
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282 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
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283 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
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284 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
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285 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
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286 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
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287 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
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288 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
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289 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
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290 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
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291 * bus mode interrupt
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292 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
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293 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
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294 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
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295 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
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296 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
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297 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
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298 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
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299 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
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300 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
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301 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
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302 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
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303 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
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304 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
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305 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
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307 * @param NewState: new state of the specified SDIO interrupts.
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308 * This parameter can be: ENABLE or DISABLE.
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311 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
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313 /* Check the parameters */
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314 assert_param(IS_SDIO_IT(SDIO_IT));
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315 assert_param(IS_FUNCTIONAL_STATE(NewState));
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317 if (NewState != DISABLE)
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319 /* Enable the SDIO interrupts */
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320 SDIO->MASK |= SDIO_IT;
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324 /* Disable the SDIO interrupts */
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325 SDIO->MASK &= ~SDIO_IT;
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330 * @brief Enables or disables the SDIO DMA request.
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331 * @param NewState: new state of the selected SDIO DMA request.
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332 * This parameter can be: ENABLE or DISABLE.
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335 void SDIO_DMACmd(FunctionalState NewState)
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337 /* Check the parameters */
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338 assert_param(IS_FUNCTIONAL_STATE(NewState));
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340 *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
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344 * @brief Initializes the SDIO Command according to the specified
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345 * parameters in the SDIO_CmdInitStruct and send the command.
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346 * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
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347 * structure that contains the configuration information
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348 * for the SDIO command.
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351 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
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353 uint32_t tmpreg = 0;
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355 /* Check the parameters */
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356 assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
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357 assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
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358 assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
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359 assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
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361 /*---------------------------- SDIO ARG Configuration ------------------------*/
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362 /* Set the SDIO Argument value */
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363 SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
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365 /*---------------------------- SDIO CMD Configuration ------------------------*/
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366 /* Get the SDIO CMD value */
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367 tmpreg = SDIO->CMD;
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368 /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
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369 tmpreg &= CMD_CLEAR_MASK;
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370 /* Set CMDINDEX bits according to SDIO_CmdIndex value */
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371 /* Set WAITRESP bits according to SDIO_Response value */
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372 /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
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373 /* Set CPSMEN bits according to SDIO_CPSM value */
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374 tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
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375 | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
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377 /* Write to SDIO CMD */
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378 SDIO->CMD = tmpreg;
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382 * @brief Fills each SDIO_CmdInitStruct member with its default value.
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383 * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
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384 * structure which will be initialized.
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387 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
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389 /* SDIO_CmdInitStruct members default value */
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390 SDIO_CmdInitStruct->SDIO_Argument = 0x00;
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391 SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
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392 SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
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393 SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
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394 SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
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398 * @brief Returns command index of last command for which response
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401 * @retval : Returns the command index of the last command response received.
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403 uint8_t SDIO_GetCommandResponse(void)
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405 return (uint8_t)(SDIO->RESPCMD);
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409 * @brief Returns response received from the card for the last command.
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410 * @param SDIO_RESP: Specifies the SDIO response register.
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411 * This parameter can be one of the following values:
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412 * @arg SDIO_RESP1: Response Register 1
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413 * @arg SDIO_RESP2: Response Register 2
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414 * @arg SDIO_RESP3: Response Register 3
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415 * @arg SDIO_RESP4: Response Register 4
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416 * @retval : The Corresponding response register value.
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418 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
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420 /* Check the parameters */
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421 assert_param(IS_SDIO_RESP(SDIO_RESP));
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423 return (*(__IO uint32_t *)(SDIO_RESP_ADDR + SDIO_RESP));
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427 * @brief Initializes the SDIO data path according to the specified
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428 * parameters in the SDIO_DataInitStruct.
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429 * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef
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430 * structure that contains the configuration information
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431 * for the SDIO command.
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434 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
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436 uint32_t tmpreg = 0;
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438 /* Check the parameters */
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439 assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
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440 assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
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441 assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
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442 assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
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443 assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
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445 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
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446 /* Set the SDIO Data TimeOut value */
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447 SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
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449 /*---------------------------- SDIO DLEN Configuration -----------------------*/
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450 /* Set the SDIO DataLength value */
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451 SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
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453 /*---------------------------- SDIO DCTRL Configuration ----------------------*/
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454 /* Get the SDIO DCTRL value */
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455 tmpreg = SDIO->DCTRL;
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456 /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
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457 tmpreg &= DCTRL_CLEAR_MASK;
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458 /* Set DEN bit according to SDIO_DPSM value */
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459 /* Set DTMODE bit according to SDIO_TransferMode value */
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460 /* Set DTDIR bit according to SDIO_TransferDir value */
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461 /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
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462 tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
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463 | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
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465 /* Write to SDIO DCTRL */
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466 SDIO->DCTRL = tmpreg;
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470 * @brief Fills each SDIO_DataInitStruct member with its default value.
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471 * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef
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472 * structure which will be initialized.
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475 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
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477 /* SDIO_DataInitStruct members default value */
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478 SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
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479 SDIO_DataInitStruct->SDIO_DataLength = 0x00;
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480 SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
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481 SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
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482 SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
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483 SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
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487 * @brief Returns number of remaining data bytes to be transferred.
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489 * @retval : Number of remaining data bytes to be transferred
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491 uint32_t SDIO_GetDataCounter(void)
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493 return SDIO->DCOUNT;
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497 * @brief Read one data word from Rx FIFO.
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499 * @retval : Data received
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501 uint32_t SDIO_ReadData(void)
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507 * @brief Write one data word to Tx FIFO.
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508 * @param Data: 32-bit data word to write.
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511 void SDIO_WriteData(uint32_t Data)
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517 * @brief Returns the number of words left to be written to or read
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520 * @retval : Remaining number of words.
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522 uint32_t SDIO_GetFIFOCount(void)
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524 return SDIO->FIFOCNT;
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528 * @brief Starts the SD I/O Read Wait operation.
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529 * @param NewState: new state of the Start SDIO Read Wait operation.
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530 * This parameter can be: ENABLE or DISABLE.
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533 void SDIO_StartSDIOReadWait(FunctionalState NewState)
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535 /* Check the parameters */
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536 assert_param(IS_FUNCTIONAL_STATE(NewState));
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538 *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
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542 * @brief Stops the SD I/O Read Wait operation.
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543 * @param NewState: new state of the Stop SDIO Read Wait operation.
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544 * This parameter can be: ENABLE or DISABLE.
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547 void SDIO_StopSDIOReadWait(FunctionalState NewState)
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549 /* Check the parameters */
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550 assert_param(IS_FUNCTIONAL_STATE(NewState));
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552 *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
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556 * @brief Sets one of the two options of inserting read wait interval.
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557 * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
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558 * This parametre can be:
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559 * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
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560 * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
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563 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
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565 /* Check the parameters */
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566 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
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568 *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
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572 * @brief Enables or disables the SD I/O Mode Operation.
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573 * @param NewState: new state of SDIO specific operation.
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574 * This parameter can be: ENABLE or DISABLE.
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577 void SDIO_SetSDIOOperation(FunctionalState NewState)
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579 /* Check the parameters */
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580 assert_param(IS_FUNCTIONAL_STATE(NewState));
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582 *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
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586 * @brief Enables or disables the SD I/O Mode suspend command sending.
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587 * @param NewState: new state of the SD I/O Mode suspend command.
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588 * This parameter can be: ENABLE or DISABLE.
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591 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
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593 /* Check the parameters */
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594 assert_param(IS_FUNCTIONAL_STATE(NewState));
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596 *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
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600 * @brief Enables or disables the command completion signal.
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601 * @param NewState: new state of command completion signal.
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602 * This parameter can be: ENABLE or DISABLE.
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605 void SDIO_CommandCompletionCmd(FunctionalState NewState)
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607 /* Check the parameters */
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608 assert_param(IS_FUNCTIONAL_STATE(NewState));
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610 *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
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614 * @brief Enables or disables the CE-ATA interrupt.
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615 * @param NewState: new state of CE-ATA interrupt.
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616 * This parameter can be: ENABLE or DISABLE.
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619 void SDIO_CEATAITCmd(FunctionalState NewState)
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621 /* Check the parameters */
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622 assert_param(IS_FUNCTIONAL_STATE(NewState));
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624 *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
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628 * @brief Sends CE-ATA command (CMD61).
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629 * @param NewState: new state of CE-ATA command.
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630 * This parameter can be: ENABLE or DISABLE.
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633 void SDIO_SendCEATACmd(FunctionalState NewState)
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635 /* Check the parameters */
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636 assert_param(IS_FUNCTIONAL_STATE(NewState));
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638 *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
\r
642 * @brief Checks whether the specified SDIO flag is set or not.
\r
643 * @param SDIO_FLAG: specifies the flag to check.
\r
644 * This parameter can be one of the following values:
\r
645 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
\r
646 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
\r
647 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
\r
648 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
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649 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
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650 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
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651 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
\r
652 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
\r
653 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
\r
654 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
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656 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
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657 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
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658 * @arg SDIO_FLAG_TXACT: Data transmit in progress
\r
659 * @arg SDIO_FLAG_RXACT: Data receive in progress
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660 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
\r
661 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
\r
662 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
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663 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
\r
664 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
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665 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
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666 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
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667 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
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668 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
\r
669 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
\r
670 * @retval : The new state of SDIO_FLAG (SET or RESET).
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672 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
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674 FlagStatus bitstatus = RESET;
\r
676 /* Check the parameters */
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677 assert_param(IS_SDIO_FLAG(SDIO_FLAG));
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679 if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
\r
691 * @brief Clears the SDIO's pending flags.
\r
692 * @param SDIO_FLAG: specifies the flag to clear.
\r
693 * This parameter can be one or a combination of the following values:
\r
694 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
\r
695 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
\r
696 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
\r
697 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
\r
698 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
\r
699 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
\r
700 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
\r
701 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
\r
702 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
\r
703 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
\r
705 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
\r
706 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
\r
707 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
\r
710 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
\r
712 /* Check the parameters */
\r
713 assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
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715 SDIO->ICR = SDIO_FLAG;
\r
719 * @brief Checks whether the specified SDIO interrupt has occurred or not.
\r
720 * @param SDIO_IT: specifies the SDIO interrupt source to check.
\r
721 * This parameter can be one of the following values:
\r
722 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
723 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
724 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
725 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
726 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
727 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
728 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
729 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
730 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
731 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
732 * bus mode interrupt
\r
733 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
734 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
\r
735 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
\r
736 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
\r
737 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
738 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
739 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
\r
740 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
\r
741 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
742 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
\r
743 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
744 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
\r
745 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
746 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
\r
748 * @retval : The new state of SDIO_IT (SET or RESET).
\r
750 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
\r
752 ITStatus bitstatus = RESET;
\r
754 /* Check the parameters */
\r
755 assert_param(IS_SDIO_GET_IT(SDIO_IT));
\r
756 if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
\r
768 * @brief Clears the SDIO
\92s interrupt pending bits.
\r
769 * @param SDIO_IT: specifies the interrupt pending bit to clear.
\r
770 * This parameter can be one or a combination of the following values:
\r
771 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
772 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
773 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
774 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
775 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
776 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
777 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
778 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
779 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
780 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
781 * bus mode interrupt
\r
782 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
783 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
\r
786 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
\r
788 /* Check the parameters */
\r
789 assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
\r
791 SDIO->ICR = SDIO_IT;
\r
806 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
\r