2 ******************************************************************************
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3 * @file stm32l1xx_rcc.h
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4 * @author MCD Application Team
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7 * @brief This file contains all the functions prototypes for the RCC
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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22 /* Define to prevent recursive inclusion -------------------------------------*/
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23 #ifndef __STM32L1xx_RCC_H
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24 #define __STM32L1xx_RCC_H
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30 /* Includes ------------------------------------------------------------------*/
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31 #include "stm32l1xx.h"
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33 /** @addtogroup STM32L1xx_StdPeriph_Driver
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41 /** @defgroup RCC_Exported_Types
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47 uint32_t SYSCLK_Frequency;
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48 uint32_t HCLK_Frequency;
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49 uint32_t PCLK1_Frequency;
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50 uint32_t PCLK2_Frequency;
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57 /** @defgroup RCC_Exported_Constants
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61 /** @defgroup HSE_configuration
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65 #define RCC_HSE_OFF ((uint8_t)0x00)
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66 #define RCC_HSE_ON ((uint8_t)0x01)
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67 #define RCC_HSE_Bypass ((uint8_t)0x05)
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68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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69 ((HSE) == RCC_HSE_Bypass))
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75 /** @defgroup MSI_Clock_Range
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79 #define RCC_MSIRange_64KHz RCC_ICSCR_MSIRANGE_64KHz
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80 #define RCC_MSIRange_128KHz RCC_ICSCR_MSIRANGE_128KHz
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81 #define RCC_MSIRange_256KHz RCC_ICSCR_MSIRANGE_256KHz
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82 #define RCC_MSIRange_512KHz RCC_ICSCR_MSIRANGE_512KHz
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83 #define RCC_MSIRange_1MHz RCC_ICSCR_MSIRANGE_1MHz
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84 #define RCC_MSIRange_2MHz RCC_ICSCR_MSIRANGE_2MHz
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85 #define RCC_MSIRange_4MHz RCC_ICSCR_MSIRANGE_4MHz
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87 #define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) || \
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88 ((RANGE) == RCC_MSIRange_128KHz) || \
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89 ((RANGE) == RCC_MSIRange_256KHz) || \
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90 ((RANGE) == RCC_MSIRange_512KHz) || \
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91 ((RANGE) == RCC_MSIRange_1MHz) || \
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92 ((RANGE) == RCC_MSIRange_2MHz) || \
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93 ((RANGE) == RCC_MSIRange_4MHz))
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99 /** @defgroup PLL_Clock_Source
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103 #define RCC_PLLSource_HSI ((uint8_t)0x00)
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104 #define RCC_PLLSource_HSE ((uint8_t)0x01)
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106 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
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107 ((SOURCE) == RCC_PLLSource_HSE))
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112 /** @defgroup PLL_Multiplication_Factor
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116 #define RCC_PLLMul_3 ((uint8_t)0x00)
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117 #define RCC_PLLMul_4 ((uint8_t)0x04)
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118 #define RCC_PLLMul_6 ((uint8_t)0x08)
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119 #define RCC_PLLMul_8 ((uint8_t)0x0C)
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120 #define RCC_PLLMul_12 ((uint8_t)0x10)
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121 #define RCC_PLLMul_16 ((uint8_t)0x14)
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122 #define RCC_PLLMul_24 ((uint8_t)0x18)
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123 #define RCC_PLLMul_32 ((uint8_t)0x1C)
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124 #define RCC_PLLMul_48 ((uint8_t)0x20)
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127 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
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128 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
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129 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
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130 ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
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131 ((MUL) == RCC_PLLMul_48))
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136 /** @defgroup PLL_Divider_Factor
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140 #define RCC_PLLDiv_2 ((uint8_t)0x40)
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141 #define RCC_PLLDiv_3 ((uint8_t)0x80)
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142 #define RCC_PLLDiv_4 ((uint8_t)0xC0)
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145 #define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
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146 ((DIV) == RCC_PLLDiv_4))
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151 /** @defgroup System_Clock_Source
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155 #define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
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156 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
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157 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
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158 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
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159 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \
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160 ((SOURCE) == RCC_SYSCLKSource_HSI) || \
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161 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
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162 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
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167 /** @defgroup AHB_Clock_Source
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171 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
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172 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
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173 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
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174 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
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175 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
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176 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
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177 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
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178 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
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179 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
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180 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
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181 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
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182 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
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183 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
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184 ((HCLK) == RCC_SYSCLK_Div512))
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189 /** @defgroup APB1_APB2_Clock_Source
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193 #define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
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194 #define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
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195 #define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
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196 #define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
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197 #define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
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198 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
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199 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
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200 ((PCLK) == RCC_HCLK_Div16))
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206 /** @defgroup RCC_Interrupt_Source
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210 #define RCC_IT_LSIRDY ((uint8_t)0x01)
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211 #define RCC_IT_LSERDY ((uint8_t)0x02)
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212 #define RCC_IT_HSIRDY ((uint8_t)0x04)
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213 #define RCC_IT_HSERDY ((uint8_t)0x08)
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214 #define RCC_IT_PLLRDY ((uint8_t)0x10)
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215 #define RCC_IT_MSIRDY ((uint8_t)0x20)
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216 #define RCC_IT_CSS ((uint8_t)0x80)
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218 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
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220 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
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221 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
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222 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
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223 ((IT) == RCC_IT_CSS))
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225 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
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231 /** @defgroup LSE_Configuration
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235 #define RCC_LSE_OFF ((uint8_t)0x00)
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236 #define RCC_LSE_ON ((uint8_t)0x01)
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237 #define RCC_LSE_Bypass ((uint8_t)0x05)
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238 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
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239 ((LSE) == RCC_LSE_Bypass))
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244 /** @defgroup RTC_Clock_Source
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248 #define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
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249 #define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI
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250 #define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
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251 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
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252 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
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253 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
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254 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
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255 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
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256 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
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257 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
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258 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
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259 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
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264 /** @defgroup AHB_Peripherals
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268 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
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269 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
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270 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
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271 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
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272 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
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273 #define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
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274 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
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275 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
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276 #define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN
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277 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
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279 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))
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280 #define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))
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286 /** @defgroup APB2_Peripherals
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290 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
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291 #define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
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292 #define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
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293 #define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
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294 #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
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295 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
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296 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
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298 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))
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303 /** @defgroup APB1_Peripherals
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307 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
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308 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
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309 #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
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310 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
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311 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
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312 #define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
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313 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
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314 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
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315 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
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316 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
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317 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
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318 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
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319 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
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320 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
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321 #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
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322 #define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
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324 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))
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329 /** @defgroup MCO_Clock_Source
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333 #define RCC_MCOSource_NoClock ((uint8_t)0x00)
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334 #define RCC_MCOSource_SYSCLK ((uint8_t)0x01)
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335 #define RCC_MCOSource_HSI ((uint8_t)0x02)
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336 #define RCC_MCOSource_MSI ((uint8_t)0x03)
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337 #define RCC_MCOSource_HSE ((uint8_t)0x04)
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338 #define RCC_MCOSource_PLLCLK ((uint8_t)0x05)
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339 #define RCC_MCOSource_LSI ((uint8_t)0x06)
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340 #define RCC_MCOSource_LSE ((uint8_t)0x07)
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342 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
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343 ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \
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344 ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
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345 ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
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350 /** @defgroup MCO_Output_Divider
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354 #define RCC_MCODiv_1 ((uint8_t)0x00)
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355 #define RCC_MCODiv_2 ((uint8_t)0x10)
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356 #define RCC_MCODiv_4 ((uint8_t)0x20)
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357 #define RCC_MCODiv_8 ((uint8_t)0x30)
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358 #define RCC_MCODiv_16 ((uint8_t)0x40)
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360 #define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
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361 ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \
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362 ((DIV) == RCC_MCODiv_16))
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367 /** @defgroup RCC_Flag
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371 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
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372 #define RCC_FLAG_MSIRDY ((uint8_t)0x29)
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373 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
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374 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
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375 #define RCC_FLAG_LSERDY ((uint8_t)0x49)
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376 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
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377 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
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378 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
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379 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
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380 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
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381 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
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382 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
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383 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
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385 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
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386 ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
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387 ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
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388 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
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389 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
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390 ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
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391 ((FLAG) == RCC_FLAG_WWDGRST))
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393 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
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394 #define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
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404 /** @defgroup RCC_Exported_Macros
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412 /** @defgroup RCC_Exported_Functions
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416 void RCC_DeInit(void);
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417 void RCC_HSEConfig(uint8_t RCC_HSE);
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418 ErrorStatus RCC_WaitForHSEStartUp(void);
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419 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
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420 void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
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421 void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
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422 void RCC_MSICmd(FunctionalState NewState);
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423 void RCC_HSICmd(FunctionalState NewState);
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424 void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
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425 void RCC_PLLCmd(FunctionalState NewState);
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426 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
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427 uint8_t RCC_GetSYSCLKSource(void);
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428 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
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429 void RCC_PCLK1Config(uint32_t RCC_HCLK);
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430 void RCC_PCLK2Config(uint32_t RCC_HCLK);
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431 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
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432 void RCC_LSEConfig(uint8_t RCC_LSE);
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433 void RCC_LSICmd(FunctionalState NewState);
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434 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
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435 void RCC_RTCCLKCmd(FunctionalState NewState);
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436 void RCC_RTCResetCmd(FunctionalState NewState);
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437 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
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438 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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439 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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440 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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441 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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442 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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443 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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444 void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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445 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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446 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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447 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
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448 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
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449 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
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450 void RCC_ClearFlag(void);
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451 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
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452 void RCC_ClearITPendingBit(uint8_t RCC_IT);
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458 #endif /* __STM32L1xx_RCC_H */
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471 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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